hw/ppce500_mpc8544ds.c

   1 /*
   2  * QEMU PowerPC MPC8544DS board emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc440_bamboo.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "config.h"
  18 #include "qemu-common.h"
  19 #include "net.h"
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "pci.h"
  23 #include "boards.h"
  24 #include "sysemu.h"
  25 #include "kvm.h"
  26 #include "kvm_ppc.h"
  27 #include "device_tree.h"
  28 #include "openpic.h"
  29 #include "ppc.h"
  30 #include "loader.h"
  31 #include "elf.h"
  32 #include "sysbus.h"
  33 #include "exec-memory.h"
  34 #include "host-utils.h"
  35
  36 #define BINARY_DEVICE_TREE_FILE    "mpc8544ds.dtb"
  37 #define UIMAGE_LOAD_BASE           0
  38 #define DTC_LOAD_PAD               0x500000
  39 #define DTC_PAD_MASK               0xFFFFF
  40 #define INITRD_LOAD_PAD            0x2000000
  41 #define INITRD_PAD_MASK            0xFFFFFF
  42
  43 #define RAM_SIZES_ALIGN            (64UL << 20)
  44
  45 #define MPC8544_CCSRBAR_BASE       0xE0000000
  46 #define MPC8544_MPIC_REGS_BASE     (MPC8544_CCSRBAR_BASE + 0x40000)
  47 #define MPC8544_SERIAL0_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4500)
  48 #define MPC8544_SERIAL1_REGS_BASE  (MPC8544_CCSRBAR_BASE + 0x4600)
  49 #define MPC8544_PCI_REGS_BASE      (MPC8544_CCSRBAR_BASE + 0x8000)
  50 #define MPC8544_PCI_REGS_SIZE      0x1000
  51 #define MPC8544_PCI_IO             0xE1000000
  52 #define MPC8544_PCI_IOLEN          0x10000
  53 #define MPC8544_UTIL_BASE          (MPC8544_CCSRBAR_BASE + 0xe0000)
  54 #define MPC8544_SPIN_BASE          0xEF000000
  55
  56 struct boot_info
  57 {
  58     uint32_t dt_base;
  59     uint32_t dt_size;
  60     uint32_t entry;
  61 };
  62
  63 static int mpc8544_load_device_tree(CPUPPCState *env,
  64                                     target_phys_addr_t addr,
  65                                     uint32_t ramsize,
  66                                     target_phys_addr_t initrd_base,
  67                                     target_phys_addr_t initrd_size,
  68                                     const char *kernel_cmdline)
  69 {
  70     int ret = -1;
  71 #ifdef CONFIG_FDT
  72     uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
  73     char *filename;
  74     int fdt_size;
  75     void *fdt;
  76     uint8_t hypercall[16];
  77     uint32_t clock_freq = 400000000;
  78     uint32_t tb_freq = 400000000;
  79     int i;
  80
  81     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
  82     if (!filename) {
  83         goto out;
  84     }
  85     fdt = load_device_tree(filename, &fdt_size);
  86     g_free(filename);
  87     if (fdt == NULL) {
  88         goto out;
  89     }
  90
  91     /* Manipulate device tree in memory. */
  92     ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
  93                                sizeof(mem_reg_property));
  94     if (ret < 0)
  95         fprintf(stderr, "couldn't set /memory/reg\n");
  96
  97     if (initrd_size) {
  98         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
  99                                         initrd_base);
 100         if (ret < 0) {
 101             fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
 102         }
 103
 104         ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
 105                                         (initrd_base + initrd_size));
 106         if (ret < 0) {
 107             fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
 108         }
 109     }
 110
 111     ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
 112                                       kernel_cmdline);
 113     if (ret < 0)
 114         fprintf(stderr, "couldn't set /chosen/bootargs\n");
 115
 116     if (kvm_enabled()) {
 117         /* Read out host's frequencies */
 118         clock_freq = kvmppc_get_clockfreq();
 119         tb_freq = kvmppc_get_tbfreq();
 120
 121         /* indicate KVM hypercall interface */
 122         qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
 123                                     "linux,kvm");
 124         kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
 125         qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
 126                              hypercall, sizeof(hypercall));
 127     }
 128
 129     /* We need to generate the cpu nodes in reverse order, so Linux can pick
 130        the first node as boot node and be happy */
 131     for (i = smp_cpus - 1; i >= 0; i--) {
 132         char cpu_name[128];
 133         uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
 134
 135         for (env = first_cpu; env != NULL; env = env->next_cpu) {
 136             if (env->cpu_index == i) {
 137                 break;
 138             }
 139         }
 140
 141         if (!env) {
 142             continue;
 143         }
 144
 145         snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
 146         qemu_devtree_add_subnode(fdt, cpu_name);
 147         qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
 148         qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
 149         qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
 150         qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
 151         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
 152                                   env->dcache_line_size);
 153         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
 154                                   env->icache_line_size);
 155         qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
 156         qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
 157         qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
 158         if (env->cpu_index) {
 159             qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
 160             qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
 161             qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
 162                                  &cpu_release_addr, sizeof(cpu_release_addr));
 163         } else {
 164             qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
 165         }
 166     }
 167
 168     ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
 169     if (ret < 0) {
 170         goto out;
 171     }
 172     g_free(fdt);
 173     ret = fdt_size;
 174
 175 out:
 176 #endif
 177
 178     return ret;
 179 }
 180
 181 /* Create -kernel TLB entries for BookE.  */
 182 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
 183 {
 184     return 63 - clz64(size >> 10);
 185 }
 186
 187 static void mmubooke_create_initial_mapping(CPUPPCState *env)
 188 {
 189     struct boot_info *bi = env->load_info;
 190     ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
 191     target_phys_addr_t size, dt_end;
 192     int ps;
 193
 194     /* Our initial TLB entry needs to cover everything from 0 to
 195        the device tree top */
 196     dt_end = bi->dt_base + bi->dt_size;
 197     ps = booke206_page_size_to_tlb(dt_end) + 1;
 198     size = (ps << MAS1_TSIZE_SHIFT);
 199     tlb->mas1 = MAS1_VALID | size;
 200     tlb->mas2 = 0;
 201     tlb->mas7_3 = 0;
 202     tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
 203
 204     env->tlb_dirty = true;
 205 }
 206
 207 static void mpc8544ds_cpu_reset_sec(void *opaque)
 208 {
 209     PowerPCCPU *cpu = opaque;
 210     CPUPPCState *env = &cpu->env;
 211
 212     cpu_reset(CPU(cpu));
 213
 214     /* Secondary CPU starts in halted state for now. Needs to change when
 215        implementing non-kernel boot. */
 216     env->halted = 1;
 217     env->exception_index = EXCP_HLT;
 218 }
 219
 220 static void mpc8544ds_cpu_reset(void *opaque)
 221 {
 222     PowerPCCPU *cpu = opaque;
 223     CPUPPCState *env = &cpu->env;
 224     struct boot_info *bi = env->load_info;
 225
 226     cpu_reset(CPU(cpu));
 227
 228     /* Set initial guest state. */
 229     env->halted = 0;
 230     env->gpr[1] = (16<<20) - 8;
 231     env->gpr[3] = bi->dt_base;
 232     env->nip = bi->entry;
 233     mmubooke_create_initial_mapping(env);
 234 }
 235
 236 static void mpc8544ds_init(ram_addr_t ram_size,
 237                          const char *boot_device,
 238                          const char *kernel_filename,
 239                          const char *kernel_cmdline,
 240                          const char *initrd_filename,
 241                          const char *cpu_model)
 242 {
 243     MemoryRegion *address_space_mem = get_system_memory();
 244     MemoryRegion *ram = g_new(MemoryRegion, 1);
 245     PCIBus *pci_bus;
 246     CPUPPCState *env = NULL;
 247     uint64_t elf_entry;
 248     uint64_t elf_lowaddr;
 249     target_phys_addr_t entry=0;
 250     target_phys_addr_t loadaddr=UIMAGE_LOAD_BASE;
 251     target_long kernel_size=0;
 252     target_ulong dt_base = 0;
 253     target_ulong initrd_base = 0;
 254     target_long initrd_size=0;
 255     int i=0;
 256     unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
 257     qemu_irq **irqs, *mpic;
 258     DeviceState *dev;
 259     CPUPPCState *firstenv = NULL;
 260
 261     /* Setup CPUs */
 262     if (cpu_model == NULL) {
 263         cpu_model = "e500v2_v30";
 264     }
 265
 266     irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
 267     irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
 268     for (i = 0; i < smp_cpus; i++) {
 269         PowerPCCPU *cpu;
 270         qemu_irq *input;
 271
 272         cpu = cpu_ppc_init(cpu_model);
 273         if (cpu == NULL) {
 274             fprintf(stderr, "Unable to initialize CPU!\n");
 275             exit(1);
 276         }
 277         env = &cpu->env;
 278
 279         if (!firstenv) {
 280             firstenv = env;
 281         }
 282
 283         irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
 284         input = (qemu_irq *)env->irq_inputs;
 285         irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
 286         irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
 287         env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
 288
 289         ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
 290
 291         /* Register reset handler */
 292         if (!i) {
 293             /* Primary CPU */
 294             struct boot_info *boot_info;
 295             boot_info = g_malloc0(sizeof(struct boot_info));
 296             qemu_register_reset(mpc8544ds_cpu_reset, cpu);
 297             env->load_info = boot_info;
 298         } else {
 299             /* Secondary CPUs */
 300             qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
 301         }
 302     }
 303
 304     env = firstenv;
 305
 306     /* Fixup Memory size on a alignment boundary */
 307     ram_size &= ~(RAM_SIZES_ALIGN - 1);
 308
 309     /* Register Memory */
 310     memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
 311     vmstate_register_ram_global(ram);
 312     memory_region_add_subregion(address_space_mem, 0, ram);
 313
 314     /* MPIC */
 315     mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
 316                      smp_cpus, irqs, NULL);
 317
 318     if (!mpic) {
 319         cpu_abort(env, "MPIC failed to initialize\n");
 320     }
 321
 322     /* Serial */
 323     if (serial_hds[0]) {
 324         serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
 325                        0, mpic[12+26], 399193,
 326                        serial_hds[0], DEVICE_BIG_ENDIAN);
 327     }
 328
 329     if (serial_hds[1]) {
 330         serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
 331                        0, mpic[12+26], 399193,
 332                        serial_hds[0], DEVICE_BIG_ENDIAN);
 333     }
 334
 335     /* General Utility device */
 336     sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
 337
 338     /* PCI */
 339     dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
 340                                 mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
 341                                 mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
 342                                 NULL);
 343     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 344     if (!pci_bus)
 345         printf("couldn't create PCI controller!\n");
 346
 347     isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
 348
 349     if (pci_bus) {
 350         /* Register network interfaces. */
 351         for (i = 0; i < nb_nics; i++) {
 352             pci_nic_init_nofail(&nd_table[i], "virtio", NULL);
 353         }
 354     }
 355
 356     /* Register spinning region */
 357     sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
 358
 359     /* Load kernel. */
 360     if (kernel_filename) {
 361         kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
 362         if (kernel_size < 0) {
 363             kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
 364                                    &elf_lowaddr, NULL, 1, ELF_MACHINE, 0);
 365             entry = elf_entry;
 366             loadaddr = elf_lowaddr;
 367         }
 368         /* XXX try again as binary */
 369         if (kernel_size < 0) {
 370             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 371                     kernel_filename);
 372             exit(1);
 373         }
 374     }
 375
 376     /* Load initrd. */
 377     if (initrd_filename) {
 378         initrd_base = (kernel_size + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
 379         initrd_size = load_image_targphys(initrd_filename, initrd_base,
 380                                           ram_size - initrd_base);
 381
 382         if (initrd_size < 0) {
 383             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 384                     initrd_filename);
 385             exit(1);
 386         }
 387     }
 388
 389     /* If we're loading a kernel directly, we must load the device tree too. */
 390     if (kernel_filename) {
 391         struct boot_info *boot_info;
 392         int dt_size;
 393
 394 #ifndef CONFIG_FDT
 395         cpu_abort(env, "Compiled without FDT support - can't load kernel\n");
 396 #endif
 397         dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
 398         dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base,
 399                                            initrd_size, kernel_cmdline);
 400         if (dt_size < 0) {
 401             fprintf(stderr, "couldn't load device tree\n");
 402             exit(1);
 403         }
 404
 405         boot_info = env->load_info;
 406         boot_info->entry = entry;
 407         boot_info->dt_base = dt_base;
 408         boot_info->dt_size = dt_size;
 409     }
 410
 411     if (kvm_enabled()) {
 412         kvmppc_init();
 413     }
 414 }
 415
 416 static QEMUMachine mpc8544ds_machine = {
 417     .name = "mpc8544ds",
 418     .desc = "mpc8544ds",
 419     .init = mpc8544ds_init,
 420     .max_cpus = 15,
 421 };
 422
 423 static void mpc8544ds_machine_init(void)
 424 {
 425     qemu_register_machine(&mpc8544ds_machine);
 426 }
 427
 428 machine_init(mpc8544ds_machine_init);