hw/ppce500_pci.c

   1 /*
   2  * QEMU PowerPC E500 embedded processors pci controller emulation
   3  *
   4  * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
   5  *
   6  * Author: Yu Liu,     <yu.liu@freescale.com>
   7  *
   8  * This file is derived from hw/ppc4xx_pci.c,
   9  * the copyright for that material belongs to the original owners.
  10  *
  11  * This is free software; you can redistribute it and/or modify
  12  * it under the terms of  the GNU General  Public License as published by
  13  * the Free Software Foundation;  either version 2 of the  License, or
  14  * (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw/ppc/e500-ccsr.h"
  19 #include "pci.h"
  20 #include "pci_host.h"
  21 #include "bswap.h"
  22
  23 #ifdef DEBUG_PCI
  24 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
  25 #else
  26 #define pci_debug(fmt, ...)
  27 #endif
  28
  29 #define PCIE500_CFGADDR       0x0
  30 #define PCIE500_CFGDATA       0x4
  31 #define PCIE500_REG_BASE      0xC00
  32 #define PCIE500_ALL_SIZE      0x1000
  33 #define PCIE500_REG_SIZE      (PCIE500_ALL_SIZE - PCIE500_REG_BASE)
  34
  35 #define PCIE500_PCI_IOLEN     0x10000ULL
  36
  37 #define PPCE500_PCI_CONFIG_ADDR         0x0
  38 #define PPCE500_PCI_CONFIG_DATA         0x4
  39 #define PPCE500_PCI_INTACK              0x8
  40
  41 #define PPCE500_PCI_OW1                 (0xC20 - PCIE500_REG_BASE)
  42 #define PPCE500_PCI_OW2                 (0xC40 - PCIE500_REG_BASE)
  43 #define PPCE500_PCI_OW3                 (0xC60 - PCIE500_REG_BASE)
  44 #define PPCE500_PCI_OW4                 (0xC80 - PCIE500_REG_BASE)
  45 #define PPCE500_PCI_IW3                 (0xDA0 - PCIE500_REG_BASE)
  46 #define PPCE500_PCI_IW2                 (0xDC0 - PCIE500_REG_BASE)
  47 #define PPCE500_PCI_IW1                 (0xDE0 - PCIE500_REG_BASE)
  48
  49 #define PPCE500_PCI_GASKET_TIMR         (0xE20 - PCIE500_REG_BASE)
  50
  51 #define PCI_POTAR               0x0
  52 #define PCI_POTEAR              0x4
  53 #define PCI_POWBAR              0x8
  54 #define PCI_POWAR               0x10
  55
  56 #define PCI_PITAR               0x0
  57 #define PCI_PIWBAR              0x8
  58 #define PCI_PIWBEAR             0xC
  59 #define PCI_PIWAR               0x10
  60
  61 #define PPCE500_PCI_NR_POBS     5
  62 #define PPCE500_PCI_NR_PIBS     3
  63
  64 struct  pci_outbound {
  65     uint32_t potar;
  66     uint32_t potear;
  67     uint32_t powbar;
  68     uint32_t powar;
  69 };
  70
  71 struct pci_inbound {
  72     uint32_t pitar;
  73     uint32_t piwbar;
  74     uint32_t piwbear;
  75     uint32_t piwar;
  76 };
  77
  78 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost"
  79
  80 #define PPC_E500_PCI_HOST_BRIDGE(obj) \
  81     OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE)
  82
  83 struct PPCE500PCIState {
  84     PCIHostState parent_obj;
  85
  86     struct pci_outbound pob[PPCE500_PCI_NR_POBS];
  87     struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
  88     uint32_t gasket_time;
  89     qemu_irq irq[4];
  90     uint32_t first_slot;
  91     /* mmio maps */
  92     MemoryRegion container;
  93     MemoryRegion iomem;
  94     MemoryRegion pio;
  95 };
  96
  97 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge"
  98 #define PPC_E500_PCI_BRIDGE(obj) \
  99     OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE)
 100
 101 struct PPCE500PCIBridgeState {
 102     /*< private >*/
 103     PCIDevice parent;
 104     /*< public >*/
 105
 106     MemoryRegion bar0;
 107 };
 108
 109 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState;
 110 typedef struct PPCE500PCIState PPCE500PCIState;
 111
 112 static uint64_t pci_reg_read4(void *opaque, hwaddr addr,
 113                               unsigned size)
 114 {
 115     PPCE500PCIState *pci = opaque;
 116     unsigned long win;
 117     uint32_t value = 0;
 118     int idx;
 119
 120     win = addr & 0xfe0;
 121
 122     switch (win) {
 123     case PPCE500_PCI_OW1:
 124     case PPCE500_PCI_OW2:
 125     case PPCE500_PCI_OW3:
 126     case PPCE500_PCI_OW4:
 127         idx = (addr >> 5) & 0x7;
 128         switch (addr & 0xC) {
 129         case PCI_POTAR:
 130             value = pci->pob[idx].potar;
 131             break;
 132         case PCI_POTEAR:
 133             value = pci->pob[idx].potear;
 134             break;
 135         case PCI_POWBAR:
 136             value = pci->pob[idx].powbar;
 137             break;
 138         case PCI_POWAR:
 139             value = pci->pob[idx].powar;
 140             break;
 141         default:
 142             break;
 143         }
 144         break;
 145
 146     case PPCE500_PCI_IW3:
 147     case PPCE500_PCI_IW2:
 148     case PPCE500_PCI_IW1:
 149         idx = ((addr >> 5) & 0x3) - 1;
 150         switch (addr & 0xC) {
 151         case PCI_PITAR:
 152             value = pci->pib[idx].pitar;
 153             break;
 154         case PCI_PIWBAR:
 155             value = pci->pib[idx].piwbar;
 156             break;
 157         case PCI_PIWBEAR:
 158             value = pci->pib[idx].piwbear;
 159             break;
 160         case PCI_PIWAR:
 161             value = pci->pib[idx].piwar;
 162             break;
 163         default:
 164             break;
 165         };
 166         break;
 167
 168     case PPCE500_PCI_GASKET_TIMR:
 169         value = pci->gasket_time;
 170         break;
 171
 172     default:
 173         break;
 174     }
 175
 176     pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__,
 177               win, addr, value);
 178     return value;
 179 }
 180
 181 static void pci_reg_write4(void *opaque, hwaddr addr,
 182                            uint64_t value, unsigned size)
 183 {
 184     PPCE500PCIState *pci = opaque;
 185     unsigned long win;
 186     int idx;
 187
 188     win = addr & 0xfe0;
 189
 190     pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n",
 191               __func__, (unsigned)value, win, addr);
 192
 193     switch (win) {
 194     case PPCE500_PCI_OW1:
 195     case PPCE500_PCI_OW2:
 196     case PPCE500_PCI_OW3:
 197     case PPCE500_PCI_OW4:
 198         idx = (addr >> 5) & 0x7;
 199         switch (addr & 0xC) {
 200         case PCI_POTAR:
 201             pci->pob[idx].potar = value;
 202             break;
 203         case PCI_POTEAR:
 204             pci->pob[idx].potear = value;
 205             break;
 206         case PCI_POWBAR:
 207             pci->pob[idx].powbar = value;
 208             break;
 209         case PCI_POWAR:
 210             pci->pob[idx].powar = value;
 211             break;
 212         default:
 213             break;
 214         };
 215         break;
 216
 217     case PPCE500_PCI_IW3:
 218     case PPCE500_PCI_IW2:
 219     case PPCE500_PCI_IW1:
 220         idx = ((addr >> 5) & 0x3) - 1;
 221         switch (addr & 0xC) {
 222         case PCI_PITAR:
 223             pci->pib[idx].pitar = value;
 224             break;
 225         case PCI_PIWBAR:
 226             pci->pib[idx].piwbar = value;
 227             break;
 228         case PCI_PIWBEAR:
 229             pci->pib[idx].piwbear = value;
 230             break;
 231         case PCI_PIWAR:
 232             pci->pib[idx].piwar = value;
 233             break;
 234         default:
 235             break;
 236         };
 237         break;
 238
 239     case PPCE500_PCI_GASKET_TIMR:
 240         pci->gasket_time = value;
 241         break;
 242
 243     default:
 244         break;
 245     };
 246 }
 247
 248 static const MemoryRegionOps e500_pci_reg_ops = {
 249     .read = pci_reg_read4,
 250     .write = pci_reg_write4,
 251     .endianness = DEVICE_BIG_ENDIAN,
 252 };
 253
 254 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int irq_num)
 255 {
 256     int devno = pci_dev->devfn >> 3;
 257     int ret;
 258
 259     ret = (irq_num + devno) % 4;
 260
 261     pci_debug("%s: devfn %x irq %d -> %d  devno:%x\n", __func__,
 262            pci_dev->devfn, irq_num, ret, devno);
 263
 264     return ret;
 265 }
 266
 267 static void mpc85xx_pci_set_irq(void *opaque, int irq_num, int level)
 268 {
 269     qemu_irq *pic = opaque;
 270
 271     pci_debug("%s: PCI irq %d, level:%d\n", __func__, irq_num, level);
 272
 273     qemu_set_irq(pic[irq_num], level);
 274 }
 275
 276 static const VMStateDescription vmstate_pci_outbound = {
 277     .name = "pci_outbound",
 278     .version_id = 0,
 279     .minimum_version_id = 0,
 280     .minimum_version_id_old = 0,
 281     .fields      = (VMStateField[]) {
 282         VMSTATE_UINT32(potar, struct pci_outbound),
 283         VMSTATE_UINT32(potear, struct pci_outbound),
 284         VMSTATE_UINT32(powbar, struct pci_outbound),
 285         VMSTATE_UINT32(powar, struct pci_outbound),
 286         VMSTATE_END_OF_LIST()
 287     }
 288 };
 289
 290 static const VMStateDescription vmstate_pci_inbound = {
 291     .name = "pci_inbound",
 292     .version_id = 0,
 293     .minimum_version_id = 0,
 294     .minimum_version_id_old = 0,
 295     .fields      = (VMStateField[]) {
 296         VMSTATE_UINT32(pitar, struct pci_inbound),
 297         VMSTATE_UINT32(piwbar, struct pci_inbound),
 298         VMSTATE_UINT32(piwbear, struct pci_inbound),
 299         VMSTATE_UINT32(piwar, struct pci_inbound),
 300         VMSTATE_END_OF_LIST()
 301     }
 302 };
 303
 304 static const VMStateDescription vmstate_ppce500_pci = {
 305     .name = "ppce500_pci",
 306     .version_id = 1,
 307     .minimum_version_id = 1,
 308     .minimum_version_id_old = 1,
 309     .fields      = (VMStateField[]) {
 310         VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1,
 311                              vmstate_pci_outbound, struct pci_outbound),
 312         VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1,
 313                              vmstate_pci_outbound, struct pci_inbound),
 314         VMSTATE_UINT32(gasket_time, PPCE500PCIState),
 315         VMSTATE_END_OF_LIST()
 316     }
 317 };
 318
 319 #include "exec-memory.h"
 320
 321 static int e500_pcihost_bridge_initfn(PCIDevice *d)
 322 {
 323     PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d);
 324     PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(),
 325                                   "/e500-ccsr"));
 326
 327     pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI);
 328     d->config[PCI_HEADER_TYPE] =
 329         (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
 330         PCI_HEADER_TYPE_BRIDGE;
 331
 332     memory_region_init_alias(&b->bar0, "e500-pci-bar0", &ccsr->ccsr_space,
 333                              0, int128_get64(ccsr->ccsr_space.size));
 334     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0);
 335
 336     return 0;
 337 }
 338
 339 static int e500_pcihost_initfn(SysBusDevice *dev)
 340 {
 341     PCIHostState *h;
 342     PPCE500PCIState *s;
 343     PCIBus *b;
 344     int i;
 345     MemoryRegion *address_space_mem = get_system_memory();
 346
 347     h = PCI_HOST_BRIDGE(dev);
 348     s = PPC_E500_PCI_HOST_BRIDGE(dev);
 349
 350     for (i = 0; i < ARRAY_SIZE(s->irq); i++) {
 351         sysbus_init_irq(dev, &s->irq[i]);
 352     }
 353
 354     memory_region_init(&s->pio, "pci-pio", PCIE500_PCI_IOLEN);
 355
 356     b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq,
 357                          mpc85xx_pci_map_irq, s->irq, address_space_mem,
 358                          &s->pio, PCI_DEVFN(s->first_slot, 0), 4);
 359     h->bus = b;
 360
 361     pci_create_simple(b, 0, "e500-host-bridge");
 362
 363     memory_region_init(&s->container, "pci-container", PCIE500_ALL_SIZE);
 364     memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
 365                           "pci-conf-idx", 4);
 366     memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
 367                           "pci-conf-data", 4);
 368     memory_region_init_io(&s->iomem, &e500_pci_reg_ops, s,
 369                           "pci.reg", PCIE500_REG_SIZE);
 370     memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem);
 371     memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem);
 372     memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem);
 373     sysbus_init_mmio(dev, &s->container);
 374     sysbus_init_mmio(dev, &s->pio);
 375
 376     return 0;
 377 }
 378
 379 static void e500_host_bridge_class_init(ObjectClass *klass, void *data)
 380 {
 381     DeviceClass *dc = DEVICE_CLASS(klass);
 382     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 383
 384     k->init = e500_pcihost_bridge_initfn;
 385     k->vendor_id = PCI_VENDOR_ID_FREESCALE;
 386     k->device_id = PCI_DEVICE_ID_MPC8533E;
 387     k->class_id = PCI_CLASS_PROCESSOR_POWERPC;
 388     dc->desc = "Host bridge";
 389 }
 390
 391 static const TypeInfo e500_host_bridge_info = {
 392     .name          = "e500-host-bridge",
 393     .parent        = TYPE_PCI_DEVICE,
 394     .instance_size = sizeof(PPCE500PCIBridgeState),
 395     .class_init    = e500_host_bridge_class_init,
 396 };
 397
 398 static Property pcihost_properties[] = {
 399     DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11),
 400     DEFINE_PROP_END_OF_LIST(),
 401 };
 402
 403 static void e500_pcihost_class_init(ObjectClass *klass, void *data)
 404 {
 405     DeviceClass *dc = DEVICE_CLASS(klass);
 406     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 407
 408     k->init = e500_pcihost_initfn;
 409     dc->props = pcihost_properties;
 410     dc->vmsd = &vmstate_ppce500_pci;
 411 }
 412
 413 static const TypeInfo e500_pcihost_info = {
 414     .name          = TYPE_PPC_E500_PCI_HOST_BRIDGE,
 415     .parent        = TYPE_PCI_HOST_BRIDGE,
 416     .instance_size = sizeof(PPCE500PCIState),
 417     .class_init    = e500_pcihost_class_init,
 418 };
 419
 420 static void e500_pci_register_types(void)
 421 {
 422     type_register_static(&e500_pcihost_info);
 423     type_register_static(&e500_host_bridge_info);
 424 }
 425
 426 type_init(e500_pci_register_types)