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PPC: E500: Add PV spinning code
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1 /*
2 * QEMU PowerPC e500v2 ePAPR spinning code
3 *
4 * Copyright (C) 2011 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Alexander Graf, <agraf@suse.de>
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 *
21 * This code is not really a device, but models an interface that usually
22 * firmware takes care of. It's used when QEMU plays the role of firmware.
23 *
24 * Specification:
25 *
26 * https://www.power.org/resources/downloads/Power_ePAPR_APPROVED_v1.1.pdf
27 *
28 */
29
30 #include "hw.h"
31 #include "sysemu.h"
32 #include "sysbus.h"
33 #include "kvm.h"
34
35 #define MAX_CPUS 32
36
37 typedef struct spin_info {
38 uint64_t addr;
39 uint64_t r3;
40 uint32_t resv;
41 uint32_t pir;
42 uint64_t reserved;
43 } __attribute__ ((packed)) SpinInfo;
44
45 typedef struct spin_state {
46 SysBusDevice busdev;
47 MemoryRegion iomem;
48 SpinInfo spin[MAX_CPUS];
49 } SpinState;
50
51 typedef struct spin_kick {
52 CPUState *env;
53 SpinInfo *spin;
54 } SpinKick;
55
56 static void spin_reset(void *opaque)
57 {
58 SpinState *s = opaque;
59 int i;
60
61 for (i = 0; i < MAX_CPUS; i++) {
62 SpinInfo *info = &s->spin[i];
63
64 info->pir = i;
65 info->r3 = i;
66 info->addr = 1;
67 }
68 }
69
70 /* Create -kernel TLB entries for BookE, linearly spanning 256MB. */
71 static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
72 {
73 return (ffs(size >> 10) - 1) >> 1;
74 }
75
76 static void mmubooke_create_initial_mapping(CPUState *env,
77 target_ulong va,
78 target_phys_addr_t pa,
79 target_phys_addr_t len)
80 {
81 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 1);
82 target_phys_addr_t size;
83
84 size = (booke206_page_size_to_tlb(len) << MAS1_TSIZE_SHIFT);
85 tlb->mas1 = MAS1_VALID | size;
86 tlb->mas2 = (va & TARGET_PAGE_MASK) | MAS2_M;
87 tlb->mas7_3 = pa & TARGET_PAGE_MASK;
88 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
89 }
90
91 static void spin_kick(void *data)
92 {
93 SpinKick *kick = data;
94 CPUState *env = kick->env;
95 SpinInfo *curspin = kick->spin;
96 target_phys_addr_t map_size = 64 * 1024 * 1024;
97 target_phys_addr_t map_start;
98
99 cpu_synchronize_state(env);
100 stl_p(&curspin->pir, env->spr[SPR_PIR]);
101 env->nip = ldq_p(&curspin->addr) & (map_size - 1);
102 env->gpr[3] = ldq_p(&curspin->r3);
103 env->gpr[4] = 0;
104 env->gpr[5] = 0;
105 env->gpr[6] = 0;
106 env->gpr[7] = map_size;
107 env->gpr[8] = 0;
108 env->gpr[9] = 0;
109
110 map_start = ldq_p(&curspin->addr) & ~(map_size - 1);
111 mmubooke_create_initial_mapping(env, 0, map_start, map_size);
112
113 env->halted = 0;
114 env->exception_index = -1;
115 qemu_cpu_kick(env);
116 }
117
118 static void spin_write(void *opaque, target_phys_addr_t addr, uint64_t value,
119 unsigned len)
120 {
121 SpinState *s = opaque;
122 int env_idx = addr / sizeof(SpinInfo);
123 CPUState *env;
124 SpinInfo *curspin = &s->spin[env_idx];
125 uint8_t *curspin_p = (uint8_t*)curspin;
126
127 for (env = first_cpu; env != NULL; env = env->next_cpu) {
128 if (env->cpu_index == env_idx) {
129 break;
130 }
131 }
132
133 if (!env) {
134 /* Unknown CPU */
135 return;
136 }
137
138 if (!env->cpu_index) {
139 /* primary CPU doesn't spin */
140 return;
141 }
142
143 curspin_p = &curspin_p[addr % sizeof(SpinInfo)];
144 switch (len) {
145 case 1:
146 stb_p(curspin_p, value);
147 break;
148 case 2:
149 stw_p(curspin_p, value);
150 break;
151 case 4:
152 stl_p(curspin_p, value);
153 break;
154 }
155
156 if (!(ldq_p(&curspin->addr) & 1)) {
157 /* run CPU */
158 SpinKick kick = {
159 .env = env,
160 .spin = curspin,
161 };
162
163 run_on_cpu(env, spin_kick, &kick);
164 }
165 }
166
167 static uint64_t spin_read(void *opaque, target_phys_addr_t addr, unsigned len)
168 {
169 SpinState *s = opaque;
170 uint8_t *spin_p = &((uint8_t*)s->spin)[addr];
171
172 switch (len) {
173 case 1:
174 return ldub_p(spin_p);
175 case 2:
176 return lduw_p(spin_p);
177 case 4:
178 return ldl_p(spin_p);
179 default:
180 assert(0);
181 }
182 }
183
184 const MemoryRegionOps spin_rw_ops = {
185 .read = spin_read,
186 .write = spin_write,
187 .endianness = DEVICE_BIG_ENDIAN,
188 };
189
190 static int ppce500_spin_initfn(SysBusDevice *dev)
191 {
192 SpinState *s;
193
194 s = FROM_SYSBUS(SpinState, sysbus_from_qdev(dev));
195
196 memory_region_init_io(&s->iomem, &spin_rw_ops, s, "e500 spin pv device",
197 sizeof(SpinInfo) * MAX_CPUS);
198 sysbus_init_mmio_region(dev, &s->iomem);
199
200 qemu_register_reset(spin_reset, s);
201
202 return 0;
203 }
204
205 static SysBusDeviceInfo ppce500_spin_info = {
206 .init = ppce500_spin_initfn,
207 .qdev.name = "e500-spin",
208 .qdev.size = sizeof(SpinState),
209 };
210
211 static void ppce500_spin_register(void)
212 {
213 sysbus_register_withprop(&ppce500_spin_info);
214 }
215 device_init(ppce500_spin_register);