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1 /*
2 * QEMU PREP PCI host
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "hw.h"
26 #include "pci.h"
27 #include "pci_host.h"
28 #include "pc.h"
29 #include "exec-memory.h"
30
31 typedef struct PRePPCIState {
32 PCIHostState host_state;
33 MemoryRegion intack;
34 qemu_irq irq[4];
35 } PREPPCIState;
36
37 typedef struct RavenPCIState {
38 PCIDevice dev;
39 } RavenPCIState;
40
41 static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr)
42 {
43 int i;
44
45 for(i = 0; i < 11; i++) {
46 if ((addr & (1 << (11 + i))) != 0)
47 break;
48 }
49 return (addr & 0x7ff) | (i << 11);
50 }
51
52 static void ppc_pci_io_write(void *opaque, target_phys_addr_t addr,
53 uint64_t val, unsigned int size)
54 {
55 PREPPCIState *s = opaque;
56 pci_data_write(s->host_state.bus, PPC_PCIIO_config(addr), val, size);
57 }
58
59 static uint64_t ppc_pci_io_read(void *opaque, target_phys_addr_t addr,
60 unsigned int size)
61 {
62 PREPPCIState *s = opaque;
63 return pci_data_read(s->host_state.bus, PPC_PCIIO_config(addr), size);
64 }
65
66 static const MemoryRegionOps PPC_PCIIO_ops = {
67 .read = ppc_pci_io_read,
68 .write = ppc_pci_io_write,
69 .endianness = DEVICE_LITTLE_ENDIAN,
70 };
71
72 static uint64_t ppc_intack_read(void *opaque, target_phys_addr_t addr,
73 unsigned int size)
74 {
75 return pic_read_irq(isa_pic);
76 }
77
78 static const MemoryRegionOps PPC_intack_ops = {
79 .read = ppc_intack_read,
80 .valid = {
81 .max_access_size = 1,
82 },
83 };
84
85 static int prep_map_irq(PCIDevice *pci_dev, int irq_num)
86 {
87 return (irq_num + (pci_dev->devfn >> 3)) & 1;
88 }
89
90 static void prep_set_irq(void *opaque, int irq_num, int level)
91 {
92 qemu_irq *pic = opaque;
93
94 qemu_set_irq(pic[irq_num] , level);
95 }
96
97 static int raven_pcihost_init(SysBusDevice *dev)
98 {
99 PCIHostState *h = FROM_SYSBUS(PCIHostState, dev);
100 PREPPCIState *s = DO_UPCAST(PREPPCIState, host_state, h);
101 MemoryRegion *address_space_mem = get_system_memory();
102 MemoryRegion *address_space_io = get_system_io();
103 PCIBus *bus;
104 int i;
105
106 for (i = 0; i < 4; i++) {
107 sysbus_init_irq(dev, &s->irq[i]);
108 }
109
110 bus = pci_register_bus(&h->busdev.qdev, NULL,
111 prep_set_irq, prep_map_irq, s->irq,
112 address_space_mem, address_space_io, 0, 4);
113 h->bus = bus;
114
115 memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, s,
116 "pci-conf-idx", 1);
117 sysbus_add_io(dev, 0xcf8, &h->conf_mem);
118 sysbus_init_ioports(&h->busdev, 0xcf8, 1);
119
120 memory_region_init_io(&h->data_mem, &pci_host_data_be_ops, s,
121 "pci-conf-data", 1);
122 sysbus_add_io(dev, 0xcfc, &h->data_mem);
123 sysbus_init_ioports(&h->busdev, 0xcfc, 1);
124
125 memory_region_init_io(&h->mmcfg, &PPC_PCIIO_ops, s, "pciio", 0x00400000);
126 memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg);
127
128 memory_region_init_io(&s->intack, &PPC_intack_ops, s, "pci-intack", 1);
129 memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->intack);
130 pci_create_simple(bus, 0, "raven");
131
132 return 0;
133 }
134
135 static int raven_init(PCIDevice *d)
136 {
137 d->config[0x0C] = 0x08; // cache_line_size
138 d->config[0x0D] = 0x10; // latency_timer
139 d->config[0x34] = 0x00; // capabilities_pointer
140
141 return 0;
142 }
143
144 static const VMStateDescription vmstate_raven = {
145 .name = "raven",
146 .version_id = 0,
147 .minimum_version_id = 0,
148 .fields = (VMStateField[]) {
149 VMSTATE_PCI_DEVICE(dev, RavenPCIState),
150 VMSTATE_END_OF_LIST()
151 },
152 };
153
154 static void raven_class_init(ObjectClass *klass, void *data)
155 {
156 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
157 DeviceClass *dc = DEVICE_CLASS(klass);
158
159 k->init = raven_init;
160 k->vendor_id = PCI_VENDOR_ID_MOTOROLA;
161 k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN;
162 k->revision = 0x00;
163 k->class_id = PCI_CLASS_BRIDGE_HOST;
164 dc->desc = "PReP Host Bridge - Motorola Raven";
165 dc->vmsd = &vmstate_raven;
166 dc->no_user = 1;
167 }
168
169 static TypeInfo raven_info = {
170 .name = "raven",
171 .parent = TYPE_PCI_DEVICE,
172 .instance_size = sizeof(RavenPCIState),
173 .class_init = raven_class_init,
174 };
175
176 static void raven_pcihost_class_init(ObjectClass *klass, void *data)
177 {
178 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
179 DeviceClass *dc = DEVICE_CLASS(klass);
180
181 k->init = raven_pcihost_init;
182 dc->fw_name = "pci";
183 dc->no_user = 1;
184 }
185
186 static TypeInfo raven_pcihost_info = {
187 .name = "raven-pcihost",
188 .parent = TYPE_SYS_BUS_DEVICE,
189 .instance_size = sizeof(PREPPCIState),
190 .class_init = raven_pcihost_class_init,
191 };
192
193 static void raven_register_types(void)
194 {
195 type_register_static(&raven_pcihost_info);
196 type_register_static(&raven_info);
197 }
198
199 type_init(raven_register_types)