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hw/pxa2xx.c: Fix handling of R/WC bits in PMCR
[qemu.git] / hw / pxa2xx.c
1 /*
2 * Intel XScale PXA255/270 processor support.
3 *
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Written by Andrzej Zaborowski <balrog@zabor.org>
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "pxa.h"
12 #include "sysemu.h"
13 #include "pc.h"
14 #include "i2c.h"
15 #include "ssi.h"
16 #include "qemu-char.h"
17 #include "blockdev.h"
18
19 static struct {
20 target_phys_addr_t io_base;
21 int irqn;
22 } pxa255_serial[] = {
23 { 0x40100000, PXA2XX_PIC_FFUART },
24 { 0x40200000, PXA2XX_PIC_BTUART },
25 { 0x40700000, PXA2XX_PIC_STUART },
26 { 0x41600000, PXA25X_PIC_HWUART },
27 { 0, 0 }
28 }, pxa270_serial[] = {
29 { 0x40100000, PXA2XX_PIC_FFUART },
30 { 0x40200000, PXA2XX_PIC_BTUART },
31 { 0x40700000, PXA2XX_PIC_STUART },
32 { 0, 0 }
33 };
34
35 typedef struct PXASSPDef {
36 target_phys_addr_t io_base;
37 int irqn;
38 } PXASSPDef;
39
40 #if 0
41 static PXASSPDef pxa250_ssp[] = {
42 { 0x41000000, PXA2XX_PIC_SSP },
43 { 0, 0 }
44 };
45 #endif
46
47 static PXASSPDef pxa255_ssp[] = {
48 { 0x41000000, PXA2XX_PIC_SSP },
49 { 0x41400000, PXA25X_PIC_NSSP },
50 { 0, 0 }
51 };
52
53 #if 0
54 static PXASSPDef pxa26x_ssp[] = {
55 { 0x41000000, PXA2XX_PIC_SSP },
56 { 0x41400000, PXA25X_PIC_NSSP },
57 { 0x41500000, PXA26X_PIC_ASSP },
58 { 0, 0 }
59 };
60 #endif
61
62 static PXASSPDef pxa27x_ssp[] = {
63 { 0x41000000, PXA2XX_PIC_SSP },
64 { 0x41700000, PXA27X_PIC_SSP2 },
65 { 0x41900000, PXA2XX_PIC_SSP3 },
66 { 0, 0 }
67 };
68
69 #define PMCR 0x00 /* Power Manager Control register */
70 #define PSSR 0x04 /* Power Manager Sleep Status register */
71 #define PSPR 0x08 /* Power Manager Scratch-Pad register */
72 #define PWER 0x0c /* Power Manager Wake-Up Enable register */
73 #define PRER 0x10 /* Power Manager Rising-Edge Detect Enable register */
74 #define PFER 0x14 /* Power Manager Falling-Edge Detect Enable register */
75 #define PEDR 0x18 /* Power Manager Edge-Detect Status register */
76 #define PCFR 0x1c /* Power Manager General Configuration register */
77 #define PGSR0 0x20 /* Power Manager GPIO Sleep-State register 0 */
78 #define PGSR1 0x24 /* Power Manager GPIO Sleep-State register 1 */
79 #define PGSR2 0x28 /* Power Manager GPIO Sleep-State register 2 */
80 #define PGSR3 0x2c /* Power Manager GPIO Sleep-State register 3 */
81 #define RCSR 0x30 /* Reset Controller Status register */
82 #define PSLR 0x34 /* Power Manager Sleep Configuration register */
83 #define PTSR 0x38 /* Power Manager Standby Configuration register */
84 #define PVCR 0x40 /* Power Manager Voltage Change Control register */
85 #define PUCR 0x4c /* Power Manager USIM Card Control/Status register */
86 #define PKWR 0x50 /* Power Manager Keyboard Wake-Up Enable register */
87 #define PKSR 0x54 /* Power Manager Keyboard Level-Detect Status */
88 #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */
89 #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */
90
91 static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr,
92 unsigned size)
93 {
94 PXA2xxState *s = (PXA2xxState *) opaque;
95
96 switch (addr) {
97 case PMCR ... PCMD31:
98 if (addr & 3)
99 goto fail;
100
101 return s->pm_regs[addr >> 2];
102 default:
103 fail:
104 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
105 break;
106 }
107 return 0;
108 }
109
110 static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr,
111 uint64_t value, unsigned size)
112 {
113 PXA2xxState *s = (PXA2xxState *) opaque;
114
115 switch (addr) {
116 case PMCR:
117 /* Clear the write-one-to-clear bits... */
118 s->pm_regs[addr >> 2] &= ~(value & 0x2a);
119 /* ...and set the plain r/w bits */
120 s->pm_regs[addr >> 2] |= value & 0x15;
121 break;
122
123 case PSSR: /* Read-clean registers */
124 case RCSR:
125 case PKSR:
126 s->pm_regs[addr >> 2] &= ~value;
127 break;
128
129 default: /* Read-write registers */
130 if (!(addr & 3)) {
131 s->pm_regs[addr >> 2] = value;
132 break;
133 }
134
135 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
136 break;
137 }
138 }
139
140 static const MemoryRegionOps pxa2xx_pm_ops = {
141 .read = pxa2xx_pm_read,
142 .write = pxa2xx_pm_write,
143 .endianness = DEVICE_NATIVE_ENDIAN,
144 };
145
146 static const VMStateDescription vmstate_pxa2xx_pm = {
147 .name = "pxa2xx_pm",
148 .version_id = 0,
149 .minimum_version_id = 0,
150 .minimum_version_id_old = 0,
151 .fields = (VMStateField[]) {
152 VMSTATE_UINT32_ARRAY(pm_regs, PXA2xxState, 0x40),
153 VMSTATE_END_OF_LIST()
154 }
155 };
156
157 #define CCCR 0x00 /* Core Clock Configuration register */
158 #define CKEN 0x04 /* Clock Enable register */
159 #define OSCC 0x08 /* Oscillator Configuration register */
160 #define CCSR 0x0c /* Core Clock Status register */
161
162 static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr,
163 unsigned size)
164 {
165 PXA2xxState *s = (PXA2xxState *) opaque;
166
167 switch (addr) {
168 case CCCR:
169 case CKEN:
170 case OSCC:
171 return s->cm_regs[addr >> 2];
172
173 case CCSR:
174 return s->cm_regs[CCCR >> 2] | (3 << 28);
175
176 default:
177 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
178 break;
179 }
180 return 0;
181 }
182
183 static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr,
184 uint64_t value, unsigned size)
185 {
186 PXA2xxState *s = (PXA2xxState *) opaque;
187
188 switch (addr) {
189 case CCCR:
190 case CKEN:
191 s->cm_regs[addr >> 2] = value;
192 break;
193
194 case OSCC:
195 s->cm_regs[addr >> 2] &= ~0x6c;
196 s->cm_regs[addr >> 2] |= value & 0x6e;
197 if ((value >> 1) & 1) /* OON */
198 s->cm_regs[addr >> 2] |= 1 << 0; /* Oscillator is now stable */
199 break;
200
201 default:
202 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
203 break;
204 }
205 }
206
207 static const MemoryRegionOps pxa2xx_cm_ops = {
208 .read = pxa2xx_cm_read,
209 .write = pxa2xx_cm_write,
210 .endianness = DEVICE_NATIVE_ENDIAN,
211 };
212
213 static const VMStateDescription vmstate_pxa2xx_cm = {
214 .name = "pxa2xx_cm",
215 .version_id = 0,
216 .minimum_version_id = 0,
217 .minimum_version_id_old = 0,
218 .fields = (VMStateField[]) {
219 VMSTATE_UINT32_ARRAY(cm_regs, PXA2xxState, 4),
220 VMSTATE_UINT32(clkcfg, PXA2xxState),
221 VMSTATE_UINT32(pmnc, PXA2xxState),
222 VMSTATE_END_OF_LIST()
223 }
224 };
225
226 static uint32_t pxa2xx_clkpwr_read(void *opaque, int op2, int reg, int crm)
227 {
228 PXA2xxState *s = (PXA2xxState *) opaque;
229
230 switch (reg) {
231 case 6: /* Clock Configuration register */
232 return s->clkcfg;
233
234 case 7: /* Power Mode register */
235 return 0;
236
237 default:
238 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
239 break;
240 }
241 return 0;
242 }
243
244 static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
245 uint32_t value)
246 {
247 PXA2xxState *s = (PXA2xxState *) opaque;
248 static const char *pwrmode[8] = {
249 "Normal", "Idle", "Deep-idle", "Standby",
250 "Sleep", "reserved (!)", "reserved (!)", "Deep-sleep",
251 };
252
253 switch (reg) {
254 case 6: /* Clock Configuration register */
255 s->clkcfg = value & 0xf;
256 if (value & 2)
257 printf("%s: CPU frequency change attempt\n", __FUNCTION__);
258 break;
259
260 case 7: /* Power Mode register */
261 if (value & 8)
262 printf("%s: CPU voltage change attempt\n", __FUNCTION__);
263 switch (value & 7) {
264 case 0:
265 /* Do nothing */
266 break;
267
268 case 1:
269 /* Idle */
270 if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */
271 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
272 break;
273 }
274 /* Fall through. */
275
276 case 2:
277 /* Deep-Idle */
278 cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
279 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
280 goto message;
281
282 case 3:
283 s->env->uncached_cpsr =
284 ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
285 s->env->cp15.c1_sys = 0;
286 s->env->cp15.c1_coproc = 0;
287 s->env->cp15.c2_base0 = 0;
288 s->env->cp15.c3 = 0;
289 s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
290 s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
291
292 /*
293 * The scratch-pad register is almost universally used
294 * for storing the return address on suspend. For the
295 * lack of a resuming bootloader, perform a jump
296 * directly to that address.
297 */
298 memset(s->env->regs, 0, 4 * 15);
299 s->env->regs[15] = s->pm_regs[PSPR >> 2];
300
301 #if 0
302 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */
303 cpu_physical_memory_write(0, &buffer, 4);
304 buffer = s->pm_regs[PSPR >> 2];
305 cpu_physical_memory_write(8, &buffer, 4);
306 #endif
307
308 /* Suspend */
309 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
310
311 goto message;
312
313 default:
314 message:
315 printf("%s: machine entered %s mode\n", __FUNCTION__,
316 pwrmode[value & 7]);
317 }
318 break;
319
320 default:
321 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
322 break;
323 }
324 }
325
326 /* Performace Monitoring Registers */
327 #define CPPMNC 0 /* Performance Monitor Control register */
328 #define CPCCNT 1 /* Clock Counter register */
329 #define CPINTEN 4 /* Interrupt Enable register */
330 #define CPFLAG 5 /* Overflow Flag register */
331 #define CPEVTSEL 8 /* Event Selection register */
332
333 #define CPPMN0 0 /* Performance Count register 0 */
334 #define CPPMN1 1 /* Performance Count register 1 */
335 #define CPPMN2 2 /* Performance Count register 2 */
336 #define CPPMN3 3 /* Performance Count register 3 */
337
338 static uint32_t pxa2xx_perf_read(void *opaque, int op2, int reg, int crm)
339 {
340 PXA2xxState *s = (PXA2xxState *) opaque;
341
342 switch (reg) {
343 case CPPMNC:
344 return s->pmnc;
345 case CPCCNT:
346 if (s->pmnc & 1)
347 return qemu_get_clock_ns(vm_clock);
348 else
349 return 0;
350 case CPINTEN:
351 case CPFLAG:
352 case CPEVTSEL:
353 return 0;
354
355 default:
356 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
357 break;
358 }
359 return 0;
360 }
361
362 static void pxa2xx_perf_write(void *opaque, int op2, int reg, int crm,
363 uint32_t value)
364 {
365 PXA2xxState *s = (PXA2xxState *) opaque;
366
367 switch (reg) {
368 case CPPMNC:
369 s->pmnc = value;
370 break;
371
372 case CPCCNT:
373 case CPINTEN:
374 case CPFLAG:
375 case CPEVTSEL:
376 break;
377
378 default:
379 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
380 break;
381 }
382 }
383
384 static uint32_t pxa2xx_cp14_read(void *opaque, int op2, int reg, int crm)
385 {
386 switch (crm) {
387 case 0:
388 return pxa2xx_clkpwr_read(opaque, op2, reg, crm);
389 case 1:
390 return pxa2xx_perf_read(opaque, op2, reg, crm);
391 case 2:
392 switch (reg) {
393 case CPPMN0:
394 case CPPMN1:
395 case CPPMN2:
396 case CPPMN3:
397 return 0;
398 }
399 /* Fall through */
400 default:
401 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
402 break;
403 }
404 return 0;
405 }
406
407 static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm,
408 uint32_t value)
409 {
410 switch (crm) {
411 case 0:
412 pxa2xx_clkpwr_write(opaque, op2, reg, crm, value);
413 break;
414 case 1:
415 pxa2xx_perf_write(opaque, op2, reg, crm, value);
416 break;
417 case 2:
418 switch (reg) {
419 case CPPMN0:
420 case CPPMN1:
421 case CPPMN2:
422 case CPPMN3:
423 return;
424 }
425 /* Fall through */
426 default:
427 printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
428 break;
429 }
430 }
431
432 #define MDCNFG 0x00 /* SDRAM Configuration register */
433 #define MDREFR 0x04 /* SDRAM Refresh Control register */
434 #define MSC0 0x08 /* Static Memory Control register 0 */
435 #define MSC1 0x0c /* Static Memory Control register 1 */
436 #define MSC2 0x10 /* Static Memory Control register 2 */
437 #define MECR 0x14 /* Expansion Memory Bus Config register */
438 #define SXCNFG 0x1c /* Synchronous Static Memory Config register */
439 #define MCMEM0 0x28 /* PC Card Memory Socket 0 Timing register */
440 #define MCMEM1 0x2c /* PC Card Memory Socket 1 Timing register */
441 #define MCATT0 0x30 /* PC Card Attribute Socket 0 register */
442 #define MCATT1 0x34 /* PC Card Attribute Socket 1 register */
443 #define MCIO0 0x38 /* PC Card I/O Socket 0 Timing register */
444 #define MCIO1 0x3c /* PC Card I/O Socket 1 Timing register */
445 #define MDMRS 0x40 /* SDRAM Mode Register Set Config register */
446 #define BOOT_DEF 0x44 /* Boot-time Default Configuration register */
447 #define ARB_CNTL 0x48 /* Arbiter Control register */
448 #define BSCNTR0 0x4c /* Memory Buffer Strength Control register 0 */
449 #define BSCNTR1 0x50 /* Memory Buffer Strength Control register 1 */
450 #define LCDBSCNTR 0x54 /* LCD Buffer Strength Control register */
451 #define MDMRSLP 0x58 /* Low Power SDRAM Mode Set Config register */
452 #define BSCNTR2 0x5c /* Memory Buffer Strength Control register 2 */
453 #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */
454 #define SA1110 0x64 /* SA-1110 Memory Compatibility register */
455
456 static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr,
457 unsigned size)
458 {
459 PXA2xxState *s = (PXA2xxState *) opaque;
460
461 switch (addr) {
462 case MDCNFG ... SA1110:
463 if ((addr & 3) == 0)
464 return s->mm_regs[addr >> 2];
465
466 default:
467 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
468 break;
469 }
470 return 0;
471 }
472
473 static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr,
474 uint64_t value, unsigned size)
475 {
476 PXA2xxState *s = (PXA2xxState *) opaque;
477
478 switch (addr) {
479 case MDCNFG ... SA1110:
480 if ((addr & 3) == 0) {
481 s->mm_regs[addr >> 2] = value;
482 break;
483 }
484
485 default:
486 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
487 break;
488 }
489 }
490
491 static const MemoryRegionOps pxa2xx_mm_ops = {
492 .read = pxa2xx_mm_read,
493 .write = pxa2xx_mm_write,
494 .endianness = DEVICE_NATIVE_ENDIAN,
495 };
496
497 static const VMStateDescription vmstate_pxa2xx_mm = {
498 .name = "pxa2xx_mm",
499 .version_id = 0,
500 .minimum_version_id = 0,
501 .minimum_version_id_old = 0,
502 .fields = (VMStateField[]) {
503 VMSTATE_UINT32_ARRAY(mm_regs, PXA2xxState, 0x1a),
504 VMSTATE_END_OF_LIST()
505 }
506 };
507
508 /* Synchronous Serial Ports */
509 typedef struct {
510 SysBusDevice busdev;
511 MemoryRegion iomem;
512 qemu_irq irq;
513 int enable;
514 SSIBus *bus;
515
516 uint32_t sscr[2];
517 uint32_t sspsp;
518 uint32_t ssto;
519 uint32_t ssitr;
520 uint32_t sssr;
521 uint8_t sstsa;
522 uint8_t ssrsa;
523 uint8_t ssacd;
524
525 uint32_t rx_fifo[16];
526 int rx_level;
527 int rx_start;
528 } PXA2xxSSPState;
529
530 #define SSCR0 0x00 /* SSP Control register 0 */
531 #define SSCR1 0x04 /* SSP Control register 1 */
532 #define SSSR 0x08 /* SSP Status register */
533 #define SSITR 0x0c /* SSP Interrupt Test register */
534 #define SSDR 0x10 /* SSP Data register */
535 #define SSTO 0x28 /* SSP Time-Out register */
536 #define SSPSP 0x2c /* SSP Programmable Serial Protocol register */
537 #define SSTSA 0x30 /* SSP TX Time Slot Active register */
538 #define SSRSA 0x34 /* SSP RX Time Slot Active register */
539 #define SSTSS 0x38 /* SSP Time Slot Status register */
540 #define SSACD 0x3c /* SSP Audio Clock Divider register */
541
542 /* Bitfields for above registers */
543 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
544 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
545 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
546 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
547 #define SSCR0_SSE (1 << 7)
548 #define SSCR0_RIM (1 << 22)
549 #define SSCR0_TIM (1 << 23)
550 #define SSCR0_MOD (1 << 31)
551 #define SSCR0_DSS(x) (((((x) >> 16) & 0x10) | ((x) & 0xf)) + 1)
552 #define SSCR1_RIE (1 << 0)
553 #define SSCR1_TIE (1 << 1)
554 #define SSCR1_LBM (1 << 2)
555 #define SSCR1_MWDS (1 << 5)
556 #define SSCR1_TFT(x) ((((x) >> 6) & 0xf) + 1)
557 #define SSCR1_RFT(x) ((((x) >> 10) & 0xf) + 1)
558 #define SSCR1_EFWR (1 << 14)
559 #define SSCR1_PINTE (1 << 18)
560 #define SSCR1_TINTE (1 << 19)
561 #define SSCR1_RSRE (1 << 20)
562 #define SSCR1_TSRE (1 << 21)
563 #define SSCR1_EBCEI (1 << 29)
564 #define SSITR_INT (7 << 5)
565 #define SSSR_TNF (1 << 2)
566 #define SSSR_RNE (1 << 3)
567 #define SSSR_TFS (1 << 5)
568 #define SSSR_RFS (1 << 6)
569 #define SSSR_ROR (1 << 7)
570 #define SSSR_PINT (1 << 18)
571 #define SSSR_TINT (1 << 19)
572 #define SSSR_EOC (1 << 20)
573 #define SSSR_TUR (1 << 21)
574 #define SSSR_BCE (1 << 23)
575 #define SSSR_RW 0x00bc0080
576
577 static void pxa2xx_ssp_int_update(PXA2xxSSPState *s)
578 {
579 int level = 0;
580
581 level |= s->ssitr & SSITR_INT;
582 level |= (s->sssr & SSSR_BCE) && (s->sscr[1] & SSCR1_EBCEI);
583 level |= (s->sssr & SSSR_TUR) && !(s->sscr[0] & SSCR0_TIM);
584 level |= (s->sssr & SSSR_EOC) && (s->sssr & (SSSR_TINT | SSSR_PINT));
585 level |= (s->sssr & SSSR_TINT) && (s->sscr[1] & SSCR1_TINTE);
586 level |= (s->sssr & SSSR_PINT) && (s->sscr[1] & SSCR1_PINTE);
587 level |= (s->sssr & SSSR_ROR) && !(s->sscr[0] & SSCR0_RIM);
588 level |= (s->sssr & SSSR_RFS) && (s->sscr[1] & SSCR1_RIE);
589 level |= (s->sssr & SSSR_TFS) && (s->sscr[1] & SSCR1_TIE);
590 qemu_set_irq(s->irq, !!level);
591 }
592
593 static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s)
594 {
595 s->sssr &= ~(0xf << 12); /* Clear RFL */
596 s->sssr &= ~(0xf << 8); /* Clear TFL */
597 s->sssr &= ~SSSR_TFS;
598 s->sssr &= ~SSSR_TNF;
599 if (s->enable) {
600 s->sssr |= ((s->rx_level - 1) & 0xf) << 12;
601 if (s->rx_level >= SSCR1_RFT(s->sscr[1]))
602 s->sssr |= SSSR_RFS;
603 else
604 s->sssr &= ~SSSR_RFS;
605 if (s->rx_level)
606 s->sssr |= SSSR_RNE;
607 else
608 s->sssr &= ~SSSR_RNE;
609 /* TX FIFO is never filled, so it is always in underrun
610 condition if SSP is enabled */
611 s->sssr |= SSSR_TFS;
612 s->sssr |= SSSR_TNF;
613 }
614
615 pxa2xx_ssp_int_update(s);
616 }
617
618 static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr,
619 unsigned size)
620 {
621 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
622 uint32_t retval;
623
624 switch (addr) {
625 case SSCR0:
626 return s->sscr[0];
627 case SSCR1:
628 return s->sscr[1];
629 case SSPSP:
630 return s->sspsp;
631 case SSTO:
632 return s->ssto;
633 case SSITR:
634 return s->ssitr;
635 case SSSR:
636 return s->sssr | s->ssitr;
637 case SSDR:
638 if (!s->enable)
639 return 0xffffffff;
640 if (s->rx_level < 1) {
641 printf("%s: SSP Rx Underrun\n", __FUNCTION__);
642 return 0xffffffff;
643 }
644 s->rx_level --;
645 retval = s->rx_fifo[s->rx_start ++];
646 s->rx_start &= 0xf;
647 pxa2xx_ssp_fifo_update(s);
648 return retval;
649 case SSTSA:
650 return s->sstsa;
651 case SSRSA:
652 return s->ssrsa;
653 case SSTSS:
654 return 0;
655 case SSACD:
656 return s->ssacd;
657 default:
658 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
659 break;
660 }
661 return 0;
662 }
663
664 static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr,
665 uint64_t value64, unsigned size)
666 {
667 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
668 uint32_t value = value64;
669
670 switch (addr) {
671 case SSCR0:
672 s->sscr[0] = value & 0xc7ffffff;
673 s->enable = value & SSCR0_SSE;
674 if (value & SSCR0_MOD)
675 printf("%s: Attempt to use network mode\n", __FUNCTION__);
676 if (s->enable && SSCR0_DSS(value) < 4)
677 printf("%s: Wrong data size: %i bits\n", __FUNCTION__,
678 SSCR0_DSS(value));
679 if (!(value & SSCR0_SSE)) {
680 s->sssr = 0;
681 s->ssitr = 0;
682 s->rx_level = 0;
683 }
684 pxa2xx_ssp_fifo_update(s);
685 break;
686
687 case SSCR1:
688 s->sscr[1] = value;
689 if (value & (SSCR1_LBM | SSCR1_EFWR))
690 printf("%s: Attempt to use SSP test mode\n", __FUNCTION__);
691 pxa2xx_ssp_fifo_update(s);
692 break;
693
694 case SSPSP:
695 s->sspsp = value;
696 break;
697
698 case SSTO:
699 s->ssto = value;
700 break;
701
702 case SSITR:
703 s->ssitr = value & SSITR_INT;
704 pxa2xx_ssp_int_update(s);
705 break;
706
707 case SSSR:
708 s->sssr &= ~(value & SSSR_RW);
709 pxa2xx_ssp_int_update(s);
710 break;
711
712 case SSDR:
713 if (SSCR0_UWIRE(s->sscr[0])) {
714 if (s->sscr[1] & SSCR1_MWDS)
715 value &= 0xffff;
716 else
717 value &= 0xff;
718 } else
719 /* Note how 32bits overflow does no harm here */
720 value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
721
722 /* Data goes from here to the Tx FIFO and is shifted out from
723 * there directly to the slave, no need to buffer it.
724 */
725 if (s->enable) {
726 uint32_t readval;
727 readval = ssi_transfer(s->bus, value);
728 if (s->rx_level < 0x10) {
729 s->rx_fifo[(s->rx_start + s->rx_level ++) & 0xf] = readval;
730 } else {
731 s->sssr |= SSSR_ROR;
732 }
733 }
734 pxa2xx_ssp_fifo_update(s);
735 break;
736
737 case SSTSA:
738 s->sstsa = value;
739 break;
740
741 case SSRSA:
742 s->ssrsa = value;
743 break;
744
745 case SSACD:
746 s->ssacd = value;
747 break;
748
749 default:
750 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
751 break;
752 }
753 }
754
755 static const MemoryRegionOps pxa2xx_ssp_ops = {
756 .read = pxa2xx_ssp_read,
757 .write = pxa2xx_ssp_write,
758 .endianness = DEVICE_NATIVE_ENDIAN,
759 };
760
761 static void pxa2xx_ssp_save(QEMUFile *f, void *opaque)
762 {
763 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
764 int i;
765
766 qemu_put_be32(f, s->enable);
767
768 qemu_put_be32s(f, &s->sscr[0]);
769 qemu_put_be32s(f, &s->sscr[1]);
770 qemu_put_be32s(f, &s->sspsp);
771 qemu_put_be32s(f, &s->ssto);
772 qemu_put_be32s(f, &s->ssitr);
773 qemu_put_be32s(f, &s->sssr);
774 qemu_put_8s(f, &s->sstsa);
775 qemu_put_8s(f, &s->ssrsa);
776 qemu_put_8s(f, &s->ssacd);
777
778 qemu_put_byte(f, s->rx_level);
779 for (i = 0; i < s->rx_level; i ++)
780 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 0xf]);
781 }
782
783 static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id)
784 {
785 PXA2xxSSPState *s = (PXA2xxSSPState *) opaque;
786 int i;
787
788 s->enable = qemu_get_be32(f);
789
790 qemu_get_be32s(f, &s->sscr[0]);
791 qemu_get_be32s(f, &s->sscr[1]);
792 qemu_get_be32s(f, &s->sspsp);
793 qemu_get_be32s(f, &s->ssto);
794 qemu_get_be32s(f, &s->ssitr);
795 qemu_get_be32s(f, &s->sssr);
796 qemu_get_8s(f, &s->sstsa);
797 qemu_get_8s(f, &s->ssrsa);
798 qemu_get_8s(f, &s->ssacd);
799
800 s->rx_level = qemu_get_byte(f);
801 s->rx_start = 0;
802 for (i = 0; i < s->rx_level; i ++)
803 s->rx_fifo[i] = qemu_get_byte(f);
804
805 return 0;
806 }
807
808 static int pxa2xx_ssp_init(SysBusDevice *dev)
809 {
810 PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev);
811
812 sysbus_init_irq(dev, &s->irq);
813
814 memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000);
815 sysbus_init_mmio_region(dev, &s->iomem);
816 register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0,
817 pxa2xx_ssp_save, pxa2xx_ssp_load, s);
818
819 s->bus = ssi_create_bus(&dev->qdev, "ssi");
820 return 0;
821 }
822
823 /* Real-Time Clock */
824 #define RCNR 0x00 /* RTC Counter register */
825 #define RTAR 0x04 /* RTC Alarm register */
826 #define RTSR 0x08 /* RTC Status register */
827 #define RTTR 0x0c /* RTC Timer Trim register */
828 #define RDCR 0x10 /* RTC Day Counter register */
829 #define RYCR 0x14 /* RTC Year Counter register */
830 #define RDAR1 0x18 /* RTC Wristwatch Day Alarm register 1 */
831 #define RYAR1 0x1c /* RTC Wristwatch Year Alarm register 1 */
832 #define RDAR2 0x20 /* RTC Wristwatch Day Alarm register 2 */
833 #define RYAR2 0x24 /* RTC Wristwatch Year Alarm register 2 */
834 #define SWCR 0x28 /* RTC Stopwatch Counter register */
835 #define SWAR1 0x2c /* RTC Stopwatch Alarm register 1 */
836 #define SWAR2 0x30 /* RTC Stopwatch Alarm register 2 */
837 #define RTCPICR 0x34 /* RTC Periodic Interrupt Counter register */
838 #define PIAR 0x38 /* RTC Periodic Interrupt Alarm register */
839
840 typedef struct {
841 SysBusDevice busdev;
842 MemoryRegion iomem;
843 uint32_t rttr;
844 uint32_t rtsr;
845 uint32_t rtar;
846 uint32_t rdar1;
847 uint32_t rdar2;
848 uint32_t ryar1;
849 uint32_t ryar2;
850 uint32_t swar1;
851 uint32_t swar2;
852 uint32_t piar;
853 uint32_t last_rcnr;
854 uint32_t last_rdcr;
855 uint32_t last_rycr;
856 uint32_t last_swcr;
857 uint32_t last_rtcpicr;
858 int64_t last_hz;
859 int64_t last_sw;
860 int64_t last_pi;
861 QEMUTimer *rtc_hz;
862 QEMUTimer *rtc_rdal1;
863 QEMUTimer *rtc_rdal2;
864 QEMUTimer *rtc_swal1;
865 QEMUTimer *rtc_swal2;
866 QEMUTimer *rtc_pi;
867 qemu_irq rtc_irq;
868 } PXA2xxRTCState;
869
870 static inline void pxa2xx_rtc_int_update(PXA2xxRTCState *s)
871 {
872 qemu_set_irq(s->rtc_irq, !!(s->rtsr & 0x2553));
873 }
874
875 static void pxa2xx_rtc_hzupdate(PXA2xxRTCState *s)
876 {
877 int64_t rt = qemu_get_clock_ms(rt_clock);
878 s->last_rcnr += ((rt - s->last_hz) << 15) /
879 (1000 * ((s->rttr & 0xffff) + 1));
880 s->last_rdcr += ((rt - s->last_hz) << 15) /
881 (1000 * ((s->rttr & 0xffff) + 1));
882 s->last_hz = rt;
883 }
884
885 static void pxa2xx_rtc_swupdate(PXA2xxRTCState *s)
886 {
887 int64_t rt = qemu_get_clock_ms(rt_clock);
888 if (s->rtsr & (1 << 12))
889 s->last_swcr += (rt - s->last_sw) / 10;
890 s->last_sw = rt;
891 }
892
893 static void pxa2xx_rtc_piupdate(PXA2xxRTCState *s)
894 {
895 int64_t rt = qemu_get_clock_ms(rt_clock);
896 if (s->rtsr & (1 << 15))
897 s->last_swcr += rt - s->last_pi;
898 s->last_pi = rt;
899 }
900
901 static inline void pxa2xx_rtc_alarm_update(PXA2xxRTCState *s,
902 uint32_t rtsr)
903 {
904 if ((rtsr & (1 << 2)) && !(rtsr & (1 << 0)))
905 qemu_mod_timer(s->rtc_hz, s->last_hz +
906 (((s->rtar - s->last_rcnr) * 1000 *
907 ((s->rttr & 0xffff) + 1)) >> 15));
908 else
909 qemu_del_timer(s->rtc_hz);
910
911 if ((rtsr & (1 << 5)) && !(rtsr & (1 << 4)))
912 qemu_mod_timer(s->rtc_rdal1, s->last_hz +
913 (((s->rdar1 - s->last_rdcr) * 1000 *
914 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
915 else
916 qemu_del_timer(s->rtc_rdal1);
917
918 if ((rtsr & (1 << 7)) && !(rtsr & (1 << 6)))
919 qemu_mod_timer(s->rtc_rdal2, s->last_hz +
920 (((s->rdar2 - s->last_rdcr) * 1000 *
921 ((s->rttr & 0xffff) + 1)) >> 15)); /* TODO: fixup */
922 else
923 qemu_del_timer(s->rtc_rdal2);
924
925 if ((rtsr & 0x1200) == 0x1200 && !(rtsr & (1 << 8)))
926 qemu_mod_timer(s->rtc_swal1, s->last_sw +
927 (s->swar1 - s->last_swcr) * 10); /* TODO: fixup */
928 else
929 qemu_del_timer(s->rtc_swal1);
930
931 if ((rtsr & 0x1800) == 0x1800 && !(rtsr & (1 << 10)))
932 qemu_mod_timer(s->rtc_swal2, s->last_sw +
933 (s->swar2 - s->last_swcr) * 10); /* TODO: fixup */
934 else
935 qemu_del_timer(s->rtc_swal2);
936
937 if ((rtsr & 0xc000) == 0xc000 && !(rtsr & (1 << 13)))
938 qemu_mod_timer(s->rtc_pi, s->last_pi +
939 (s->piar & 0xffff) - s->last_rtcpicr);
940 else
941 qemu_del_timer(s->rtc_pi);
942 }
943
944 static inline void pxa2xx_rtc_hz_tick(void *opaque)
945 {
946 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
947 s->rtsr |= (1 << 0);
948 pxa2xx_rtc_alarm_update(s, s->rtsr);
949 pxa2xx_rtc_int_update(s);
950 }
951
952 static inline void pxa2xx_rtc_rdal1_tick(void *opaque)
953 {
954 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
955 s->rtsr |= (1 << 4);
956 pxa2xx_rtc_alarm_update(s, s->rtsr);
957 pxa2xx_rtc_int_update(s);
958 }
959
960 static inline void pxa2xx_rtc_rdal2_tick(void *opaque)
961 {
962 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
963 s->rtsr |= (1 << 6);
964 pxa2xx_rtc_alarm_update(s, s->rtsr);
965 pxa2xx_rtc_int_update(s);
966 }
967
968 static inline void pxa2xx_rtc_swal1_tick(void *opaque)
969 {
970 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
971 s->rtsr |= (1 << 8);
972 pxa2xx_rtc_alarm_update(s, s->rtsr);
973 pxa2xx_rtc_int_update(s);
974 }
975
976 static inline void pxa2xx_rtc_swal2_tick(void *opaque)
977 {
978 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
979 s->rtsr |= (1 << 10);
980 pxa2xx_rtc_alarm_update(s, s->rtsr);
981 pxa2xx_rtc_int_update(s);
982 }
983
984 static inline void pxa2xx_rtc_pi_tick(void *opaque)
985 {
986 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
987 s->rtsr |= (1 << 13);
988 pxa2xx_rtc_piupdate(s);
989 s->last_rtcpicr = 0;
990 pxa2xx_rtc_alarm_update(s, s->rtsr);
991 pxa2xx_rtc_int_update(s);
992 }
993
994 static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr,
995 unsigned size)
996 {
997 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
998
999 switch (addr) {
1000 case RTTR:
1001 return s->rttr;
1002 case RTSR:
1003 return s->rtsr;
1004 case RTAR:
1005 return s->rtar;
1006 case RDAR1:
1007 return s->rdar1;
1008 case RDAR2:
1009 return s->rdar2;
1010 case RYAR1:
1011 return s->ryar1;
1012 case RYAR2:
1013 return s->ryar2;
1014 case SWAR1:
1015 return s->swar1;
1016 case SWAR2:
1017 return s->swar2;
1018 case PIAR:
1019 return s->piar;
1020 case RCNR:
1021 return s->last_rcnr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1022 (1000 * ((s->rttr & 0xffff) + 1));
1023 case RDCR:
1024 return s->last_rdcr + ((qemu_get_clock_ms(rt_clock) - s->last_hz) << 15) /
1025 (1000 * ((s->rttr & 0xffff) + 1));
1026 case RYCR:
1027 return s->last_rycr;
1028 case SWCR:
1029 if (s->rtsr & (1 << 12))
1030 return s->last_swcr + (qemu_get_clock_ms(rt_clock) - s->last_sw) / 10;
1031 else
1032 return s->last_swcr;
1033 default:
1034 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1035 break;
1036 }
1037 return 0;
1038 }
1039
1040 static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr,
1041 uint64_t value64, unsigned size)
1042 {
1043 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1044 uint32_t value = value64;
1045
1046 switch (addr) {
1047 case RTTR:
1048 if (!(s->rttr & (1 << 31))) {
1049 pxa2xx_rtc_hzupdate(s);
1050 s->rttr = value;
1051 pxa2xx_rtc_alarm_update(s, s->rtsr);
1052 }
1053 break;
1054
1055 case RTSR:
1056 if ((s->rtsr ^ value) & (1 << 15))
1057 pxa2xx_rtc_piupdate(s);
1058
1059 if ((s->rtsr ^ value) & (1 << 12))
1060 pxa2xx_rtc_swupdate(s);
1061
1062 if (((s->rtsr ^ value) & 0x4aac) | (value & ~0xdaac))
1063 pxa2xx_rtc_alarm_update(s, value);
1064
1065 s->rtsr = (value & 0xdaac) | (s->rtsr & ~(value & ~0xdaac));
1066 pxa2xx_rtc_int_update(s);
1067 break;
1068
1069 case RTAR:
1070 s->rtar = value;
1071 pxa2xx_rtc_alarm_update(s, s->rtsr);
1072 break;
1073
1074 case RDAR1:
1075 s->rdar1 = value;
1076 pxa2xx_rtc_alarm_update(s, s->rtsr);
1077 break;
1078
1079 case RDAR2:
1080 s->rdar2 = value;
1081 pxa2xx_rtc_alarm_update(s, s->rtsr);
1082 break;
1083
1084 case RYAR1:
1085 s->ryar1 = value;
1086 pxa2xx_rtc_alarm_update(s, s->rtsr);
1087 break;
1088
1089 case RYAR2:
1090 s->ryar2 = value;
1091 pxa2xx_rtc_alarm_update(s, s->rtsr);
1092 break;
1093
1094 case SWAR1:
1095 pxa2xx_rtc_swupdate(s);
1096 s->swar1 = value;
1097 s->last_swcr = 0;
1098 pxa2xx_rtc_alarm_update(s, s->rtsr);
1099 break;
1100
1101 case SWAR2:
1102 s->swar2 = value;
1103 pxa2xx_rtc_alarm_update(s, s->rtsr);
1104 break;
1105
1106 case PIAR:
1107 s->piar = value;
1108 pxa2xx_rtc_alarm_update(s, s->rtsr);
1109 break;
1110
1111 case RCNR:
1112 pxa2xx_rtc_hzupdate(s);
1113 s->last_rcnr = value;
1114 pxa2xx_rtc_alarm_update(s, s->rtsr);
1115 break;
1116
1117 case RDCR:
1118 pxa2xx_rtc_hzupdate(s);
1119 s->last_rdcr = value;
1120 pxa2xx_rtc_alarm_update(s, s->rtsr);
1121 break;
1122
1123 case RYCR:
1124 s->last_rycr = value;
1125 break;
1126
1127 case SWCR:
1128 pxa2xx_rtc_swupdate(s);
1129 s->last_swcr = value;
1130 pxa2xx_rtc_alarm_update(s, s->rtsr);
1131 break;
1132
1133 case RTCPICR:
1134 pxa2xx_rtc_piupdate(s);
1135 s->last_rtcpicr = value & 0xffff;
1136 pxa2xx_rtc_alarm_update(s, s->rtsr);
1137 break;
1138
1139 default:
1140 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1141 }
1142 }
1143
1144 static const MemoryRegionOps pxa2xx_rtc_ops = {
1145 .read = pxa2xx_rtc_read,
1146 .write = pxa2xx_rtc_write,
1147 .endianness = DEVICE_NATIVE_ENDIAN,
1148 };
1149
1150 static int pxa2xx_rtc_init(SysBusDevice *dev)
1151 {
1152 PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev);
1153 struct tm tm;
1154 int wom;
1155
1156 s->rttr = 0x7fff;
1157 s->rtsr = 0;
1158
1159 qemu_get_timedate(&tm, 0);
1160 wom = ((tm.tm_mday - 1) / 7) + 1;
1161
1162 s->last_rcnr = (uint32_t) mktimegm(&tm);
1163 s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
1164 (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
1165 s->last_rycr = ((tm.tm_year + 1900) << 9) |
1166 ((tm.tm_mon + 1) << 5) | tm.tm_mday;
1167 s->last_swcr = (tm.tm_hour << 19) |
1168 (tm.tm_min << 13) | (tm.tm_sec << 7);
1169 s->last_rtcpicr = 0;
1170 s->last_hz = s->last_sw = s->last_pi = qemu_get_clock_ms(rt_clock);
1171
1172 s->rtc_hz = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_hz_tick, s);
1173 s->rtc_rdal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal1_tick, s);
1174 s->rtc_rdal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_rdal2_tick, s);
1175 s->rtc_swal1 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal1_tick, s);
1176 s->rtc_swal2 = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_swal2_tick, s);
1177 s->rtc_pi = qemu_new_timer_ms(rt_clock, pxa2xx_rtc_pi_tick, s);
1178
1179 sysbus_init_irq(dev, &s->rtc_irq);
1180
1181 memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000);
1182 sysbus_init_mmio_region(dev, &s->iomem);
1183
1184 return 0;
1185 }
1186
1187 static void pxa2xx_rtc_pre_save(void *opaque)
1188 {
1189 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1190
1191 pxa2xx_rtc_hzupdate(s);
1192 pxa2xx_rtc_piupdate(s);
1193 pxa2xx_rtc_swupdate(s);
1194 }
1195
1196 static int pxa2xx_rtc_post_load(void *opaque, int version_id)
1197 {
1198 PXA2xxRTCState *s = (PXA2xxRTCState *) opaque;
1199
1200 pxa2xx_rtc_alarm_update(s, s->rtsr);
1201
1202 return 0;
1203 }
1204
1205 static const VMStateDescription vmstate_pxa2xx_rtc_regs = {
1206 .name = "pxa2xx_rtc",
1207 .version_id = 0,
1208 .minimum_version_id = 0,
1209 .minimum_version_id_old = 0,
1210 .pre_save = pxa2xx_rtc_pre_save,
1211 .post_load = pxa2xx_rtc_post_load,
1212 .fields = (VMStateField[]) {
1213 VMSTATE_UINT32(rttr, PXA2xxRTCState),
1214 VMSTATE_UINT32(rtsr, PXA2xxRTCState),
1215 VMSTATE_UINT32(rtar, PXA2xxRTCState),
1216 VMSTATE_UINT32(rdar1, PXA2xxRTCState),
1217 VMSTATE_UINT32(rdar2, PXA2xxRTCState),
1218 VMSTATE_UINT32(ryar1, PXA2xxRTCState),
1219 VMSTATE_UINT32(ryar2, PXA2xxRTCState),
1220 VMSTATE_UINT32(swar1, PXA2xxRTCState),
1221 VMSTATE_UINT32(swar2, PXA2xxRTCState),
1222 VMSTATE_UINT32(piar, PXA2xxRTCState),
1223 VMSTATE_UINT32(last_rcnr, PXA2xxRTCState),
1224 VMSTATE_UINT32(last_rdcr, PXA2xxRTCState),
1225 VMSTATE_UINT32(last_rycr, PXA2xxRTCState),
1226 VMSTATE_UINT32(last_swcr, PXA2xxRTCState),
1227 VMSTATE_UINT32(last_rtcpicr, PXA2xxRTCState),
1228 VMSTATE_INT64(last_hz, PXA2xxRTCState),
1229 VMSTATE_INT64(last_sw, PXA2xxRTCState),
1230 VMSTATE_INT64(last_pi, PXA2xxRTCState),
1231 VMSTATE_END_OF_LIST(),
1232 },
1233 };
1234
1235 static SysBusDeviceInfo pxa2xx_rtc_sysbus_info = {
1236 .init = pxa2xx_rtc_init,
1237 .qdev.name = "pxa2xx_rtc",
1238 .qdev.desc = "PXA2xx RTC Controller",
1239 .qdev.size = sizeof(PXA2xxRTCState),
1240 .qdev.vmsd = &vmstate_pxa2xx_rtc_regs,
1241 };
1242
1243 /* I2C Interface */
1244 typedef struct {
1245 i2c_slave i2c;
1246 PXA2xxI2CState *host;
1247 } PXA2xxI2CSlaveState;
1248
1249 struct PXA2xxI2CState {
1250 SysBusDevice busdev;
1251 MemoryRegion iomem;
1252 PXA2xxI2CSlaveState *slave;
1253 i2c_bus *bus;
1254 qemu_irq irq;
1255 uint32_t offset;
1256 uint32_t region_size;
1257
1258 uint16_t control;
1259 uint16_t status;
1260 uint8_t ibmr;
1261 uint8_t data;
1262 };
1263
1264 #define IBMR 0x80 /* I2C Bus Monitor register */
1265 #define IDBR 0x88 /* I2C Data Buffer register */
1266 #define ICR 0x90 /* I2C Control register */
1267 #define ISR 0x98 /* I2C Status register */
1268 #define ISAR 0xa0 /* I2C Slave Address register */
1269
1270 static void pxa2xx_i2c_update(PXA2xxI2CState *s)
1271 {
1272 uint16_t level = 0;
1273 level |= s->status & s->control & (1 << 10); /* BED */
1274 level |= (s->status & (1 << 7)) && (s->control & (1 << 9)); /* IRF */
1275 level |= (s->status & (1 << 6)) && (s->control & (1 << 8)); /* ITE */
1276 level |= s->status & (1 << 9); /* SAD */
1277 qemu_set_irq(s->irq, !!level);
1278 }
1279
1280 /* These are only stubs now. */
1281 static void pxa2xx_i2c_event(i2c_slave *i2c, enum i2c_event event)
1282 {
1283 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1284 PXA2xxI2CState *s = slave->host;
1285
1286 switch (event) {
1287 case I2C_START_SEND:
1288 s->status |= (1 << 9); /* set SAD */
1289 s->status &= ~(1 << 0); /* clear RWM */
1290 break;
1291 case I2C_START_RECV:
1292 s->status |= (1 << 9); /* set SAD */
1293 s->status |= 1 << 0; /* set RWM */
1294 break;
1295 case I2C_FINISH:
1296 s->status |= (1 << 4); /* set SSD */
1297 break;
1298 case I2C_NACK:
1299 s->status |= 1 << 1; /* set ACKNAK */
1300 break;
1301 }
1302 pxa2xx_i2c_update(s);
1303 }
1304
1305 static int pxa2xx_i2c_rx(i2c_slave *i2c)
1306 {
1307 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1308 PXA2xxI2CState *s = slave->host;
1309 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1310 return 0;
1311
1312 if (s->status & (1 << 0)) { /* RWM */
1313 s->status |= 1 << 6; /* set ITE */
1314 }
1315 pxa2xx_i2c_update(s);
1316
1317 return s->data;
1318 }
1319
1320 static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data)
1321 {
1322 PXA2xxI2CSlaveState *slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, i2c);
1323 PXA2xxI2CState *s = slave->host;
1324 if ((s->control & (1 << 14)) || !(s->control & (1 << 6)))
1325 return 1;
1326
1327 if (!(s->status & (1 << 0))) { /* RWM */
1328 s->status |= 1 << 7; /* set IRF */
1329 s->data = data;
1330 }
1331 pxa2xx_i2c_update(s);
1332
1333 return 1;
1334 }
1335
1336 static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr,
1337 unsigned size)
1338 {
1339 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1340
1341 addr -= s->offset;
1342 switch (addr) {
1343 case ICR:
1344 return s->control;
1345 case ISR:
1346 return s->status | (i2c_bus_busy(s->bus) << 2);
1347 case ISAR:
1348 return s->slave->i2c.address;
1349 case IDBR:
1350 return s->data;
1351 case IBMR:
1352 if (s->status & (1 << 2))
1353 s->ibmr ^= 3; /* Fake SCL and SDA pin changes */
1354 else
1355 s->ibmr = 0;
1356 return s->ibmr;
1357 default:
1358 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1359 break;
1360 }
1361 return 0;
1362 }
1363
1364 static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr,
1365 uint64_t value64, unsigned size)
1366 {
1367 PXA2xxI2CState *s = (PXA2xxI2CState *) opaque;
1368 uint32_t value = value64;
1369 int ack;
1370
1371 addr -= s->offset;
1372 switch (addr) {
1373 case ICR:
1374 s->control = value & 0xfff7;
1375 if ((value & (1 << 3)) && (value & (1 << 6))) { /* TB and IUE */
1376 /* TODO: slave mode */
1377 if (value & (1 << 0)) { /* START condition */
1378 if (s->data & 1)
1379 s->status |= 1 << 0; /* set RWM */
1380 else
1381 s->status &= ~(1 << 0); /* clear RWM */
1382 ack = !i2c_start_transfer(s->bus, s->data >> 1, s->data & 1);
1383 } else {
1384 if (s->status & (1 << 0)) { /* RWM */
1385 s->data = i2c_recv(s->bus);
1386 if (value & (1 << 2)) /* ACKNAK */
1387 i2c_nack(s->bus);
1388 ack = 1;
1389 } else
1390 ack = !i2c_send(s->bus, s->data);
1391 }
1392
1393 if (value & (1 << 1)) /* STOP condition */
1394 i2c_end_transfer(s->bus);
1395
1396 if (ack) {
1397 if (value & (1 << 0)) /* START condition */
1398 s->status |= 1 << 6; /* set ITE */
1399 else
1400 if (s->status & (1 << 0)) /* RWM */
1401 s->status |= 1 << 7; /* set IRF */
1402 else
1403 s->status |= 1 << 6; /* set ITE */
1404 s->status &= ~(1 << 1); /* clear ACKNAK */
1405 } else {
1406 s->status |= 1 << 6; /* set ITE */
1407 s->status |= 1 << 10; /* set BED */
1408 s->status |= 1 << 1; /* set ACKNAK */
1409 }
1410 }
1411 if (!(value & (1 << 3)) && (value & (1 << 6))) /* !TB and IUE */
1412 if (value & (1 << 4)) /* MA */
1413 i2c_end_transfer(s->bus);
1414 pxa2xx_i2c_update(s);
1415 break;
1416
1417 case ISR:
1418 s->status &= ~(value & 0x07f0);
1419 pxa2xx_i2c_update(s);
1420 break;
1421
1422 case ISAR:
1423 i2c_set_slave_address(&s->slave->i2c, value & 0x7f);
1424 break;
1425
1426 case IDBR:
1427 s->data = value & 0xff;
1428 break;
1429
1430 default:
1431 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1432 }
1433 }
1434
1435 static const MemoryRegionOps pxa2xx_i2c_ops = {
1436 .read = pxa2xx_i2c_read,
1437 .write = pxa2xx_i2c_write,
1438 .endianness = DEVICE_NATIVE_ENDIAN,
1439 };
1440
1441 static const VMStateDescription vmstate_pxa2xx_i2c_slave = {
1442 .name = "pxa2xx_i2c_slave",
1443 .version_id = 1,
1444 .minimum_version_id = 1,
1445 .minimum_version_id_old = 1,
1446 .fields = (VMStateField []) {
1447 VMSTATE_I2C_SLAVE(i2c, PXA2xxI2CSlaveState),
1448 VMSTATE_END_OF_LIST()
1449 }
1450 };
1451
1452 static const VMStateDescription vmstate_pxa2xx_i2c = {
1453 .name = "pxa2xx_i2c",
1454 .version_id = 1,
1455 .minimum_version_id = 1,
1456 .minimum_version_id_old = 1,
1457 .fields = (VMStateField []) {
1458 VMSTATE_UINT16(control, PXA2xxI2CState),
1459 VMSTATE_UINT16(status, PXA2xxI2CState),
1460 VMSTATE_UINT8(ibmr, PXA2xxI2CState),
1461 VMSTATE_UINT8(data, PXA2xxI2CState),
1462 VMSTATE_STRUCT_POINTER(slave, PXA2xxI2CState,
1463 vmstate_pxa2xx_i2c_slave, PXA2xxI2CSlaveState *),
1464 VMSTATE_END_OF_LIST()
1465 }
1466 };
1467
1468 static int pxa2xx_i2c_slave_init(i2c_slave *i2c)
1469 {
1470 /* Nothing to do. */
1471 return 0;
1472 }
1473
1474 static I2CSlaveInfo pxa2xx_i2c_slave_info = {
1475 .qdev.name = "pxa2xx-i2c-slave",
1476 .qdev.size = sizeof(PXA2xxI2CSlaveState),
1477 .init = pxa2xx_i2c_slave_init,
1478 .event = pxa2xx_i2c_event,
1479 .recv = pxa2xx_i2c_rx,
1480 .send = pxa2xx_i2c_tx
1481 };
1482
1483 PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
1484 qemu_irq irq, uint32_t region_size)
1485 {
1486 DeviceState *dev;
1487 SysBusDevice *i2c_dev;
1488 PXA2xxI2CState *s;
1489
1490 i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
1491 qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
1492 qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
1493 base - (base & (~region_size) & TARGET_PAGE_MASK));
1494
1495 qdev_init_nofail(&i2c_dev->qdev);
1496
1497 sysbus_mmio_map(i2c_dev, 0, base & ~region_size);
1498 sysbus_connect_irq(i2c_dev, 0, irq);
1499
1500 s = FROM_SYSBUS(PXA2xxI2CState, i2c_dev);
1501 /* FIXME: Should the slave device really be on a separate bus? */
1502 dev = i2c_create_slave(i2c_init_bus(NULL, "dummy"), "pxa2xx-i2c-slave", 0);
1503 s->slave = FROM_I2C_SLAVE(PXA2xxI2CSlaveState, I2C_SLAVE_FROM_QDEV(dev));
1504 s->slave->host = s;
1505
1506 return s;
1507 }
1508
1509 static int pxa2xx_i2c_initfn(SysBusDevice *dev)
1510 {
1511 PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev);
1512
1513 s->bus = i2c_init_bus(&dev->qdev, "i2c");
1514
1515 memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s,
1516 "pxa2xx-i2x", s->region_size);
1517 sysbus_init_mmio_region(dev, &s->iomem);
1518 sysbus_init_irq(dev, &s->irq);
1519
1520 return 0;
1521 }
1522
1523 i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s)
1524 {
1525 return s->bus;
1526 }
1527
1528 static SysBusDeviceInfo pxa2xx_i2c_info = {
1529 .init = pxa2xx_i2c_initfn,
1530 .qdev.name = "pxa2xx_i2c",
1531 .qdev.desc = "PXA2xx I2C Bus Controller",
1532 .qdev.size = sizeof(PXA2xxI2CState),
1533 .qdev.vmsd = &vmstate_pxa2xx_i2c,
1534 .qdev.props = (Property[]) {
1535 DEFINE_PROP_UINT32("size", PXA2xxI2CState, region_size, 0x10000),
1536 DEFINE_PROP_UINT32("offset", PXA2xxI2CState, offset, 0),
1537 DEFINE_PROP_END_OF_LIST(),
1538 },
1539 };
1540
1541 /* PXA Inter-IC Sound Controller */
1542 static void pxa2xx_i2s_reset(PXA2xxI2SState *i2s)
1543 {
1544 i2s->rx_len = 0;
1545 i2s->tx_len = 0;
1546 i2s->fifo_len = 0;
1547 i2s->clk = 0x1a;
1548 i2s->control[0] = 0x00;
1549 i2s->control[1] = 0x00;
1550 i2s->status = 0x00;
1551 i2s->mask = 0x00;
1552 }
1553
1554 #define SACR_TFTH(val) ((val >> 8) & 0xf)
1555 #define SACR_RFTH(val) ((val >> 12) & 0xf)
1556 #define SACR_DREC(val) (val & (1 << 3))
1557 #define SACR_DPRL(val) (val & (1 << 4))
1558
1559 static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
1560 {
1561 int rfs, tfs;
1562 rfs = SACR_RFTH(i2s->control[0]) < i2s->rx_len &&
1563 !SACR_DREC(i2s->control[1]);
1564 tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
1565 i2s->enable && !SACR_DPRL(i2s->control[1]);
1566
1567 qemu_set_irq(i2s->rx_dma, rfs);
1568 qemu_set_irq(i2s->tx_dma, tfs);
1569
1570 i2s->status &= 0xe0;
1571 if (i2s->fifo_len < 16 || !i2s->enable)
1572 i2s->status |= 1 << 0; /* TNF */
1573 if (i2s->rx_len)
1574 i2s->status |= 1 << 1; /* RNE */
1575 if (i2s->enable)
1576 i2s->status |= 1 << 2; /* BSY */
1577 if (tfs)
1578 i2s->status |= 1 << 3; /* TFS */
1579 if (rfs)
1580 i2s->status |= 1 << 4; /* RFS */
1581 if (!(i2s->tx_len && i2s->enable))
1582 i2s->status |= i2s->fifo_len << 8; /* TFL */
1583 i2s->status |= MAX(i2s->rx_len, 0xf) << 12; /* RFL */
1584
1585 qemu_set_irq(i2s->irq, i2s->status & i2s->mask);
1586 }
1587
1588 #define SACR0 0x00 /* Serial Audio Global Control register */
1589 #define SACR1 0x04 /* Serial Audio I2S/MSB-Justified Control register */
1590 #define SASR0 0x0c /* Serial Audio Interface and FIFO Status register */
1591 #define SAIMR 0x14 /* Serial Audio Interrupt Mask register */
1592 #define SAICR 0x18 /* Serial Audio Interrupt Clear register */
1593 #define SADIV 0x60 /* Serial Audio Clock Divider register */
1594 #define SADR 0x80 /* Serial Audio Data register */
1595
1596 static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr,
1597 unsigned size)
1598 {
1599 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1600
1601 switch (addr) {
1602 case SACR0:
1603 return s->control[0];
1604 case SACR1:
1605 return s->control[1];
1606 case SASR0:
1607 return s->status;
1608 case SAIMR:
1609 return s->mask;
1610 case SAICR:
1611 return 0;
1612 case SADIV:
1613 return s->clk;
1614 case SADR:
1615 if (s->rx_len > 0) {
1616 s->rx_len --;
1617 pxa2xx_i2s_update(s);
1618 return s->codec_in(s->opaque);
1619 }
1620 return 0;
1621 default:
1622 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1623 break;
1624 }
1625 return 0;
1626 }
1627
1628 static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr,
1629 uint64_t value, unsigned size)
1630 {
1631 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1632 uint32_t *sample;
1633
1634 switch (addr) {
1635 case SACR0:
1636 if (value & (1 << 3)) /* RST */
1637 pxa2xx_i2s_reset(s);
1638 s->control[0] = value & 0xff3d;
1639 if (!s->enable && (value & 1) && s->tx_len) { /* ENB */
1640 for (sample = s->fifo; s->fifo_len > 0; s->fifo_len --, sample ++)
1641 s->codec_out(s->opaque, *sample);
1642 s->status &= ~(1 << 7); /* I2SOFF */
1643 }
1644 if (value & (1 << 4)) /* EFWR */
1645 printf("%s: Attempt to use special function\n", __FUNCTION__);
1646 s->enable = (value & 9) == 1; /* ENB && !RST*/
1647 pxa2xx_i2s_update(s);
1648 break;
1649 case SACR1:
1650 s->control[1] = value & 0x0039;
1651 if (value & (1 << 5)) /* ENLBF */
1652 printf("%s: Attempt to use loopback function\n", __FUNCTION__);
1653 if (value & (1 << 4)) /* DPRL */
1654 s->fifo_len = 0;
1655 pxa2xx_i2s_update(s);
1656 break;
1657 case SAIMR:
1658 s->mask = value & 0x0078;
1659 pxa2xx_i2s_update(s);
1660 break;
1661 case SAICR:
1662 s->status &= ~(value & (3 << 5));
1663 pxa2xx_i2s_update(s);
1664 break;
1665 case SADIV:
1666 s->clk = value & 0x007f;
1667 break;
1668 case SADR:
1669 if (s->tx_len && s->enable) {
1670 s->tx_len --;
1671 pxa2xx_i2s_update(s);
1672 s->codec_out(s->opaque, value);
1673 } else if (s->fifo_len < 16) {
1674 s->fifo[s->fifo_len ++] = value;
1675 pxa2xx_i2s_update(s);
1676 }
1677 break;
1678 default:
1679 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1680 }
1681 }
1682
1683 static const MemoryRegionOps pxa2xx_i2s_ops = {
1684 .read = pxa2xx_i2s_read,
1685 .write = pxa2xx_i2s_write,
1686 .endianness = DEVICE_NATIVE_ENDIAN,
1687 };
1688
1689 static const VMStateDescription vmstate_pxa2xx_i2s = {
1690 .name = "pxa2xx_i2s",
1691 .version_id = 0,
1692 .minimum_version_id = 0,
1693 .minimum_version_id_old = 0,
1694 .fields = (VMStateField[]) {
1695 VMSTATE_UINT32_ARRAY(control, PXA2xxI2SState, 2),
1696 VMSTATE_UINT32(status, PXA2xxI2SState),
1697 VMSTATE_UINT32(mask, PXA2xxI2SState),
1698 VMSTATE_UINT32(clk, PXA2xxI2SState),
1699 VMSTATE_INT32(enable, PXA2xxI2SState),
1700 VMSTATE_INT32(rx_len, PXA2xxI2SState),
1701 VMSTATE_INT32(tx_len, PXA2xxI2SState),
1702 VMSTATE_INT32(fifo_len, PXA2xxI2SState),
1703 VMSTATE_END_OF_LIST()
1704 }
1705 };
1706
1707 static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
1708 {
1709 PXA2xxI2SState *s = (PXA2xxI2SState *) opaque;
1710 uint32_t *sample;
1711
1712 /* Signal FIFO errors */
1713 if (s->enable && s->tx_len)
1714 s->status |= 1 << 5; /* TUR */
1715 if (s->enable && s->rx_len)
1716 s->status |= 1 << 6; /* ROR */
1717
1718 /* Should be tx - MIN(tx, s->fifo_len) but we don't really need to
1719 * handle the cases where it makes a difference. */
1720 s->tx_len = tx - s->fifo_len;
1721 s->rx_len = rx;
1722 /* Note that is s->codec_out wasn't set, we wouldn't get called. */
1723 if (s->enable)
1724 for (sample = s->fifo; s->fifo_len; s->fifo_len --, sample ++)
1725 s->codec_out(s->opaque, *sample);
1726 pxa2xx_i2s_update(s);
1727 }
1728
1729 static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem,
1730 target_phys_addr_t base,
1731 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
1732 {
1733 PXA2xxI2SState *s = (PXA2xxI2SState *)
1734 g_malloc0(sizeof(PXA2xxI2SState));
1735
1736 s->irq = irq;
1737 s->rx_dma = rx_dma;
1738 s->tx_dma = tx_dma;
1739 s->data_req = pxa2xx_i2s_data_req;
1740
1741 pxa2xx_i2s_reset(s);
1742
1743 memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s,
1744 "pxa2xx-i2s", 0x100000);
1745 memory_region_add_subregion(sysmem, base, &s->iomem);
1746
1747 vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s);
1748
1749 return s;
1750 }
1751
1752 /* PXA Fast Infra-red Communications Port */
1753 struct PXA2xxFIrState {
1754 MemoryRegion iomem;
1755 qemu_irq irq;
1756 qemu_irq rx_dma;
1757 qemu_irq tx_dma;
1758 int enable;
1759 CharDriverState *chr;
1760
1761 uint8_t control[3];
1762 uint8_t status[2];
1763
1764 int rx_len;
1765 int rx_start;
1766 uint8_t rx_fifo[64];
1767 };
1768
1769 static void pxa2xx_fir_reset(PXA2xxFIrState *s)
1770 {
1771 s->control[0] = 0x00;
1772 s->control[1] = 0x00;
1773 s->control[2] = 0x00;
1774 s->status[0] = 0x00;
1775 s->status[1] = 0x00;
1776 s->enable = 0;
1777 }
1778
1779 static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
1780 {
1781 static const int tresh[4] = { 8, 16, 32, 0 };
1782 int intr = 0;
1783 if ((s->control[0] & (1 << 4)) && /* RXE */
1784 s->rx_len >= tresh[s->control[2] & 3]) /* TRIG */
1785 s->status[0] |= 1 << 4; /* RFS */
1786 else
1787 s->status[0] &= ~(1 << 4); /* RFS */
1788 if (s->control[0] & (1 << 3)) /* TXE */
1789 s->status[0] |= 1 << 3; /* TFS */
1790 else
1791 s->status[0] &= ~(1 << 3); /* TFS */
1792 if (s->rx_len)
1793 s->status[1] |= 1 << 2; /* RNE */
1794 else
1795 s->status[1] &= ~(1 << 2); /* RNE */
1796 if (s->control[0] & (1 << 4)) /* RXE */
1797 s->status[1] |= 1 << 0; /* RSY */
1798 else
1799 s->status[1] &= ~(1 << 0); /* RSY */
1800
1801 intr |= (s->control[0] & (1 << 5)) && /* RIE */
1802 (s->status[0] & (1 << 4)); /* RFS */
1803 intr |= (s->control[0] & (1 << 6)) && /* TIE */
1804 (s->status[0] & (1 << 3)); /* TFS */
1805 intr |= (s->control[2] & (1 << 4)) && /* TRAIL */
1806 (s->status[0] & (1 << 6)); /* EOC */
1807 intr |= (s->control[0] & (1 << 2)) && /* TUS */
1808 (s->status[0] & (1 << 1)); /* TUR */
1809 intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
1810
1811 qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
1812 qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
1813
1814 qemu_set_irq(s->irq, intr && s->enable);
1815 }
1816
1817 #define ICCR0 0x00 /* FICP Control register 0 */
1818 #define ICCR1 0x04 /* FICP Control register 1 */
1819 #define ICCR2 0x08 /* FICP Control register 2 */
1820 #define ICDR 0x0c /* FICP Data register */
1821 #define ICSR0 0x14 /* FICP Status register 0 */
1822 #define ICSR1 0x18 /* FICP Status register 1 */
1823 #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */
1824
1825 static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr,
1826 unsigned size)
1827 {
1828 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1829 uint8_t ret;
1830
1831 switch (addr) {
1832 case ICCR0:
1833 return s->control[0];
1834 case ICCR1:
1835 return s->control[1];
1836 case ICCR2:
1837 return s->control[2];
1838 case ICDR:
1839 s->status[0] &= ~0x01;
1840 s->status[1] &= ~0x72;
1841 if (s->rx_len) {
1842 s->rx_len --;
1843 ret = s->rx_fifo[s->rx_start ++];
1844 s->rx_start &= 63;
1845 pxa2xx_fir_update(s);
1846 return ret;
1847 }
1848 printf("%s: Rx FIFO underrun.\n", __FUNCTION__);
1849 break;
1850 case ICSR0:
1851 return s->status[0];
1852 case ICSR1:
1853 return s->status[1] | (1 << 3); /* TNF */
1854 case ICFOR:
1855 return s->rx_len;
1856 default:
1857 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1858 break;
1859 }
1860 return 0;
1861 }
1862
1863 static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
1864 uint64_t value64, unsigned size)
1865 {
1866 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1867 uint32_t value = value64;
1868 uint8_t ch;
1869
1870 switch (addr) {
1871 case ICCR0:
1872 s->control[0] = value;
1873 if (!(value & (1 << 4))) /* RXE */
1874 s->rx_len = s->rx_start = 0;
1875 if (!(value & (1 << 3))) { /* TXE */
1876 /* Nop */
1877 }
1878 s->enable = value & 1; /* ITR */
1879 if (!s->enable)
1880 s->status[0] = 0;
1881 pxa2xx_fir_update(s);
1882 break;
1883 case ICCR1:
1884 s->control[1] = value;
1885 break;
1886 case ICCR2:
1887 s->control[2] = value & 0x3f;
1888 pxa2xx_fir_update(s);
1889 break;
1890 case ICDR:
1891 if (s->control[2] & (1 << 2)) /* TXP */
1892 ch = value;
1893 else
1894 ch = ~value;
1895 if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
1896 qemu_chr_fe_write(s->chr, &ch, 1);
1897 break;
1898 case ICSR0:
1899 s->status[0] &= ~(value & 0x66);
1900 pxa2xx_fir_update(s);
1901 break;
1902 case ICFOR:
1903 break;
1904 default:
1905 printf("%s: Bad register " REG_FMT "\n", __FUNCTION__, addr);
1906 }
1907 }
1908
1909 static const MemoryRegionOps pxa2xx_fir_ops = {
1910 .read = pxa2xx_fir_read,
1911 .write = pxa2xx_fir_write,
1912 .endianness = DEVICE_NATIVE_ENDIAN,
1913 };
1914
1915 static int pxa2xx_fir_is_empty(void *opaque)
1916 {
1917 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1918 return (s->rx_len < 64);
1919 }
1920
1921 static void pxa2xx_fir_rx(void *opaque, const uint8_t *buf, int size)
1922 {
1923 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1924 if (!(s->control[0] & (1 << 4))) /* RXE */
1925 return;
1926
1927 while (size --) {
1928 s->status[1] |= 1 << 4; /* EOF */
1929 if (s->rx_len >= 64) {
1930 s->status[1] |= 1 << 6; /* ROR */
1931 break;
1932 }
1933
1934 if (s->control[2] & (1 << 3)) /* RXP */
1935 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = *(buf ++);
1936 else
1937 s->rx_fifo[(s->rx_start + s->rx_len ++) & 63] = ~*(buf ++);
1938 }
1939
1940 pxa2xx_fir_update(s);
1941 }
1942
1943 static void pxa2xx_fir_event(void *opaque, int event)
1944 {
1945 }
1946
1947 static void pxa2xx_fir_save(QEMUFile *f, void *opaque)
1948 {
1949 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1950 int i;
1951
1952 qemu_put_be32(f, s->enable);
1953
1954 qemu_put_8s(f, &s->control[0]);
1955 qemu_put_8s(f, &s->control[1]);
1956 qemu_put_8s(f, &s->control[2]);
1957 qemu_put_8s(f, &s->status[0]);
1958 qemu_put_8s(f, &s->status[1]);
1959
1960 qemu_put_byte(f, s->rx_len);
1961 for (i = 0; i < s->rx_len; i ++)
1962 qemu_put_byte(f, s->rx_fifo[(s->rx_start + i) & 63]);
1963 }
1964
1965 static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
1966 {
1967 PXA2xxFIrState *s = (PXA2xxFIrState *) opaque;
1968 int i;
1969
1970 s->enable = qemu_get_be32(f);
1971
1972 qemu_get_8s(f, &s->control[0]);
1973 qemu_get_8s(f, &s->control[1]);
1974 qemu_get_8s(f, &s->control[2]);
1975 qemu_get_8s(f, &s->status[0]);
1976 qemu_get_8s(f, &s->status[1]);
1977
1978 s->rx_len = qemu_get_byte(f);
1979 s->rx_start = 0;
1980 for (i = 0; i < s->rx_len; i ++)
1981 s->rx_fifo[i] = qemu_get_byte(f);
1982
1983 return 0;
1984 }
1985
1986 static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
1987 target_phys_addr_t base,
1988 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
1989 CharDriverState *chr)
1990 {
1991 PXA2xxFIrState *s = (PXA2xxFIrState *)
1992 g_malloc0(sizeof(PXA2xxFIrState));
1993
1994 s->irq = irq;
1995 s->rx_dma = rx_dma;
1996 s->tx_dma = tx_dma;
1997 s->chr = chr;
1998
1999 pxa2xx_fir_reset(s);
2000
2001 memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
2002 memory_region_add_subregion(sysmem, base, &s->iomem);
2003
2004 if (chr)
2005 qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
2006 pxa2xx_fir_rx, pxa2xx_fir_event, s);
2007
2008 register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
2009 pxa2xx_fir_load, s);
2010
2011 return s;
2012 }
2013
2014 static void pxa2xx_reset(void *opaque, int line, int level)
2015 {
2016 PXA2xxState *s = (PXA2xxState *) opaque;
2017
2018 if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */
2019 cpu_reset(s->env);
2020 /* TODO: reset peripherals */
2021 }
2022 }
2023
2024 /* Initialise a PXA270 integrated chip (ARM based core). */
2025 PXA2xxState *pxa270_init(MemoryRegion *address_space,
2026 unsigned int sdram_size, const char *revision)
2027 {
2028 PXA2xxState *s;
2029 int i;
2030 DriveInfo *dinfo;
2031 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2032
2033 if (revision && strncmp(revision, "pxa27", 5)) {
2034 fprintf(stderr, "Machine requires a PXA27x processor.\n");
2035 exit(1);
2036 }
2037 if (!revision)
2038 revision = "pxa270";
2039
2040 s->env = cpu_init(revision);
2041 if (!s->env) {
2042 fprintf(stderr, "Unable to find CPU definition\n");
2043 exit(1);
2044 }
2045 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2046
2047 /* SDRAM & Internal Memory Storage */
2048 memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size);
2049 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2050 memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000);
2051 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2052 &s->internal);
2053
2054 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2055
2056 s->dma = pxa27x_dma_init(0x40000000,
2057 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2058
2059 sysbus_create_varargs("pxa27x-timer", 0x40a00000,
2060 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2061 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2062 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2063 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2064 qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11),
2065 NULL);
2066
2067 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121);
2068
2069 dinfo = drive_get(IF_SD, 0, 0);
2070 if (!dinfo) {
2071 fprintf(stderr, "qemu: missing SecureDigital device\n");
2072 exit(1);
2073 }
2074 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2075 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2076 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2077 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2078
2079 for (i = 0; pxa270_serial[i].io_base; i++) {
2080 if (serial_hds[i]) {
2081 serial_mm_init(address_space, pxa270_serial[i].io_base, 2,
2082 qdev_get_gpio_in(s->pic, pxa270_serial[i].irqn),
2083 14857000 / 16, serial_hds[i],
2084 DEVICE_NATIVE_ENDIAN);
2085 } else {
2086 break;
2087 }
2088 }
2089 if (serial_hds[i])
2090 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2091 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2092 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2093 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2094 serial_hds[i]);
2095
2096 s->lcd = pxa2xx_lcdc_init(0x44000000,
2097 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2098
2099 s->cm_base = 0x41300000;
2100 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2101 s->clkcfg = 0x00000009; /* Turbo mode active */
2102 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2103 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2104 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2105
2106 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2107
2108 s->mm_base = 0x48000000;
2109 s->mm_regs[MDMRS >> 2] = 0x00020002;
2110 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2111 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2112 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2113 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2114 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2115
2116 s->pm_base = 0x40f00000;
2117 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2118 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2119 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2120
2121 for (i = 0; pxa27x_ssp[i].io_base; i ++);
2122 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2123 for (i = 0; pxa27x_ssp[i].io_base; i ++) {
2124 DeviceState *dev;
2125 dev = sysbus_create_simple("pxa2xx-ssp", pxa27x_ssp[i].io_base,
2126 qdev_get_gpio_in(s->pic, pxa27x_ssp[i].irqn));
2127 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2128 }
2129
2130 if (usb_enabled) {
2131 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2132 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2133 }
2134
2135 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2136 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2137
2138 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2139 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2140
2141 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2142 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2143 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2144 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2145
2146 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2147 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2148 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2149 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2150
2151 s->kp = pxa27x_keypad_init(0x41500000,
2152 qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
2153
2154 /* GPIO1 resets the processor */
2155 /* The handler can be overridden by board-specific code */
2156 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2157 return s;
2158 }
2159
2160 /* Initialise a PXA255 integrated chip (ARM based core). */
2161 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size)
2162 {
2163 PXA2xxState *s;
2164 int i;
2165 DriveInfo *dinfo;
2166
2167 s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState));
2168
2169 s->env = cpu_init("pxa255");
2170 if (!s->env) {
2171 fprintf(stderr, "Unable to find CPU definition\n");
2172 exit(1);
2173 }
2174 s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
2175
2176 /* SDRAM & Internal Memory Storage */
2177 memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size);
2178 memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram);
2179 memory_region_init_ram(&s->internal, NULL, "pxa255.internal",
2180 PXA2XX_INTERNAL_SIZE);
2181 memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE,
2182 &s->internal);
2183
2184 s->pic = pxa2xx_pic_init(0x40d00000, s->env);
2185
2186 s->dma = pxa255_dma_init(0x40000000,
2187 qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA));
2188
2189 sysbus_create_varargs("pxa25x-timer", 0x40a00000,
2190 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 0),
2191 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 1),
2192 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 2),
2193 qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3),
2194 NULL);
2195
2196 s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85);
2197
2198 dinfo = drive_get(IF_SD, 0, 0);
2199 if (!dinfo) {
2200 fprintf(stderr, "qemu: missing SecureDigital device\n");
2201 exit(1);
2202 }
2203 s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
2204 qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
2205 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
2206 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
2207
2208 for (i = 0; pxa255_serial[i].io_base; i++) {
2209 if (serial_hds[i]) {
2210 serial_mm_init(address_space, pxa255_serial[i].io_base, 2,
2211 qdev_get_gpio_in(s->pic, pxa255_serial[i].irqn),
2212 14745600 / 16, serial_hds[i],
2213 DEVICE_NATIVE_ENDIAN);
2214 } else {
2215 break;
2216 }
2217 }
2218 if (serial_hds[i])
2219 s->fir = pxa2xx_fir_init(address_space, 0x40800000,
2220 qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
2221 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
2222 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
2223 serial_hds[i]);
2224
2225 s->lcd = pxa2xx_lcdc_init(0x44000000,
2226 qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
2227
2228 s->cm_base = 0x41300000;
2229 s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */
2230 s->clkcfg = 0x00000009; /* Turbo mode active */
2231 memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000);
2232 memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem);
2233 vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s);
2234
2235 cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s);
2236
2237 s->mm_base = 0x48000000;
2238 s->mm_regs[MDMRS >> 2] = 0x00020002;
2239 s->mm_regs[MDREFR >> 2] = 0x03ca4000;
2240 s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */
2241 memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000);
2242 memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem);
2243 vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s);
2244
2245 s->pm_base = 0x40f00000;
2246 memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100);
2247 memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem);
2248 vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s);
2249
2250 for (i = 0; pxa255_ssp[i].io_base; i ++);
2251 s->ssp = (SSIBus **)g_malloc0(sizeof(SSIBus *) * i);
2252 for (i = 0; pxa255_ssp[i].io_base; i ++) {
2253 DeviceState *dev;
2254 dev = sysbus_create_simple("pxa2xx-ssp", pxa255_ssp[i].io_base,
2255 qdev_get_gpio_in(s->pic, pxa255_ssp[i].irqn));
2256 s->ssp[i] = (SSIBus *)qdev_get_child_bus(dev, "ssi");
2257 }
2258
2259 if (usb_enabled) {
2260 sysbus_create_simple("sysbus-ohci", 0x4c000000,
2261 qdev_get_gpio_in(s->pic, PXA2XX_PIC_USBH1));
2262 }
2263
2264 s->pcmcia[0] = pxa2xx_pcmcia_init(0x20000000);
2265 s->pcmcia[1] = pxa2xx_pcmcia_init(0x30000000);
2266
2267 sysbus_create_simple("pxa2xx_rtc", 0x40900000,
2268 qdev_get_gpio_in(s->pic, PXA2XX_PIC_RTCALARM));
2269
2270 s->i2c[0] = pxa2xx_i2c_init(0x40301600,
2271 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2C), 0xffff);
2272 s->i2c[1] = pxa2xx_i2c_init(0x40f00100,
2273 qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
2274
2275 s->i2s = pxa2xx_i2s_init(address_space, 0x40400000,
2276 qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
2277 qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
2278 qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
2279
2280 /* GPIO1 resets the processor */
2281 /* The handler can be overridden by board-specific code */
2282 qdev_connect_gpio_out(s->gpio, 1, s->reset);
2283 return s;
2284 }
2285
2286 static void pxa2xx_register_devices(void)
2287 {
2288 i2c_register_slave(&pxa2xx_i2c_slave_info);
2289 sysbus_register_dev("pxa2xx-ssp", sizeof(PXA2xxSSPState), pxa2xx_ssp_init);
2290 sysbus_register_withprop(&pxa2xx_i2c_info);
2291 sysbus_register_withprop(&pxa2xx_rtc_sysbus_info);
2292 }
2293
2294 device_init(pxa2xx_register_devices)
Qemu copy for testing