2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
60 #define QXL_MODE(_x, _y, _b, _o) \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
80 static QXLMode qxl_modes
[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
120 static PCIQXLDevice
*qxl0
;
122 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
123 static void qxl_destroy_primary(PCIQXLDevice
*d
);
124 static void qxl_reset_memslots(PCIQXLDevice
*d
);
125 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
126 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
128 static inline uint32_t msb_mask(uint32_t val
)
133 mask
= ~(val
- 1) & val
;
135 } while (mask
< val
);
140 static ram_addr_t
qxl_rom_size(void)
142 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
143 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
144 rom_size
= msb_mask(rom_size
* 2 - 1);
148 static void init_qxl_rom(PCIQXLDevice
*d
)
150 QXLRom
*rom
= qemu_get_ram_ptr(d
->rom_offset
);
151 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
152 uint32_t ram_header_size
;
153 uint32_t surface0_area_size
;
155 uint32_t fb
, maxfb
= 0;
158 memset(rom
, 0, d
->rom_size
);
160 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
161 rom
->id
= cpu_to_le32(d
->id
);
162 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
163 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
165 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
166 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
167 rom
->slots_start
= 1;
168 rom
->slots_end
= NUM_MEMSLOTS
- 1;
169 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
171 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
172 for (i
= 0; i
< modes
->n_modes
; i
++) {
173 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
177 modes
->modes
[i
].id
= cpu_to_le32(i
);
178 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
179 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
180 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
181 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
182 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
183 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
184 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
186 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
187 maxfb
= VGA_RAM_SIZE
;
189 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
190 surface0_area_size
= ALIGN(maxfb
, 4096);
191 num_pages
= d
->vga
.vram_size
;
192 num_pages
-= ram_header_size
;
193 num_pages
-= surface0_area_size
;
194 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
196 rom
->draw_area_offset
= cpu_to_le32(0);
197 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
198 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
199 rom
->num_pages
= cpu_to_le32(num_pages
);
200 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
202 d
->shadow_rom
= *rom
;
207 static void init_qxl_ram(PCIQXLDevice
*d
)
212 buf
= d
->vga
.vram_ptr
;
213 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
214 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
215 d
->ram
->int_pending
= cpu_to_le32(0);
216 d
->ram
->int_mask
= cpu_to_le32(0);
217 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
218 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
219 SPICE_RING_INIT(&d
->ram
->release_ring
);
220 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
222 qxl_ring_set_dirty(d
);
225 /* can be called from spice server thread context */
226 static void qxl_set_dirty(ram_addr_t addr
, ram_addr_t end
)
229 cpu_physical_memory_set_dirty(addr
);
230 addr
+= TARGET_PAGE_SIZE
;
234 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
236 ram_addr_t addr
= qxl
->rom_offset
;
237 qxl_set_dirty(addr
, addr
+ qxl
->rom_size
);
240 /* called from spice server thread context only */
241 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
243 ram_addr_t addr
= qxl
->vga
.vram_offset
;
244 void *base
= qxl
->vga
.vram_ptr
;
248 offset
&= ~(TARGET_PAGE_SIZE
-1);
249 assert(offset
< qxl
->vga
.vram_size
);
250 qxl_set_dirty(addr
+ offset
, addr
+ offset
+ TARGET_PAGE_SIZE
);
253 /* can be called from spice server thread context */
254 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
256 ram_addr_t addr
= qxl
->vga
.vram_offset
+ qxl
->shadow_rom
.ram_header_offset
;
257 ram_addr_t end
= qxl
->vga
.vram_offset
+ qxl
->vga
.vram_size
;
258 qxl_set_dirty(addr
, end
);
262 * keep track of some command state, for savevm/loadvm.
263 * called from spice server thread context only
265 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
267 switch (le32_to_cpu(ext
->cmd
.type
)) {
268 case QXL_CMD_SURFACE
:
270 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
271 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
272 PANIC_ON(id
>= NUM_SURFACES
);
273 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
274 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
275 qxl
->guest_surfaces
.count
++;
276 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
277 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
279 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
280 qxl
->guest_surfaces
.cmds
[id
] = 0;
281 qxl
->guest_surfaces
.count
--;
287 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
288 if (cmd
->type
== QXL_CURSOR_SET
) {
289 qxl
->guest_cursor
= ext
->cmd
.data
;
296 /* spice display interface callbacks */
298 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
300 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
302 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
303 qxl
->ssd
.worker
= qxl_worker
;
306 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
308 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
310 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
311 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
312 qxl
->rom
->compression_level
= cpu_to_le32(level
);
313 qxl_rom_set_dirty(qxl
);
316 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
318 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
320 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
321 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
322 qxl_rom_set_dirty(qxl
);
325 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
327 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
329 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
330 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
331 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
332 info
->num_memslots
= NUM_MEMSLOTS
;
333 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
334 info
->internal_groupslot_id
= 0;
335 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
336 info
->n_surfaces
= NUM_SURFACES
;
339 static const char *qxl_mode_to_string(int mode
)
342 case QXL_MODE_COMPAT
:
344 case QXL_MODE_NATIVE
:
346 case QXL_MODE_UNDEFINED
:
354 /* called from spice server thread context only */
355 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
357 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
358 SimpleSpiceUpdate
*update
;
359 QXLCommandRing
*ring
;
365 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
367 qemu_mutex_lock(&qxl
->ssd
.lock
);
368 if (qxl
->ssd
.update
!= NULL
) {
369 update
= qxl
->ssd
.update
;
370 qxl
->ssd
.update
= NULL
;
374 qemu_mutex_unlock(&qxl
->ssd
.lock
);
376 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
377 qxl_log_command(qxl
, "vga", ext
);
380 case QXL_MODE_COMPAT
:
381 case QXL_MODE_NATIVE
:
382 case QXL_MODE_UNDEFINED
:
383 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
384 ring
= &qxl
->ram
->cmd_ring
;
385 if (SPICE_RING_IS_EMPTY(ring
)) {
388 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
389 SPICE_RING_CONS_ITEM(ring
, cmd
);
391 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
392 ext
->flags
= qxl
->cmdflags
;
393 SPICE_RING_POP(ring
, notify
);
394 qxl_ring_set_dirty(qxl
);
396 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
398 qxl
->guest_primary
.commands
++;
399 qxl_track_command(qxl
, ext
);
400 qxl_log_command(qxl
, "cmd", ext
);
407 /* called from spice server thread context only */
408 static int interface_req_cmd_notification(QXLInstance
*sin
)
410 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
414 case QXL_MODE_COMPAT
:
415 case QXL_MODE_NATIVE
:
416 case QXL_MODE_UNDEFINED
:
417 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
418 qxl_ring_set_dirty(qxl
);
427 /* called from spice server thread context only */
428 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
430 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
434 #define QXL_FREE_BUNCH_SIZE 32
436 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
437 /* ring full -- can't push */
440 if (!flush
&& d
->oom_running
) {
441 /* collect everything from oom handler before pushing */
444 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
445 /* collect a bit more before pushing */
449 SPICE_RING_PUSH(ring
, notify
);
450 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
451 d
->num_free_res
, notify
? "yes" : "no",
452 ring
->prod
- ring
->cons
, ring
->num_items
,
453 ring
->prod
, ring
->cons
);
455 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
457 SPICE_RING_PROD_ITEM(ring
, item
);
460 d
->last_release
= NULL
;
461 qxl_ring_set_dirty(d
);
464 /* called from spice server thread context only */
465 static void interface_release_resource(QXLInstance
*sin
,
466 struct QXLReleaseInfoExt ext
)
468 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
469 QXLReleaseRing
*ring
;
472 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
473 /* host group -> vga mode update request */
474 qemu_spice_destroy_update(&qxl
->ssd
, (void*)ext
.info
->id
);
479 * ext->info points into guest-visible memory
480 * pci bar 0, $command.release_info
482 ring
= &qxl
->ram
->release_ring
;
483 SPICE_RING_PROD_ITEM(ring
, item
);
485 /* stick head into the ring */
488 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
490 qxl_ring_set_dirty(qxl
);
492 /* append item to the list */
493 qxl
->last_release
->next
= ext
.info
->id
;
494 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
496 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
498 qxl
->last_release
= ext
.info
;
500 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
501 qxl_push_free_res(qxl
, 0);
504 /* called from spice server thread context only */
505 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
507 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
513 case QXL_MODE_COMPAT
:
514 case QXL_MODE_NATIVE
:
515 case QXL_MODE_UNDEFINED
:
516 ring
= &qxl
->ram
->cursor_ring
;
517 if (SPICE_RING_IS_EMPTY(ring
)) {
520 SPICE_RING_CONS_ITEM(ring
, cmd
);
522 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
523 ext
->flags
= qxl
->cmdflags
;
524 SPICE_RING_POP(ring
, notify
);
525 qxl_ring_set_dirty(qxl
);
527 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
529 qxl
->guest_primary
.commands
++;
530 qxl_track_command(qxl
, ext
);
531 qxl_log_command(qxl
, "csr", ext
);
533 qxl_render_cursor(qxl
, ext
);
541 /* called from spice server thread context only */
542 static int interface_req_cursor_notification(QXLInstance
*sin
)
544 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
548 case QXL_MODE_COMPAT
:
549 case QXL_MODE_NATIVE
:
550 case QXL_MODE_UNDEFINED
:
551 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
552 qxl_ring_set_dirty(qxl
);
561 /* called from spice server thread context */
562 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
564 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
568 /* called from spice server thread context only */
569 static int interface_flush_resources(QXLInstance
*sin
)
571 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
574 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
575 ret
= qxl
->num_free_res
;
577 qxl_push_free_res(qxl
, 1);
582 static const QXLInterface qxl_interface
= {
583 .base
.type
= SPICE_INTERFACE_QXL
,
584 .base
.description
= "qxl gpu",
585 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
586 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
588 .attache_worker
= interface_attach_worker
,
589 .set_compression_level
= interface_set_compression_level
,
590 .set_mm_time
= interface_set_mm_time
,
591 .get_init_info
= interface_get_init_info
,
593 /* the callbacks below are called from spice server thread context */
594 .get_command
= interface_get_command
,
595 .req_cmd_notification
= interface_req_cmd_notification
,
596 .release_resource
= interface_release_resource
,
597 .get_cursor_command
= interface_get_cursor_command
,
598 .req_cursor_notification
= interface_req_cursor_notification
,
599 .notify_update
= interface_notify_update
,
600 .flush_resources
= interface_flush_resources
,
603 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
605 if (d
->mode
== QXL_MODE_VGA
) {
608 dprint(d
, 1, "%s\n", __FUNCTION__
);
609 qemu_spice_create_host_primary(&d
->ssd
);
610 d
->mode
= QXL_MODE_VGA
;
611 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
614 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
616 if (d
->mode
!= QXL_MODE_VGA
) {
619 dprint(d
, 1, "%s\n", __FUNCTION__
);
620 qxl_destroy_primary(d
);
623 static void qxl_set_irq(PCIQXLDevice
*d
)
625 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
626 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
627 int level
= !!(pending
& mask
);
628 qemu_set_irq(d
->pci
.irq
[0], level
);
629 qxl_ring_set_dirty(d
);
632 static void qxl_write_config(PCIDevice
*d
, uint32_t address
,
633 uint32_t val
, int len
)
635 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, d
);
636 VGACommonState
*vga
= &qxl
->vga
;
638 vga_dirty_log_stop(vga
);
639 pci_default_write_config(d
, address
, val
, len
);
640 if (vga
->map_addr
&& qxl
->pci
.io_regions
[0].addr
== -1) {
643 vga_dirty_log_start(vga
);
646 static void qxl_check_state(PCIQXLDevice
*d
)
648 QXLRam
*ram
= d
->ram
;
650 assert(SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
651 assert(SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
654 static void qxl_reset_state(PCIQXLDevice
*d
)
656 QXLRam
*ram
= d
->ram
;
657 QXLRom
*rom
= d
->rom
;
659 assert(SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
660 assert(SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
661 d
->shadow_rom
.update_id
= cpu_to_le32(0);
662 *rom
= d
->shadow_rom
;
663 qxl_rom_set_dirty(d
);
666 d
->last_release
= NULL
;
667 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
670 static void qxl_soft_reset(PCIQXLDevice
*d
)
672 dprint(d
, 1, "%s:\n", __FUNCTION__
);
676 qxl_enter_vga_mode(d
);
678 d
->mode
= QXL_MODE_UNDEFINED
;
682 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
684 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
685 loadvm
? " (loadvm)" : "");
687 d
->ssd
.worker
->reset_cursor(d
->ssd
.worker
);
688 d
->ssd
.worker
->reset_image_cache(d
->ssd
.worker
);
689 qxl_reset_surfaces(d
);
690 qxl_reset_memslots(d
);
692 /* pre loadvm reset must not touch QXLRam. This lives in
693 * device memory, is migrated together with RAM and thus
694 * already loaded at this point */
698 qemu_spice_create_host_memslot(&d
->ssd
);
701 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
704 static void qxl_reset_handler(DeviceState
*dev
)
706 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
707 qxl_hard_reset(d
, 0);
710 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
712 VGACommonState
*vga
= opaque
;
713 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
715 if (qxl
->mode
!= QXL_MODE_VGA
) {
716 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
717 qxl_destroy_primary(qxl
);
720 vga_ioport_write(opaque
, addr
, val
);
723 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
)
725 static const int regions
[] = {
727 QXL_VRAM_RANGE_INDEX
,
729 uint64_t guest_start
;
735 QXLDevMemSlot memslot
;
738 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
739 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
741 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
742 __FUNCTION__
, slot_id
,
743 guest_start
, guest_end
);
745 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
746 PANIC_ON(guest_start
> guest_end
);
748 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
749 pci_region
= regions
[i
];
750 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
751 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
753 if (pci_start
== -1) {
756 /* start address in range ? */
757 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
760 /* end address in range ? */
761 if (guest_end
> pci_end
) {
767 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
769 switch (pci_region
) {
770 case QXL_RAM_RANGE_INDEX
:
771 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vga
.vram_offset
);
773 case QXL_VRAM_RANGE_INDEX
:
774 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vram_offset
);
777 /* should not happen */
781 memslot
.slot_id
= slot_id
;
782 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
783 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
784 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
785 memslot
.addr_delta
= memslot
.virt_start
- delta
;
786 memslot
.generation
= d
->rom
->slot_generation
= 0;
787 qxl_rom_set_dirty(d
);
789 dprint(d
, 1, "%s: slot %d: host virt 0x%" PRIx64
" - 0x%" PRIx64
"\n",
790 __FUNCTION__
, memslot
.slot_id
,
791 memslot
.virt_start
, memslot
.virt_end
);
793 d
->ssd
.worker
->add_memslot(d
->ssd
.worker
, &memslot
);
794 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
795 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
796 d
->guest_slots
[slot_id
].delta
= delta
;
797 d
->guest_slots
[slot_id
].active
= 1;
800 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
802 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
803 d
->ssd
.worker
->del_memslot(d
->ssd
.worker
, MEMSLOT_GROUP_HOST
, slot_id
);
804 d
->guest_slots
[slot_id
].active
= 0;
807 static void qxl_reset_memslots(PCIQXLDevice
*d
)
809 dprint(d
, 1, "%s:\n", __FUNCTION__
);
810 d
->ssd
.worker
->reset_memslots(d
->ssd
.worker
);
811 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
814 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
816 dprint(d
, 1, "%s:\n", __FUNCTION__
);
817 d
->mode
= QXL_MODE_UNDEFINED
;
818 d
->ssd
.worker
->destroy_surfaces(d
->ssd
.worker
);
819 memset(&d
->guest_surfaces
.cmds
, 0, sizeof(d
->guest_surfaces
.cmds
));
822 /* called from spice server thread context only */
823 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
825 uint64_t phys
= le64_to_cpu(pqxl
);
826 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
827 uint64_t offset
= phys
& 0xffffffffffff;
830 case MEMSLOT_GROUP_HOST
:
831 return (void*)offset
;
832 case MEMSLOT_GROUP_GUEST
:
833 PANIC_ON(slot
> NUM_MEMSLOTS
);
834 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
835 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
836 offset
-= qxl
->guest_slots
[slot
].delta
;
837 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
838 return qxl
->guest_slots
[slot
].ptr
+ offset
;
844 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
)
846 QXLDevSurfaceCreate surface
;
847 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
849 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
850 qxl_exit_vga_mode(qxl
);
852 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
853 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
855 surface
.format
= le32_to_cpu(sc
->format
);
856 surface
.height
= le32_to_cpu(sc
->height
);
857 surface
.mem
= le64_to_cpu(sc
->mem
);
858 surface
.position
= le32_to_cpu(sc
->position
);
859 surface
.stride
= le32_to_cpu(sc
->stride
);
860 surface
.width
= le32_to_cpu(sc
->width
);
861 surface
.type
= le32_to_cpu(sc
->type
);
862 surface
.flags
= le32_to_cpu(sc
->flags
);
864 surface
.mouse_mode
= true;
865 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
867 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
870 qxl
->mode
= QXL_MODE_NATIVE
;
872 qxl
->ssd
.worker
->create_primary_surface(qxl
->ssd
.worker
, 0, &surface
);
874 /* for local rendering */
875 qxl_render_resize(qxl
);
878 static void qxl_destroy_primary(PCIQXLDevice
*d
)
880 if (d
->mode
== QXL_MODE_UNDEFINED
) {
884 dprint(d
, 1, "%s\n", __FUNCTION__
);
886 d
->mode
= QXL_MODE_UNDEFINED
;
887 d
->ssd
.worker
->destroy_primary_surface(d
->ssd
.worker
, 0);
890 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
892 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
893 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
894 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
895 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
900 QXLSurfaceCreate surface
= {
901 .width
= mode
->x_res
,
902 .height
= mode
->y_res
,
903 .stride
= -mode
->x_res
* 4,
904 .format
= SPICE_SURFACE_FMT_32_xRGB
,
905 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
907 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
910 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__
,
911 modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
913 qxl_hard_reset(d
, 0);
916 d
->guest_slots
[0].slot
= slot
;
917 qxl_add_memslot(d
, 0, devmem
);
919 d
->guest_primary
.surface
= surface
;
920 qxl_create_guest_primary(d
, 0);
922 d
->mode
= QXL_MODE_COMPAT
;
923 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
924 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
925 if (mode
->bits
== 16) {
926 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
929 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
930 d
->rom
->mode
= cpu_to_le32(modenr
);
931 qxl_rom_set_dirty(d
);
934 static void ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
936 PCIQXLDevice
*d
= opaque
;
937 uint32_t io_port
= addr
- d
->io_base
;
941 case QXL_IO_SET_MODE
:
942 case QXL_IO_MEMSLOT_ADD
:
943 case QXL_IO_MEMSLOT_DEL
:
944 case QXL_IO_CREATE_PRIMARY
:
947 if (d
->mode
== QXL_MODE_NATIVE
|| d
->mode
== QXL_MODE_COMPAT
)
949 dprint(d
, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__
, io_port
);
954 case QXL_IO_UPDATE_AREA
:
956 QXLRect update
= d
->ram
->update_area
;
957 d
->ssd
.worker
->update_area(d
->ssd
.worker
, d
->ram
->update_surface
,
958 &update
, NULL
, 0, 0);
961 case QXL_IO_NOTIFY_CMD
:
962 d
->ssd
.worker
->wakeup(d
->ssd
.worker
);
964 case QXL_IO_NOTIFY_CURSOR
:
965 d
->ssd
.worker
->wakeup(d
->ssd
.worker
);
967 case QXL_IO_UPDATE_IRQ
:
970 case QXL_IO_NOTIFY_OOM
:
971 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
975 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
979 d
->ssd
.worker
->oom(d
->ssd
.worker
);
982 case QXL_IO_SET_MODE
:
983 dprint(d
, 1, "QXL_SET_MODE %d\n", val
);
984 qxl_set_mode(d
, val
, 0);
988 fprintf(stderr
, "qxl/guest: %s", d
->ram
->log_buf
);
992 dprint(d
, 1, "QXL_IO_RESET\n");
993 qxl_hard_reset(d
, 0);
995 case QXL_IO_MEMSLOT_ADD
:
996 PANIC_ON(val
>= NUM_MEMSLOTS
);
997 PANIC_ON(d
->guest_slots
[val
].active
);
998 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
999 qxl_add_memslot(d
, val
, 0);
1001 case QXL_IO_MEMSLOT_DEL
:
1002 qxl_del_memslot(d
, val
);
1004 case QXL_IO_CREATE_PRIMARY
:
1006 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY\n");
1007 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1008 qxl_create_guest_primary(d
, 0);
1010 case QXL_IO_DESTROY_PRIMARY
:
1012 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (%s)\n", qxl_mode_to_string(d
->mode
));
1013 qxl_destroy_primary(d
);
1015 case QXL_IO_DESTROY_SURFACE_WAIT
:
1016 d
->ssd
.worker
->destroy_surface_wait(d
->ssd
.worker
, val
);
1018 case QXL_IO_DESTROY_ALL_SURFACES
:
1019 d
->ssd
.worker
->destroy_surfaces(d
->ssd
.worker
);
1022 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1027 static uint32_t ioport_read(void *opaque
, uint32_t addr
)
1029 PCIQXLDevice
*d
= opaque
;
1031 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1035 static void qxl_map(PCIDevice
*pci
, int region_num
,
1036 pcibus_t addr
, pcibus_t size
, int type
)
1038 static const char *names
[] = {
1039 [ QXL_IO_RANGE_INDEX
] = "ioports",
1040 [ QXL_RAM_RANGE_INDEX
] = "devram",
1041 [ QXL_ROM_RANGE_INDEX
] = "rom",
1042 [ QXL_VRAM_RANGE_INDEX
] = "vram",
1044 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, pci
);
1046 dprint(qxl
, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__
,
1047 region_num
, names
[region_num
], addr
, size
);
1049 switch (region_num
) {
1050 case QXL_IO_RANGE_INDEX
:
1051 register_ioport_write(addr
, size
, 1, ioport_write
, pci
);
1052 register_ioport_read(addr
, size
, 1, ioport_read
, pci
);
1053 qxl
->io_base
= addr
;
1055 case QXL_RAM_RANGE_INDEX
:
1056 cpu_register_physical_memory(addr
, size
, qxl
->vga
.vram_offset
| IO_MEM_RAM
);
1057 qxl
->vga
.map_addr
= addr
;
1058 qxl
->vga
.map_end
= addr
+ size
;
1060 vga_dirty_log_start(&qxl
->vga
);
1063 case QXL_ROM_RANGE_INDEX
:
1064 cpu_register_physical_memory(addr
, size
, qxl
->rom_offset
| IO_MEM_ROM
);
1066 case QXL_VRAM_RANGE_INDEX
:
1067 cpu_register_physical_memory(addr
, size
, qxl
->vram_offset
| IO_MEM_RAM
);
1072 static void pipe_read(void *opaque
)
1074 PCIQXLDevice
*d
= opaque
;
1079 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1080 } while (len
== sizeof(dummy
));
1084 /* called from spice server thread context only */
1085 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1087 uint32_t old_pending
;
1088 uint32_t le_events
= cpu_to_le32(events
);
1090 assert(d
->ssd
.running
);
1091 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1092 if ((old_pending
& le_events
) == le_events
) {
1095 if (pthread_self() == d
->main
) {
1098 if (write(d
->pipe
[1], d
, 1) != 1) {
1099 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1104 static void init_pipe_signaling(PCIQXLDevice
*d
)
1106 if (pipe(d
->pipe
) < 0) {
1107 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1110 #ifdef CONFIG_IOTHREAD
1111 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1113 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
/* | O_ASYNC */);
1115 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1116 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1118 d
->main
= pthread_self();
1119 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1122 /* graphics console */
1124 static void qxl_hw_update(void *opaque
)
1126 PCIQXLDevice
*qxl
= opaque
;
1127 VGACommonState
*vga
= &qxl
->vga
;
1129 switch (qxl
->mode
) {
1133 case QXL_MODE_COMPAT
:
1134 case QXL_MODE_NATIVE
:
1135 qxl_render_update(qxl
);
1142 static void qxl_hw_invalidate(void *opaque
)
1144 PCIQXLDevice
*qxl
= opaque
;
1145 VGACommonState
*vga
= &qxl
->vga
;
1147 vga
->invalidate(vga
);
1150 static void qxl_hw_screen_dump(void *opaque
, const char *filename
)
1152 PCIQXLDevice
*qxl
= opaque
;
1153 VGACommonState
*vga
= &qxl
->vga
;
1155 switch (qxl
->mode
) {
1156 case QXL_MODE_COMPAT
:
1157 case QXL_MODE_NATIVE
:
1158 qxl_render_update(qxl
);
1159 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1162 vga
->screen_dump(vga
, filename
);
1169 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1171 PCIQXLDevice
*qxl
= opaque
;
1172 VGACommonState
*vga
= &qxl
->vga
;
1174 if (qxl
->mode
== QXL_MODE_VGA
) {
1175 vga
->text_update(vga
, chardata
);
1180 static void qxl_vm_change_state_handler(void *opaque
, int running
, int reason
)
1182 PCIQXLDevice
*qxl
= opaque
;
1183 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, reason
);
1185 if (!running
&& qxl
->mode
== QXL_MODE_NATIVE
) {
1186 /* dirty all vram (which holds surfaces) to make sure it is saved */
1187 /* FIXME #1: should go out during "live" stage */
1188 /* FIXME #2: we only need to save the areas which are actually used */
1189 ram_addr_t addr
= qxl
->vram_offset
;
1190 qxl_set_dirty(addr
, addr
+ qxl
->vram_size
);
1194 /* display change listener */
1196 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1198 if (qxl0
->mode
== QXL_MODE_VGA
) {
1199 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1203 static void display_resize(struct DisplayState
*ds
)
1205 if (qxl0
->mode
== QXL_MODE_VGA
) {
1206 qemu_spice_display_resize(&qxl0
->ssd
);
1210 static void display_refresh(struct DisplayState
*ds
)
1212 if (qxl0
->mode
== QXL_MODE_VGA
) {
1213 qemu_spice_display_refresh(&qxl0
->ssd
);
1217 static DisplayChangeListener display_listener
= {
1218 .dpy_update
= display_update
,
1219 .dpy_resize
= display_resize
,
1220 .dpy_refresh
= display_refresh
,
1223 static int qxl_init_common(PCIQXLDevice
*qxl
)
1225 uint8_t* config
= qxl
->pci
.config
;
1226 uint32_t pci_device_rev
;
1229 qxl
->mode
= QXL_MODE_UNDEFINED
;
1230 qxl
->generation
= 1;
1231 qxl
->num_memslots
= NUM_MEMSLOTS
;
1232 qxl
->num_surfaces
= NUM_SURFACES
;
1234 switch (qxl
->revision
) {
1235 case 1: /* spice 0.4 -- qxl-1 */
1236 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1238 case 2: /* spice 0.6 -- qxl-2 */
1240 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1244 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1245 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1247 qxl
->rom_size
= qxl_rom_size();
1248 qxl
->rom_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vrom", qxl
->rom_size
);
1252 if (qxl
->vram_size
< 16 * 1024 * 1024) {
1253 qxl
->vram_size
= 16 * 1024 * 1024;
1255 if (qxl
->revision
== 1) {
1256 qxl
->vram_size
= 4096;
1258 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1259 qxl
->vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vram", qxl
->vram_size
);
1261 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1262 if (qxl
->revision
== 1) {
1266 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1267 io_size
, PCI_BASE_ADDRESS_SPACE_IO
, qxl_map
);
1269 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1270 qxl
->rom_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1273 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1274 qxl
->vga
.vram_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1277 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
, qxl
->vram_size
,
1278 PCI_BASE_ADDRESS_SPACE_MEMORY
, qxl_map
);
1280 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1281 qxl
->ssd
.qxl
.id
= qxl
->id
;
1282 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1283 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1285 init_pipe_signaling(qxl
);
1286 qxl_reset_state(qxl
);
1291 static int qxl_init_primary(PCIDevice
*dev
)
1293 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1294 VGACommonState
*vga
= &qxl
->vga
;
1295 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1299 if (ram_size
< 32 * 1024 * 1024) {
1300 ram_size
= 32 * 1024 * 1024;
1302 vga_common_init(vga
, ram_size
);
1304 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write
, vga
);
1305 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write
, vga
);
1306 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write
, vga
);
1307 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write
, vga
);
1308 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write
, vga
);
1310 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1311 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1312 qxl
->ssd
.ds
= vga
->ds
;
1313 qemu_mutex_init(&qxl
->ssd
.lock
);
1314 qxl
->ssd
.mouse_x
= -1;
1315 qxl
->ssd
.mouse_y
= -1;
1316 qxl
->ssd
.bufsize
= (16 * 1024 * 1024);
1317 qxl
->ssd
.buf
= qemu_malloc(qxl
->ssd
.bufsize
);
1320 register_displaychangelistener(vga
->ds
, &display_listener
);
1322 return qxl_init_common(qxl
);
1325 static int qxl_init_secondary(PCIDevice
*dev
)
1327 static int device_id
= 1;
1328 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1329 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1331 qxl
->id
= device_id
++;
1333 if (ram_size
< 16 * 1024 * 1024) {
1334 ram_size
= 16 * 1024 * 1024;
1336 qxl
->vga
.vram_size
= ram_size
;
1337 qxl
->vga
.vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vgavram",
1338 qxl
->vga
.vram_size
);
1339 qxl
->vga
.vram_ptr
= qemu_get_ram_ptr(qxl
->vga
.vram_offset
);
1341 return qxl_init_common(qxl
);
1344 static void qxl_pre_save(void *opaque
)
1346 PCIQXLDevice
* d
= opaque
;
1347 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1349 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1350 if (d
->last_release
== NULL
) {
1351 d
->last_release_offset
= 0;
1353 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1355 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1358 static int qxl_pre_load(void *opaque
)
1360 PCIQXLDevice
* d
= opaque
;
1362 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1363 qxl_hard_reset(d
, 1);
1364 qxl_exit_vga_mode(d
);
1365 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1369 static int qxl_post_load(void *opaque
, int version
)
1371 PCIQXLDevice
* d
= opaque
;
1372 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1373 QXLCommandExt
*cmds
;
1374 int in
, out
, i
, newmode
;
1376 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1378 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1379 if (d
->last_release_offset
== 0) {
1380 d
->last_release
= NULL
;
1382 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1385 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1387 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1388 qxl_mode_to_string(d
->mode
));
1390 d
->mode
= QXL_MODE_UNDEFINED
;
1392 case QXL_MODE_UNDEFINED
:
1395 qxl_enter_vga_mode(d
);
1397 case QXL_MODE_NATIVE
:
1398 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1399 if (!d
->guest_slots
[i
].active
) {
1402 qxl_add_memslot(d
, i
, 0);
1404 qxl_create_guest_primary(d
, 1);
1406 /* replay surface-create and cursor-set commands */
1407 cmds
= qemu_mallocz(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1408 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1409 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1412 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1413 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1414 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1417 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1418 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1419 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1421 d
->ssd
.worker
->loadvm_commands(d
->ssd
.worker
, cmds
, out
);
1425 case QXL_MODE_COMPAT
:
1426 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1429 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1434 #define QXL_SAVE_VERSION 21
1436 static VMStateDescription qxl_memslot
= {
1437 .name
= "qxl-memslot",
1438 .version_id
= QXL_SAVE_VERSION
,
1439 .minimum_version_id
= QXL_SAVE_VERSION
,
1440 .fields
= (VMStateField
[]) {
1441 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1442 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1443 VMSTATE_UINT32(active
, struct guest_slots
),
1444 VMSTATE_END_OF_LIST()
1448 static VMStateDescription qxl_surface
= {
1449 .name
= "qxl-surface",
1450 .version_id
= QXL_SAVE_VERSION
,
1451 .minimum_version_id
= QXL_SAVE_VERSION
,
1452 .fields
= (VMStateField
[]) {
1453 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1454 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1455 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1456 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1457 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1458 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1459 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1460 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1461 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1462 VMSTATE_END_OF_LIST()
1466 static VMStateDescription qxl_vmstate
= {
1468 .version_id
= QXL_SAVE_VERSION
,
1469 .minimum_version_id
= QXL_SAVE_VERSION
,
1470 .pre_save
= qxl_pre_save
,
1471 .pre_load
= qxl_pre_load
,
1472 .post_load
= qxl_post_load
,
1473 .fields
= (VMStateField
[]) {
1474 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1475 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1476 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1477 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1478 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1479 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1480 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1481 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1482 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1483 qxl_memslot
, struct guest_slots
),
1484 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1485 qxl_surface
, QXLSurfaceCreate
),
1486 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1487 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1488 vmstate_info_uint64
, uint64_t),
1489 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1490 VMSTATE_END_OF_LIST()
1494 static PCIDeviceInfo qxl_info_primary
= {
1495 .qdev
.name
= "qxl-vga",
1496 .qdev
.desc
= "Spice QXL GPU (primary, vga compatible)",
1497 .qdev
.size
= sizeof(PCIQXLDevice
),
1498 .qdev
.reset
= qxl_reset_handler
,
1499 .qdev
.vmsd
= &qxl_vmstate
,
1501 .init
= qxl_init_primary
,
1502 .config_write
= qxl_write_config
,
1503 .romfile
= "vgabios-qxl.bin",
1504 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1505 .device_id
= QXL_DEVICE_ID_STABLE
,
1506 .class_id
= PCI_CLASS_DISPLAY_VGA
,
1507 .qdev
.props
= (Property
[]) {
1508 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1509 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1510 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1511 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1512 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1513 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1514 DEFINE_PROP_END_OF_LIST(),
1518 static PCIDeviceInfo qxl_info_secondary
= {
1520 .qdev
.desc
= "Spice QXL GPU (secondary)",
1521 .qdev
.size
= sizeof(PCIQXLDevice
),
1522 .qdev
.reset
= qxl_reset_handler
,
1523 .qdev
.vmsd
= &qxl_vmstate
,
1524 .init
= qxl_init_secondary
,
1525 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1526 .device_id
= QXL_DEVICE_ID_STABLE
,
1527 .class_id
= PCI_CLASS_DISPLAY_OTHER
,
1528 .qdev
.props
= (Property
[]) {
1529 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1530 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1531 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1532 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1533 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1534 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1535 DEFINE_PROP_END_OF_LIST(),
1539 static void qxl_register(void)
1541 pci_qdev_register(&qxl_info_primary
);
1542 pci_qdev_register(&qxl_info_secondary
);
1545 device_init(qxl_register
);