2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
60 #define QXL_MODE(_x, _y, _b, _o) \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
80 static QXLMode qxl_modes
[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
120 static PCIQXLDevice
*qxl0
;
122 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
123 static void qxl_destroy_primary(PCIQXLDevice
*d
);
124 static void qxl_reset_memslots(PCIQXLDevice
*d
);
125 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
126 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
129 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
130 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
131 uint32_t num_dirty_rects
,
132 uint32_t clear_dirty_region
)
134 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
, dirty_rects
,
135 num_dirty_rects
, clear_dirty_region
);
138 void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
)
140 qemu_mutex_lock(&qxl
->track_lock
);
141 PANIC_ON(id
>= NUM_SURFACES
);
142 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
143 qxl
->guest_surfaces
.cmds
[id
] = 0;
144 qxl
->guest_surfaces
.count
--;
145 qemu_mutex_unlock(&qxl
->track_lock
);
148 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
151 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
154 void qxl_spice_oom(PCIQXLDevice
*qxl
)
156 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
159 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
161 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
164 void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
)
166 qemu_mutex_lock(&qxl
->track_lock
);
167 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
168 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
169 qxl
->guest_surfaces
.count
= 0;
170 qemu_mutex_unlock(&qxl
->track_lock
);
173 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
175 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
178 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
180 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
184 static inline uint32_t msb_mask(uint32_t val
)
189 mask
= ~(val
- 1) & val
;
191 } while (mask
< val
);
196 static ram_addr_t
qxl_rom_size(void)
198 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
199 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
200 rom_size
= msb_mask(rom_size
* 2 - 1);
204 static void init_qxl_rom(PCIQXLDevice
*d
)
206 QXLRom
*rom
= qemu_get_ram_ptr(d
->rom_offset
);
207 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
208 uint32_t ram_header_size
;
209 uint32_t surface0_area_size
;
211 uint32_t fb
, maxfb
= 0;
214 memset(rom
, 0, d
->rom_size
);
216 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
217 rom
->id
= cpu_to_le32(d
->id
);
218 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
219 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
221 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
222 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
223 rom
->slots_start
= 1;
224 rom
->slots_end
= NUM_MEMSLOTS
- 1;
225 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
227 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
228 for (i
= 0; i
< modes
->n_modes
; i
++) {
229 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
233 modes
->modes
[i
].id
= cpu_to_le32(i
);
234 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
235 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
236 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
237 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
238 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
239 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
240 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
242 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
243 maxfb
= VGA_RAM_SIZE
;
245 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
246 surface0_area_size
= ALIGN(maxfb
, 4096);
247 num_pages
= d
->vga
.vram_size
;
248 num_pages
-= ram_header_size
;
249 num_pages
-= surface0_area_size
;
250 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
252 rom
->draw_area_offset
= cpu_to_le32(0);
253 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
254 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
255 rom
->num_pages
= cpu_to_le32(num_pages
);
256 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
258 d
->shadow_rom
= *rom
;
263 static void init_qxl_ram(PCIQXLDevice
*d
)
268 buf
= d
->vga
.vram_ptr
;
269 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
270 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
271 d
->ram
->int_pending
= cpu_to_le32(0);
272 d
->ram
->int_mask
= cpu_to_le32(0);
273 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
274 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
275 SPICE_RING_INIT(&d
->ram
->release_ring
);
276 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
278 qxl_ring_set_dirty(d
);
281 /* can be called from spice server thread context */
282 static void qxl_set_dirty(ram_addr_t addr
, ram_addr_t end
)
285 cpu_physical_memory_set_dirty(addr
);
286 addr
+= TARGET_PAGE_SIZE
;
290 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
292 ram_addr_t addr
= qxl
->rom_offset
;
293 qxl_set_dirty(addr
, addr
+ qxl
->rom_size
);
296 /* called from spice server thread context only */
297 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
299 ram_addr_t addr
= qxl
->vga
.vram_offset
;
300 void *base
= qxl
->vga
.vram_ptr
;
304 offset
&= ~(TARGET_PAGE_SIZE
-1);
305 assert(offset
< qxl
->vga
.vram_size
);
306 qxl_set_dirty(addr
+ offset
, addr
+ offset
+ TARGET_PAGE_SIZE
);
309 /* can be called from spice server thread context */
310 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
312 ram_addr_t addr
= qxl
->vga
.vram_offset
+ qxl
->shadow_rom
.ram_header_offset
;
313 ram_addr_t end
= qxl
->vga
.vram_offset
+ qxl
->vga
.vram_size
;
314 qxl_set_dirty(addr
, end
);
318 * keep track of some command state, for savevm/loadvm.
319 * called from spice server thread context only
321 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
323 switch (le32_to_cpu(ext
->cmd
.type
)) {
324 case QXL_CMD_SURFACE
:
326 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
327 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
328 PANIC_ON(id
>= NUM_SURFACES
);
329 qemu_mutex_lock(&qxl
->track_lock
);
330 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
331 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
332 qxl
->guest_surfaces
.count
++;
333 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
334 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
336 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
337 qxl
->guest_surfaces
.cmds
[id
] = 0;
338 qxl
->guest_surfaces
.count
--;
340 qemu_mutex_unlock(&qxl
->track_lock
);
345 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
346 if (cmd
->type
== QXL_CURSOR_SET
) {
347 qxl
->guest_cursor
= ext
->cmd
.data
;
354 /* spice display interface callbacks */
356 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
358 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
360 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
361 qxl
->ssd
.worker
= qxl_worker
;
364 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
366 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
368 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
369 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
370 qxl
->rom
->compression_level
= cpu_to_le32(level
);
371 qxl_rom_set_dirty(qxl
);
374 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
376 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
378 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
379 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
380 qxl_rom_set_dirty(qxl
);
383 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
385 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
387 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
388 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
389 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
390 info
->num_memslots
= NUM_MEMSLOTS
;
391 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
392 info
->internal_groupslot_id
= 0;
393 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
394 info
->n_surfaces
= NUM_SURFACES
;
397 static const char *qxl_mode_to_string(int mode
)
400 case QXL_MODE_COMPAT
:
402 case QXL_MODE_NATIVE
:
404 case QXL_MODE_UNDEFINED
:
412 /* called from spice server thread context only */
413 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
415 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
416 SimpleSpiceUpdate
*update
;
417 QXLCommandRing
*ring
;
423 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
425 qemu_mutex_lock(&qxl
->ssd
.lock
);
426 if (qxl
->ssd
.update
!= NULL
) {
427 update
= qxl
->ssd
.update
;
428 qxl
->ssd
.update
= NULL
;
432 qemu_mutex_unlock(&qxl
->ssd
.lock
);
434 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
435 qxl_log_command(qxl
, "vga", ext
);
438 case QXL_MODE_COMPAT
:
439 case QXL_MODE_NATIVE
:
440 case QXL_MODE_UNDEFINED
:
441 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
442 ring
= &qxl
->ram
->cmd_ring
;
443 if (SPICE_RING_IS_EMPTY(ring
)) {
446 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
447 SPICE_RING_CONS_ITEM(ring
, cmd
);
449 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
450 ext
->flags
= qxl
->cmdflags
;
451 SPICE_RING_POP(ring
, notify
);
452 qxl_ring_set_dirty(qxl
);
454 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
456 qxl
->guest_primary
.commands
++;
457 qxl_track_command(qxl
, ext
);
458 qxl_log_command(qxl
, "cmd", ext
);
465 /* called from spice server thread context only */
466 static int interface_req_cmd_notification(QXLInstance
*sin
)
468 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
472 case QXL_MODE_COMPAT
:
473 case QXL_MODE_NATIVE
:
474 case QXL_MODE_UNDEFINED
:
475 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
476 qxl_ring_set_dirty(qxl
);
485 /* called from spice server thread context only */
486 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
488 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
492 #define QXL_FREE_BUNCH_SIZE 32
494 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
495 /* ring full -- can't push */
498 if (!flush
&& d
->oom_running
) {
499 /* collect everything from oom handler before pushing */
502 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
503 /* collect a bit more before pushing */
507 SPICE_RING_PUSH(ring
, notify
);
508 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
509 d
->num_free_res
, notify
? "yes" : "no",
510 ring
->prod
- ring
->cons
, ring
->num_items
,
511 ring
->prod
, ring
->cons
);
513 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
515 SPICE_RING_PROD_ITEM(ring
, item
);
518 d
->last_release
= NULL
;
519 qxl_ring_set_dirty(d
);
522 /* called from spice server thread context only */
523 static void interface_release_resource(QXLInstance
*sin
,
524 struct QXLReleaseInfoExt ext
)
526 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
527 QXLReleaseRing
*ring
;
530 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
531 /* host group -> vga mode update request */
532 qemu_spice_destroy_update(&qxl
->ssd
, (void*)ext
.info
->id
);
537 * ext->info points into guest-visible memory
538 * pci bar 0, $command.release_info
540 ring
= &qxl
->ram
->release_ring
;
541 SPICE_RING_PROD_ITEM(ring
, item
);
543 /* stick head into the ring */
546 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
548 qxl_ring_set_dirty(qxl
);
550 /* append item to the list */
551 qxl
->last_release
->next
= ext
.info
->id
;
552 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
554 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
556 qxl
->last_release
= ext
.info
;
558 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
559 qxl_push_free_res(qxl
, 0);
562 /* called from spice server thread context only */
563 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
565 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
571 case QXL_MODE_COMPAT
:
572 case QXL_MODE_NATIVE
:
573 case QXL_MODE_UNDEFINED
:
574 ring
= &qxl
->ram
->cursor_ring
;
575 if (SPICE_RING_IS_EMPTY(ring
)) {
578 SPICE_RING_CONS_ITEM(ring
, cmd
);
580 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
581 ext
->flags
= qxl
->cmdflags
;
582 SPICE_RING_POP(ring
, notify
);
583 qxl_ring_set_dirty(qxl
);
585 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
587 qxl
->guest_primary
.commands
++;
588 qxl_track_command(qxl
, ext
);
589 qxl_log_command(qxl
, "csr", ext
);
591 qxl_render_cursor(qxl
, ext
);
599 /* called from spice server thread context only */
600 static int interface_req_cursor_notification(QXLInstance
*sin
)
602 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
606 case QXL_MODE_COMPAT
:
607 case QXL_MODE_NATIVE
:
608 case QXL_MODE_UNDEFINED
:
609 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
610 qxl_ring_set_dirty(qxl
);
619 /* called from spice server thread context */
620 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
622 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
626 /* called from spice server thread context only */
627 static int interface_flush_resources(QXLInstance
*sin
)
629 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
632 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
633 ret
= qxl
->num_free_res
;
635 qxl_push_free_res(qxl
, 1);
640 static const QXLInterface qxl_interface
= {
641 .base
.type
= SPICE_INTERFACE_QXL
,
642 .base
.description
= "qxl gpu",
643 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
644 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
646 .attache_worker
= interface_attach_worker
,
647 .set_compression_level
= interface_set_compression_level
,
648 .set_mm_time
= interface_set_mm_time
,
649 .get_init_info
= interface_get_init_info
,
651 /* the callbacks below are called from spice server thread context */
652 .get_command
= interface_get_command
,
653 .req_cmd_notification
= interface_req_cmd_notification
,
654 .release_resource
= interface_release_resource
,
655 .get_cursor_command
= interface_get_cursor_command
,
656 .req_cursor_notification
= interface_req_cursor_notification
,
657 .notify_update
= interface_notify_update
,
658 .flush_resources
= interface_flush_resources
,
661 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
663 if (d
->mode
== QXL_MODE_VGA
) {
666 dprint(d
, 1, "%s\n", __FUNCTION__
);
667 qemu_spice_create_host_primary(&d
->ssd
);
668 d
->mode
= QXL_MODE_VGA
;
669 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
672 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
674 if (d
->mode
!= QXL_MODE_VGA
) {
677 dprint(d
, 1, "%s\n", __FUNCTION__
);
678 qxl_destroy_primary(d
);
681 static void qxl_set_irq(PCIQXLDevice
*d
)
683 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
684 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
685 int level
= !!(pending
& mask
);
686 qemu_set_irq(d
->pci
.irq
[0], level
);
687 qxl_ring_set_dirty(d
);
690 static void qxl_write_config(PCIDevice
*d
, uint32_t address
,
691 uint32_t val
, int len
)
693 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, d
);
694 VGACommonState
*vga
= &qxl
->vga
;
696 vga_dirty_log_stop(vga
);
697 pci_default_write_config(d
, address
, val
, len
);
698 if (vga
->map_addr
&& qxl
->pci
.io_regions
[0].addr
== -1) {
701 vga_dirty_log_start(vga
);
704 static void qxl_check_state(PCIQXLDevice
*d
)
706 QXLRam
*ram
= d
->ram
;
708 assert(SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
709 assert(SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
712 static void qxl_reset_state(PCIQXLDevice
*d
)
714 QXLRam
*ram
= d
->ram
;
715 QXLRom
*rom
= d
->rom
;
717 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
718 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
719 d
->shadow_rom
.update_id
= cpu_to_le32(0);
720 *rom
= d
->shadow_rom
;
721 qxl_rom_set_dirty(d
);
724 d
->last_release
= NULL
;
725 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
728 static void qxl_soft_reset(PCIQXLDevice
*d
)
730 dprint(d
, 1, "%s:\n", __FUNCTION__
);
734 qxl_enter_vga_mode(d
);
736 d
->mode
= QXL_MODE_UNDEFINED
;
740 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
742 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
743 loadvm
? " (loadvm)" : "");
745 qxl_spice_reset_cursor(d
);
746 qxl_spice_reset_image_cache(d
);
747 qxl_reset_surfaces(d
);
748 qxl_reset_memslots(d
);
750 /* pre loadvm reset must not touch QXLRam. This lives in
751 * device memory, is migrated together with RAM and thus
752 * already loaded at this point */
756 qemu_spice_create_host_memslot(&d
->ssd
);
759 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
762 static void qxl_reset_handler(DeviceState
*dev
)
764 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
765 qxl_hard_reset(d
, 0);
768 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
770 VGACommonState
*vga
= opaque
;
771 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
773 if (qxl
->mode
!= QXL_MODE_VGA
) {
774 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
775 qxl_destroy_primary(qxl
);
778 vga_ioport_write(opaque
, addr
, val
);
781 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
)
783 static const int regions
[] = {
785 QXL_VRAM_RANGE_INDEX
,
787 uint64_t guest_start
;
793 QXLDevMemSlot memslot
;
796 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
797 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
799 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
800 __FUNCTION__
, slot_id
,
801 guest_start
, guest_end
);
803 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
804 PANIC_ON(guest_start
> guest_end
);
806 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
807 pci_region
= regions
[i
];
808 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
809 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
811 if (pci_start
== -1) {
814 /* start address in range ? */
815 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
818 /* end address in range ? */
819 if (guest_end
> pci_end
) {
825 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
827 switch (pci_region
) {
828 case QXL_RAM_RANGE_INDEX
:
829 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vga
.vram_offset
);
831 case QXL_VRAM_RANGE_INDEX
:
832 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vram_offset
);
835 /* should not happen */
839 memslot
.slot_id
= slot_id
;
840 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
841 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
842 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
843 memslot
.addr_delta
= memslot
.virt_start
- delta
;
844 memslot
.generation
= d
->rom
->slot_generation
= 0;
845 qxl_rom_set_dirty(d
);
847 dprint(d
, 1, "%s: slot %d: host virt 0x%" PRIx64
" - 0x%" PRIx64
"\n",
848 __FUNCTION__
, memslot
.slot_id
,
849 memslot
.virt_start
, memslot
.virt_end
);
851 qemu_spice_add_memslot(&d
->ssd
, &memslot
);
852 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
853 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
854 d
->guest_slots
[slot_id
].delta
= delta
;
855 d
->guest_slots
[slot_id
].active
= 1;
858 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
860 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
861 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
862 d
->guest_slots
[slot_id
].active
= 0;
865 static void qxl_reset_memslots(PCIQXLDevice
*d
)
867 dprint(d
, 1, "%s:\n", __FUNCTION__
);
868 qxl_spice_reset_memslots(d
);
869 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
872 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
874 dprint(d
, 1, "%s:\n", __FUNCTION__
);
875 d
->mode
= QXL_MODE_UNDEFINED
;
876 qxl_spice_destroy_surfaces(d
);
879 /* called from spice server thread context only */
880 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
882 uint64_t phys
= le64_to_cpu(pqxl
);
883 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
884 uint64_t offset
= phys
& 0xffffffffffff;
887 case MEMSLOT_GROUP_HOST
:
888 return (void*)offset
;
889 case MEMSLOT_GROUP_GUEST
:
890 PANIC_ON(slot
> NUM_MEMSLOTS
);
891 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
892 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
893 offset
-= qxl
->guest_slots
[slot
].delta
;
894 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
895 return qxl
->guest_slots
[slot
].ptr
+ offset
;
901 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
)
903 QXLDevSurfaceCreate surface
;
904 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
906 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
907 qxl_exit_vga_mode(qxl
);
909 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
910 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
912 surface
.format
= le32_to_cpu(sc
->format
);
913 surface
.height
= le32_to_cpu(sc
->height
);
914 surface
.mem
= le64_to_cpu(sc
->mem
);
915 surface
.position
= le32_to_cpu(sc
->position
);
916 surface
.stride
= le32_to_cpu(sc
->stride
);
917 surface
.width
= le32_to_cpu(sc
->width
);
918 surface
.type
= le32_to_cpu(sc
->type
);
919 surface
.flags
= le32_to_cpu(sc
->flags
);
921 surface
.mouse_mode
= true;
922 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
924 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
927 qxl
->mode
= QXL_MODE_NATIVE
;
929 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
);
931 /* for local rendering */
932 qxl_render_resize(qxl
);
935 static void qxl_destroy_primary(PCIQXLDevice
*d
)
937 if (d
->mode
== QXL_MODE_UNDEFINED
) {
941 dprint(d
, 1, "%s\n", __FUNCTION__
);
943 d
->mode
= QXL_MODE_UNDEFINED
;
944 qemu_spice_destroy_primary_surface(&d
->ssd
, 0);
947 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
949 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
950 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
951 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
952 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
957 QXLSurfaceCreate surface
= {
958 .width
= mode
->x_res
,
959 .height
= mode
->y_res
,
960 .stride
= -mode
->x_res
* 4,
961 .format
= SPICE_SURFACE_FMT_32_xRGB
,
962 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
964 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
967 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__
,
968 modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
970 qxl_hard_reset(d
, 0);
973 d
->guest_slots
[0].slot
= slot
;
974 qxl_add_memslot(d
, 0, devmem
);
976 d
->guest_primary
.surface
= surface
;
977 qxl_create_guest_primary(d
, 0);
979 d
->mode
= QXL_MODE_COMPAT
;
980 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
981 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
982 if (mode
->bits
== 16) {
983 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
986 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
987 d
->rom
->mode
= cpu_to_le32(modenr
);
988 qxl_rom_set_dirty(d
);
991 static void ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
993 PCIQXLDevice
*d
= opaque
;
994 uint32_t io_port
= addr
- d
->io_base
;
998 case QXL_IO_SET_MODE
:
999 case QXL_IO_MEMSLOT_ADD
:
1000 case QXL_IO_MEMSLOT_DEL
:
1001 case QXL_IO_CREATE_PRIMARY
:
1002 case QXL_IO_UPDATE_IRQ
:
1006 if (d
->mode
== QXL_MODE_NATIVE
|| d
->mode
== QXL_MODE_COMPAT
)
1008 dprint(d
, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__
, io_port
);
1013 case QXL_IO_UPDATE_AREA
:
1015 QXLRect update
= d
->ram
->update_area
;
1016 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1017 &update
, NULL
, 0, 0);
1020 case QXL_IO_NOTIFY_CMD
:
1021 qemu_spice_wakeup(&d
->ssd
);
1023 case QXL_IO_NOTIFY_CURSOR
:
1024 qemu_spice_wakeup(&d
->ssd
);
1026 case QXL_IO_UPDATE_IRQ
:
1029 case QXL_IO_NOTIFY_OOM
:
1030 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1034 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1041 case QXL_IO_SET_MODE
:
1042 dprint(d
, 1, "QXL_SET_MODE %d\n", val
);
1043 qxl_set_mode(d
, val
, 0);
1046 if (d
->guestdebug
) {
1047 fprintf(stderr
, "qxl/guest-%d: %ld: %s", d
->id
,
1048 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1052 dprint(d
, 1, "QXL_IO_RESET\n");
1053 qxl_hard_reset(d
, 0);
1055 case QXL_IO_MEMSLOT_ADD
:
1056 PANIC_ON(val
>= NUM_MEMSLOTS
);
1057 PANIC_ON(d
->guest_slots
[val
].active
);
1058 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1059 qxl_add_memslot(d
, val
, 0);
1061 case QXL_IO_MEMSLOT_DEL
:
1062 qxl_del_memslot(d
, val
);
1064 case QXL_IO_CREATE_PRIMARY
:
1066 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY\n");
1067 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1068 qxl_create_guest_primary(d
, 0);
1070 case QXL_IO_DESTROY_PRIMARY
:
1072 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (%s)\n", qxl_mode_to_string(d
->mode
));
1073 qxl_destroy_primary(d
);
1075 case QXL_IO_DESTROY_SURFACE_WAIT
:
1076 qxl_spice_destroy_surface_wait(d
, val
);
1078 case QXL_IO_DESTROY_ALL_SURFACES
:
1079 qxl_spice_destroy_surfaces(d
);
1082 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1087 static uint32_t ioport_read(void *opaque
, uint32_t addr
)
1089 PCIQXLDevice
*d
= opaque
;
1091 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1095 static void qxl_map(PCIDevice
*pci
, int region_num
,
1096 pcibus_t addr
, pcibus_t size
, int type
)
1098 static const char *names
[] = {
1099 [ QXL_IO_RANGE_INDEX
] = "ioports",
1100 [ QXL_RAM_RANGE_INDEX
] = "devram",
1101 [ QXL_ROM_RANGE_INDEX
] = "rom",
1102 [ QXL_VRAM_RANGE_INDEX
] = "vram",
1104 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, pci
);
1106 dprint(qxl
, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__
,
1107 region_num
, names
[region_num
], addr
, size
);
1109 switch (region_num
) {
1110 case QXL_IO_RANGE_INDEX
:
1111 register_ioport_write(addr
, size
, 1, ioport_write
, pci
);
1112 register_ioport_read(addr
, size
, 1, ioport_read
, pci
);
1113 qxl
->io_base
= addr
;
1115 case QXL_RAM_RANGE_INDEX
:
1116 cpu_register_physical_memory(addr
, size
, qxl
->vga
.vram_offset
| IO_MEM_RAM
);
1117 qxl
->vga
.map_addr
= addr
;
1118 qxl
->vga
.map_end
= addr
+ size
;
1120 vga_dirty_log_start(&qxl
->vga
);
1123 case QXL_ROM_RANGE_INDEX
:
1124 cpu_register_physical_memory(addr
, size
, qxl
->rom_offset
| IO_MEM_ROM
);
1126 case QXL_VRAM_RANGE_INDEX
:
1127 cpu_register_physical_memory(addr
, size
, qxl
->vram_offset
| IO_MEM_RAM
);
1132 static void pipe_read(void *opaque
)
1134 PCIQXLDevice
*d
= opaque
;
1139 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1140 } while (len
== sizeof(dummy
));
1144 /* called from spice server thread context only */
1145 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1147 uint32_t old_pending
;
1148 uint32_t le_events
= cpu_to_le32(events
);
1150 assert(d
->ssd
.running
);
1151 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1152 if ((old_pending
& le_events
) == le_events
) {
1155 if (pthread_self() == d
->main
) {
1158 if (write(d
->pipe
[1], d
, 1) != 1) {
1159 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1164 static void init_pipe_signaling(PCIQXLDevice
*d
)
1166 if (pipe(d
->pipe
) < 0) {
1167 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1170 #ifdef CONFIG_IOTHREAD
1171 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1173 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
/* | O_ASYNC */);
1175 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1176 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1178 d
->main
= pthread_self();
1179 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1182 /* graphics console */
1184 static void qxl_hw_update(void *opaque
)
1186 PCIQXLDevice
*qxl
= opaque
;
1187 VGACommonState
*vga
= &qxl
->vga
;
1189 switch (qxl
->mode
) {
1193 case QXL_MODE_COMPAT
:
1194 case QXL_MODE_NATIVE
:
1195 qxl_render_update(qxl
);
1202 static void qxl_hw_invalidate(void *opaque
)
1204 PCIQXLDevice
*qxl
= opaque
;
1205 VGACommonState
*vga
= &qxl
->vga
;
1207 vga
->invalidate(vga
);
1210 static void qxl_hw_screen_dump(void *opaque
, const char *filename
)
1212 PCIQXLDevice
*qxl
= opaque
;
1213 VGACommonState
*vga
= &qxl
->vga
;
1215 switch (qxl
->mode
) {
1216 case QXL_MODE_COMPAT
:
1217 case QXL_MODE_NATIVE
:
1218 qxl_render_update(qxl
);
1219 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1222 vga
->screen_dump(vga
, filename
);
1229 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1231 PCIQXLDevice
*qxl
= opaque
;
1232 VGACommonState
*vga
= &qxl
->vga
;
1234 if (qxl
->mode
== QXL_MODE_VGA
) {
1235 vga
->text_update(vga
, chardata
);
1240 static void qxl_vm_change_state_handler(void *opaque
, int running
, int reason
)
1242 PCIQXLDevice
*qxl
= opaque
;
1243 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, reason
);
1245 if (!running
&& qxl
->mode
== QXL_MODE_NATIVE
) {
1246 /* dirty all vram (which holds surfaces) and devram (primary surface)
1247 * to make sure they are saved */
1248 /* FIXME #1: should go out during "live" stage */
1249 /* FIXME #2: we only need to save the areas which are actually used */
1250 ram_addr_t vram_addr
= qxl
->vram_offset
;
1251 ram_addr_t surface0_addr
= qxl
->vga
.vram_offset
+ qxl
->shadow_rom
.draw_area_offset
;
1252 qxl_set_dirty(vram_addr
, vram_addr
+ qxl
->vram_size
);
1253 qxl_set_dirty(surface0_addr
, surface0_addr
+ qxl
->shadow_rom
.surface0_area_size
);
1257 /* display change listener */
1259 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1261 if (qxl0
->mode
== QXL_MODE_VGA
) {
1262 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1266 static void display_resize(struct DisplayState
*ds
)
1268 if (qxl0
->mode
== QXL_MODE_VGA
) {
1269 qemu_spice_display_resize(&qxl0
->ssd
);
1273 static void display_refresh(struct DisplayState
*ds
)
1275 if (qxl0
->mode
== QXL_MODE_VGA
) {
1276 qemu_spice_display_refresh(&qxl0
->ssd
);
1280 static DisplayChangeListener display_listener
= {
1281 .dpy_update
= display_update
,
1282 .dpy_resize
= display_resize
,
1283 .dpy_refresh
= display_refresh
,
1286 static int qxl_init_common(PCIQXLDevice
*qxl
)
1288 uint8_t* config
= qxl
->pci
.config
;
1289 uint32_t pci_device_rev
;
1292 qxl
->mode
= QXL_MODE_UNDEFINED
;
1293 qxl
->generation
= 1;
1294 qxl
->num_memslots
= NUM_MEMSLOTS
;
1295 qxl
->num_surfaces
= NUM_SURFACES
;
1296 qemu_mutex_init(&qxl
->track_lock
);
1298 switch (qxl
->revision
) {
1299 case 1: /* spice 0.4 -- qxl-1 */
1300 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1302 case 2: /* spice 0.6 -- qxl-2 */
1304 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1308 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1309 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1311 qxl
->rom_size
= qxl_rom_size();
1312 qxl
->rom_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vrom", qxl
->rom_size
);
1316 if (qxl
->vram_size
< 16 * 1024 * 1024) {
1317 qxl
->vram_size
= 16 * 1024 * 1024;
1319 if (qxl
->revision
== 1) {
1320 qxl
->vram_size
= 4096;
1322 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1323 qxl
->vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vram", qxl
->vram_size
);
1325 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1326 if (qxl
->revision
== 1) {
1330 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1331 io_size
, PCI_BASE_ADDRESS_SPACE_IO
, qxl_map
);
1333 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1334 qxl
->rom_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1337 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1338 qxl
->vga
.vram_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1341 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
, qxl
->vram_size
,
1342 PCI_BASE_ADDRESS_SPACE_MEMORY
, qxl_map
);
1344 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1345 qxl
->ssd
.qxl
.id
= qxl
->id
;
1346 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1347 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1349 init_pipe_signaling(qxl
);
1350 qxl_reset_state(qxl
);
1355 static int qxl_init_primary(PCIDevice
*dev
)
1357 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1358 VGACommonState
*vga
= &qxl
->vga
;
1359 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1363 if (ram_size
< 32 * 1024 * 1024) {
1364 ram_size
= 32 * 1024 * 1024;
1366 vga_common_init(vga
, ram_size
);
1368 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write
, vga
);
1369 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write
, vga
);
1370 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write
, vga
);
1371 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write
, vga
);
1372 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write
, vga
);
1374 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1375 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1376 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1379 register_displaychangelistener(vga
->ds
, &display_listener
);
1381 return qxl_init_common(qxl
);
1384 static int qxl_init_secondary(PCIDevice
*dev
)
1386 static int device_id
= 1;
1387 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1388 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1390 qxl
->id
= device_id
++;
1392 if (ram_size
< 16 * 1024 * 1024) {
1393 ram_size
= 16 * 1024 * 1024;
1395 qxl
->vga
.vram_size
= ram_size
;
1396 qxl
->vga
.vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vgavram",
1397 qxl
->vga
.vram_size
);
1398 qxl
->vga
.vram_ptr
= qemu_get_ram_ptr(qxl
->vga
.vram_offset
);
1400 return qxl_init_common(qxl
);
1403 static void qxl_pre_save(void *opaque
)
1405 PCIQXLDevice
* d
= opaque
;
1406 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1408 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1409 if (d
->last_release
== NULL
) {
1410 d
->last_release_offset
= 0;
1412 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1414 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1417 static int qxl_pre_load(void *opaque
)
1419 PCIQXLDevice
* d
= opaque
;
1421 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1422 qxl_hard_reset(d
, 1);
1423 qxl_exit_vga_mode(d
);
1424 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1428 static int qxl_post_load(void *opaque
, int version
)
1430 PCIQXLDevice
* d
= opaque
;
1431 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1432 QXLCommandExt
*cmds
;
1433 int in
, out
, i
, newmode
;
1435 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1437 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1438 if (d
->last_release_offset
== 0) {
1439 d
->last_release
= NULL
;
1441 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1444 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1446 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1447 qxl_mode_to_string(d
->mode
));
1449 d
->mode
= QXL_MODE_UNDEFINED
;
1451 case QXL_MODE_UNDEFINED
:
1454 qxl_enter_vga_mode(d
);
1456 case QXL_MODE_NATIVE
:
1457 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1458 if (!d
->guest_slots
[i
].active
) {
1461 qxl_add_memslot(d
, i
, 0);
1463 qxl_create_guest_primary(d
, 1);
1465 /* replay surface-create and cursor-set commands */
1466 cmds
= qemu_mallocz(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1467 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1468 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1471 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1472 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1473 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1476 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1477 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1478 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1480 qxl_spice_loadvm_commands(d
, cmds
, out
);
1484 case QXL_MODE_COMPAT
:
1485 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1488 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1493 #define QXL_SAVE_VERSION 21
1495 static VMStateDescription qxl_memslot
= {
1496 .name
= "qxl-memslot",
1497 .version_id
= QXL_SAVE_VERSION
,
1498 .minimum_version_id
= QXL_SAVE_VERSION
,
1499 .fields
= (VMStateField
[]) {
1500 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1501 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1502 VMSTATE_UINT32(active
, struct guest_slots
),
1503 VMSTATE_END_OF_LIST()
1507 static VMStateDescription qxl_surface
= {
1508 .name
= "qxl-surface",
1509 .version_id
= QXL_SAVE_VERSION
,
1510 .minimum_version_id
= QXL_SAVE_VERSION
,
1511 .fields
= (VMStateField
[]) {
1512 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1513 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1514 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1515 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1516 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1517 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1518 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1519 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1520 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1521 VMSTATE_END_OF_LIST()
1525 static VMStateDescription qxl_vmstate
= {
1527 .version_id
= QXL_SAVE_VERSION
,
1528 .minimum_version_id
= QXL_SAVE_VERSION
,
1529 .pre_save
= qxl_pre_save
,
1530 .pre_load
= qxl_pre_load
,
1531 .post_load
= qxl_post_load
,
1532 .fields
= (VMStateField
[]) {
1533 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1534 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1535 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1536 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1537 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1538 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1539 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1540 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1541 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1542 qxl_memslot
, struct guest_slots
),
1543 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1544 qxl_surface
, QXLSurfaceCreate
),
1545 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1546 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1547 vmstate_info_uint64
, uint64_t),
1548 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1549 VMSTATE_END_OF_LIST()
1553 static PCIDeviceInfo qxl_info_primary
= {
1554 .qdev
.name
= "qxl-vga",
1555 .qdev
.desc
= "Spice QXL GPU (primary, vga compatible)",
1556 .qdev
.size
= sizeof(PCIQXLDevice
),
1557 .qdev
.reset
= qxl_reset_handler
,
1558 .qdev
.vmsd
= &qxl_vmstate
,
1560 .init
= qxl_init_primary
,
1561 .config_write
= qxl_write_config
,
1562 .romfile
= "vgabios-qxl.bin",
1563 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1564 .device_id
= QXL_DEVICE_ID_STABLE
,
1565 .class_id
= PCI_CLASS_DISPLAY_VGA
,
1566 .qdev
.props
= (Property
[]) {
1567 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1568 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1569 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1570 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1571 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1572 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1573 DEFINE_PROP_END_OF_LIST(),
1577 static PCIDeviceInfo qxl_info_secondary
= {
1579 .qdev
.desc
= "Spice QXL GPU (secondary)",
1580 .qdev
.size
= sizeof(PCIQXLDevice
),
1581 .qdev
.reset
= qxl_reset_handler
,
1582 .qdev
.vmsd
= &qxl_vmstate
,
1583 .init
= qxl_init_secondary
,
1584 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1585 .device_id
= QXL_DEVICE_ID_STABLE
,
1586 .class_id
= PCI_CLASS_DISPLAY_OTHER
,
1587 .qdev
.props
= (Property
[]) {
1588 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1589 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1590 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1591 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1592 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1593 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1594 DEFINE_PROP_END_OF_LIST(),
1598 static void qxl_register(void)
1600 pci_qdev_register(&qxl_info_primary
);
1601 pci_qdev_register(&qxl_info_secondary
);
1604 device_init(qxl_register
);