2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
30 #ifndef CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC
31 /* spice-protocol is too old, add missing definitions */
32 #define QXL_IO_MONITORS_CONFIG_ASYNC (QXL_IO_FLUSH_RELEASE + 1)
36 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
37 * such can be changed by the guest, so to avoid a guest trigerrable
38 * abort we just qxl_set_guest_bug and set the return to NULL. Still
39 * it may happen as a result of emulator bug as well.
41 #undef SPICE_RING_PROD_ITEM
42 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
48 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
49 "! %p <= %p < %p", (uint8_t *)start, \
50 (uint8_t *)m_item, (uint8_t *)end); \
57 #undef SPICE_RING_CONS_ITEM
58 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
59 typeof(r) start = r; \
60 typeof(r) end = r + 1; \
61 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
62 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
63 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
64 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
65 "! %p <= %p < %p", (uint8_t *)start, \
66 (uint8_t *)m_item, (uint8_t *)end); \
74 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
76 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
78 #define QXL_MODE(_x, _y, _b, _o) \
82 .stride = (_x) * (_b) / 8, \
83 .x_mili = PIXEL_SIZE * (_x), \
84 .y_mili = PIXEL_SIZE * (_y), \
88 #define QXL_MODE_16_32(x_res, y_res, orientation) \
89 QXL_MODE(x_res, y_res, 16, orientation), \
90 QXL_MODE(x_res, y_res, 32, orientation)
92 #define QXL_MODE_EX(x_res, y_res) \
93 QXL_MODE_16_32(x_res, y_res, 0), \
94 QXL_MODE_16_32(y_res, x_res, 1), \
95 QXL_MODE_16_32(x_res, y_res, 2), \
96 QXL_MODE_16_32(y_res, x_res, 3)
98 static QXLMode qxl_modes
[] = {
99 QXL_MODE_EX(640, 480),
100 QXL_MODE_EX(800, 480),
101 QXL_MODE_EX(800, 600),
102 QXL_MODE_EX(832, 624),
103 QXL_MODE_EX(960, 640),
104 QXL_MODE_EX(1024, 600),
105 QXL_MODE_EX(1024, 768),
106 QXL_MODE_EX(1152, 864),
107 QXL_MODE_EX(1152, 870),
108 QXL_MODE_EX(1280, 720),
109 QXL_MODE_EX(1280, 760),
110 QXL_MODE_EX(1280, 768),
111 QXL_MODE_EX(1280, 800),
112 QXL_MODE_EX(1280, 960),
113 QXL_MODE_EX(1280, 1024),
114 QXL_MODE_EX(1360, 768),
115 QXL_MODE_EX(1366, 768),
116 QXL_MODE_EX(1400, 1050),
117 QXL_MODE_EX(1440, 900),
118 QXL_MODE_EX(1600, 900),
119 QXL_MODE_EX(1600, 1200),
120 QXL_MODE_EX(1680, 1050),
121 QXL_MODE_EX(1920, 1080),
122 /* these modes need more than 8 MB video memory */
123 QXL_MODE_EX(1920, 1200),
124 QXL_MODE_EX(1920, 1440),
125 QXL_MODE_EX(2048, 1536),
126 QXL_MODE_EX(2560, 1440),
127 QXL_MODE_EX(2560, 1600),
128 /* these modes need more than 16 MB video memory */
129 QXL_MODE_EX(2560, 2048),
130 QXL_MODE_EX(2800, 2100),
131 QXL_MODE_EX(3200, 2400),
134 static PCIQXLDevice
*qxl0
;
136 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
137 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
138 static void qxl_reset_memslots(PCIQXLDevice
*d
);
139 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
140 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
142 void qxl_set_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
144 trace_qxl_set_guest_bug(qxl
->id
);
145 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
147 if (qxl
->guestdebug
) {
150 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
151 vfprintf(stderr
, msg
, ap
);
152 fprintf(stderr
, "\n");
157 static void qxl_clear_guest_bug(PCIQXLDevice
*qxl
)
162 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
163 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
164 uint32_t num_dirty_rects
,
165 uint32_t clear_dirty_region
,
166 qxl_async_io async
, struct QXLCookie
*cookie
)
168 trace_qxl_spice_update_area(qxl
->id
, surface_id
, area
->left
, area
->right
,
169 area
->top
, area
->bottom
);
170 trace_qxl_spice_update_area_rest(qxl
->id
, num_dirty_rects
,
172 if (async
== QXL_SYNC
) {
173 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
174 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
176 assert(cookie
!= NULL
);
177 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
178 clear_dirty_region
, (uintptr_t)cookie
);
182 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
185 trace_qxl_spice_destroy_surface_wait_complete(qxl
->id
, id
);
186 qemu_mutex_lock(&qxl
->track_lock
);
187 qxl
->guest_surfaces
.cmds
[id
] = 0;
188 qxl
->guest_surfaces
.count
--;
189 qemu_mutex_unlock(&qxl
->track_lock
);
192 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
197 trace_qxl_spice_destroy_surface_wait(qxl
->id
, id
, async
);
199 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
200 QXL_IO_DESTROY_SURFACE_ASYNC
);
201 cookie
->u
.surface_id
= id
;
202 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
, (uintptr_t)cookie
);
204 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
205 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
209 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
211 trace_qxl_spice_flush_surfaces_async(qxl
->id
, qxl
->guest_surfaces
.count
,
213 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
,
214 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
215 QXL_IO_FLUSH_SURFACES_ASYNC
));
218 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
221 trace_qxl_spice_loadvm_commands(qxl
->id
, ext
, count
);
222 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
225 void qxl_spice_oom(PCIQXLDevice
*qxl
)
227 trace_qxl_spice_oom(qxl
->id
);
228 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
231 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
233 trace_qxl_spice_reset_memslots(qxl
->id
);
234 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
237 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
239 trace_qxl_spice_destroy_surfaces_complete(qxl
->id
);
240 qemu_mutex_lock(&qxl
->track_lock
);
241 memset(qxl
->guest_surfaces
.cmds
, 0,
242 sizeof(qxl
->guest_surfaces
.cmds
) * qxl
->ssd
.num_surfaces
);
243 qxl
->guest_surfaces
.count
= 0;
244 qemu_mutex_unlock(&qxl
->track_lock
);
247 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
249 trace_qxl_spice_destroy_surfaces(qxl
->id
, async
);
251 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
,
252 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
253 QXL_IO_DESTROY_ALL_SURFACES_ASYNC
));
255 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
256 qxl_spice_destroy_surfaces_complete(qxl
);
260 static void qxl_spice_monitors_config_async(PCIQXLDevice
*qxl
, int replay
)
262 trace_qxl_spice_monitors_config(qxl
->id
);
263 /* 0x000b01 == 0.11.1 */
264 #if SPICE_SERVER_VERSION >= 0x000b01 && \
265 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
268 * don't use QXL_COOKIE_TYPE_IO:
269 * - we are not running yet (post_load), we will assert
271 * - this is not a guest io, but a reply, so async_io isn't set.
273 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
274 qxl
->guest_monitors_config
,
276 (uintptr_t)qxl_cookie_new(
277 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
,
280 qxl
->guest_monitors_config
= qxl
->ram
->monitors_config
;
281 spice_qxl_monitors_config_async(&qxl
->ssd
.qxl
,
282 qxl
->ram
->monitors_config
,
284 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
285 QXL_IO_MONITORS_CONFIG_ASYNC
));
288 fprintf(stderr
, "qxl: too old spice-protocol/spice-server for "
289 "QXL_IO_MONITORS_CONFIG_ASYNC\n");
293 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
295 trace_qxl_spice_reset_image_cache(qxl
->id
);
296 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
299 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
301 trace_qxl_spice_reset_cursor(qxl
->id
);
302 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
303 qemu_mutex_lock(&qxl
->track_lock
);
304 qxl
->guest_cursor
= 0;
305 qemu_mutex_unlock(&qxl
->track_lock
);
309 static inline uint32_t msb_mask(uint32_t val
)
314 mask
= ~(val
- 1) & val
;
316 } while (mask
< val
);
321 static ram_addr_t
qxl_rom_size(void)
323 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
325 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
326 rom_size
= msb_mask(rom_size
* 2 - 1);
330 static void init_qxl_rom(PCIQXLDevice
*d
)
332 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
333 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
334 uint32_t ram_header_size
;
335 uint32_t surface0_area_size
;
340 memset(rom
, 0, d
->rom_size
);
342 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
343 rom
->id
= cpu_to_le32(d
->id
);
344 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
345 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
347 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
348 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
349 rom
->slots_start
= 1;
350 rom
->slots_end
= NUM_MEMSLOTS
- 1;
351 rom
->n_surfaces
= cpu_to_le32(d
->ssd
.num_surfaces
);
353 for (i
= 0, n
= 0; i
< ARRAY_SIZE(qxl_modes
); i
++) {
354 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
355 if (fb
> d
->vgamem_size
) {
358 modes
->modes
[n
].id
= cpu_to_le32(i
);
359 modes
->modes
[n
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
360 modes
->modes
[n
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
361 modes
->modes
[n
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
362 modes
->modes
[n
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
363 modes
->modes
[n
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
364 modes
->modes
[n
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
365 modes
->modes
[n
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
368 modes
->n_modes
= cpu_to_le32(n
);
370 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
371 surface0_area_size
= ALIGN(d
->vgamem_size
, 4096);
372 num_pages
= d
->vga
.vram_size
;
373 num_pages
-= ram_header_size
;
374 num_pages
-= surface0_area_size
;
375 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
377 rom
->draw_area_offset
= cpu_to_le32(0);
378 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
379 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
380 rom
->num_pages
= cpu_to_le32(num_pages
);
381 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
383 d
->shadow_rom
= *rom
;
388 static void init_qxl_ram(PCIQXLDevice
*d
)
393 buf
= d
->vga
.vram_ptr
;
394 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
395 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
396 d
->ram
->int_pending
= cpu_to_le32(0);
397 d
->ram
->int_mask
= cpu_to_le32(0);
398 d
->ram
->update_surface
= 0;
399 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
400 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
401 SPICE_RING_INIT(&d
->ram
->release_ring
);
402 SPICE_RING_PROD_ITEM(d
, &d
->ram
->release_ring
, item
);
405 qxl_ring_set_dirty(d
);
408 /* can be called from spice server thread context */
409 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
411 memory_region_set_dirty(mr
, addr
, end
- addr
);
414 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
416 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
419 /* called from spice server thread context only */
420 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
422 void *base
= qxl
->vga
.vram_ptr
;
426 offset
&= ~(TARGET_PAGE_SIZE
-1);
427 assert(offset
< qxl
->vga
.vram_size
);
428 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
431 /* can be called from spice server thread context */
432 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
434 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
435 ram_addr_t end
= qxl
->vga
.vram_size
;
436 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
440 * keep track of some command state, for savevm/loadvm.
441 * called from spice server thread context only
443 static int qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
445 switch (le32_to_cpu(ext
->cmd
.type
)) {
446 case QXL_CMD_SURFACE
:
448 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
453 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
455 if (id
>= qxl
->ssd
.num_surfaces
) {
456 qxl_set_guest_bug(qxl
, "QXL_CMD_SURFACE id %d >= %d", id
,
457 qxl
->ssd
.num_surfaces
);
460 qemu_mutex_lock(&qxl
->track_lock
);
461 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
462 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
463 qxl
->guest_surfaces
.count
++;
464 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
465 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
467 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
468 qxl
->guest_surfaces
.cmds
[id
] = 0;
469 qxl
->guest_surfaces
.count
--;
471 qemu_mutex_unlock(&qxl
->track_lock
);
476 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
481 if (cmd
->type
== QXL_CURSOR_SET
) {
482 qemu_mutex_lock(&qxl
->track_lock
);
483 qxl
->guest_cursor
= ext
->cmd
.data
;
484 qemu_mutex_unlock(&qxl
->track_lock
);
492 /* spice display interface callbacks */
494 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
496 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
498 trace_qxl_interface_attach_worker(qxl
->id
);
499 qxl
->ssd
.worker
= qxl_worker
;
502 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
504 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
506 trace_qxl_interface_set_compression_level(qxl
->id
, level
);
507 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
508 qxl
->rom
->compression_level
= cpu_to_le32(level
);
509 qxl_rom_set_dirty(qxl
);
512 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
514 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
516 trace_qxl_interface_set_mm_time(qxl
->id
, mm_time
);
517 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
518 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
519 qxl_rom_set_dirty(qxl
);
522 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
524 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
526 trace_qxl_interface_get_init_info(qxl
->id
);
527 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
528 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
529 info
->num_memslots
= NUM_MEMSLOTS
;
530 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
531 info
->internal_groupslot_id
= 0;
532 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
533 info
->n_surfaces
= qxl
->ssd
.num_surfaces
;
536 static const char *qxl_mode_to_string(int mode
)
539 case QXL_MODE_COMPAT
:
541 case QXL_MODE_NATIVE
:
543 case QXL_MODE_UNDEFINED
:
551 static const char *io_port_to_string(uint32_t io_port
)
553 if (io_port
>= QXL_IO_RANGE_SIZE
) {
554 return "out of range";
556 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
557 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
558 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
559 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
560 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
561 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
562 [QXL_IO_RESET
] = "QXL_IO_RESET",
563 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
564 [QXL_IO_LOG
] = "QXL_IO_LOG",
565 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
566 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
567 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
568 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
569 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
570 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
571 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
572 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
573 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
574 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
575 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
576 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
577 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
578 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
579 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
580 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
581 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
582 [QXL_IO_MONITORS_CONFIG_ASYNC
] = "QXL_IO_MONITORS_CONFIG_ASYNC",
584 return io_port_to_string
[io_port
];
587 /* called from spice server thread context only */
588 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
590 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
591 SimpleSpiceUpdate
*update
;
592 QXLCommandRing
*ring
;
596 trace_qxl_ring_command_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
601 qemu_mutex_lock(&qxl
->ssd
.lock
);
602 update
= QTAILQ_FIRST(&qxl
->ssd
.updates
);
603 if (update
!= NULL
) {
604 QTAILQ_REMOVE(&qxl
->ssd
.updates
, update
, next
);
608 qemu_mutex_unlock(&qxl
->ssd
.lock
);
610 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
611 qxl_log_command(qxl
, "vga", ext
);
614 case QXL_MODE_COMPAT
:
615 case QXL_MODE_NATIVE
:
616 case QXL_MODE_UNDEFINED
:
617 ring
= &qxl
->ram
->cmd_ring
;
618 if (qxl
->guest_bug
|| SPICE_RING_IS_EMPTY(ring
)) {
621 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
626 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
627 ext
->flags
= qxl
->cmdflags
;
628 SPICE_RING_POP(ring
, notify
);
629 qxl_ring_set_dirty(qxl
);
631 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
633 qxl
->guest_primary
.commands
++;
634 qxl_track_command(qxl
, ext
);
635 qxl_log_command(qxl
, "cmd", ext
);
636 trace_qxl_ring_command_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
643 /* called from spice server thread context only */
644 static int interface_req_cmd_notification(QXLInstance
*sin
)
646 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
649 trace_qxl_ring_command_req_notification(qxl
->id
);
651 case QXL_MODE_COMPAT
:
652 case QXL_MODE_NATIVE
:
653 case QXL_MODE_UNDEFINED
:
654 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
655 qxl_ring_set_dirty(qxl
);
664 /* called from spice server thread context only */
665 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
667 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
671 #define QXL_FREE_BUNCH_SIZE 32
673 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
674 /* ring full -- can't push */
677 if (!flush
&& d
->oom_running
) {
678 /* collect everything from oom handler before pushing */
681 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
682 /* collect a bit more before pushing */
686 SPICE_RING_PUSH(ring
, notify
);
687 trace_qxl_ring_res_push(d
->id
, qxl_mode_to_string(d
->mode
),
688 d
->guest_surfaces
.count
, d
->num_free_res
,
689 d
->last_release
, notify
? "yes" : "no");
690 trace_qxl_ring_res_push_rest(d
->id
, ring
->prod
- ring
->cons
,
691 ring
->num_items
, ring
->prod
, ring
->cons
);
693 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
695 SPICE_RING_PROD_ITEM(d
, ring
, item
);
701 d
->last_release
= NULL
;
702 qxl_ring_set_dirty(d
);
705 /* called from spice server thread context only */
706 static void interface_release_resource(QXLInstance
*sin
,
707 struct QXLReleaseInfoExt ext
)
709 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
710 QXLReleaseRing
*ring
;
713 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
714 /* host group -> vga mode update request */
715 qemu_spice_destroy_update(&qxl
->ssd
, (void *)(intptr_t)ext
.info
->id
);
720 * ext->info points into guest-visible memory
721 * pci bar 0, $command.release_info
723 ring
= &qxl
->ram
->release_ring
;
724 SPICE_RING_PROD_ITEM(qxl
, ring
, item
);
729 /* stick head into the ring */
732 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
734 qxl_ring_set_dirty(qxl
);
736 /* append item to the list */
737 qxl
->last_release
->next
= ext
.info
->id
;
738 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
740 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
742 qxl
->last_release
= ext
.info
;
744 trace_qxl_ring_res_put(qxl
->id
, qxl
->num_free_res
);
745 qxl_push_free_res(qxl
, 0);
748 /* called from spice server thread context only */
749 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
751 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
756 trace_qxl_ring_cursor_check(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
759 case QXL_MODE_COMPAT
:
760 case QXL_MODE_NATIVE
:
761 case QXL_MODE_UNDEFINED
:
762 ring
= &qxl
->ram
->cursor_ring
;
763 if (SPICE_RING_IS_EMPTY(ring
)) {
766 SPICE_RING_CONS_ITEM(qxl
, ring
, cmd
);
771 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
772 ext
->flags
= qxl
->cmdflags
;
773 SPICE_RING_POP(ring
, notify
);
774 qxl_ring_set_dirty(qxl
);
776 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
778 qxl
->guest_primary
.commands
++;
779 qxl_track_command(qxl
, ext
);
780 qxl_log_command(qxl
, "csr", ext
);
782 qxl_render_cursor(qxl
, ext
);
784 trace_qxl_ring_cursor_get(qxl
->id
, qxl_mode_to_string(qxl
->mode
));
791 /* called from spice server thread context only */
792 static int interface_req_cursor_notification(QXLInstance
*sin
)
794 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
797 trace_qxl_ring_cursor_req_notification(qxl
->id
);
799 case QXL_MODE_COMPAT
:
800 case QXL_MODE_NATIVE
:
801 case QXL_MODE_UNDEFINED
:
802 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
803 qxl_ring_set_dirty(qxl
);
812 /* called from spice server thread context */
813 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
816 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
817 * use by xf86-video-qxl and is defined out in the qxl windows driver.
818 * Probably was at some earlier version that is prior to git start (2009),
819 * and is still guest trigerrable.
821 fprintf(stderr
, "%s: deprecated\n", __func__
);
824 /* called from spice server thread context only */
825 static int interface_flush_resources(QXLInstance
*sin
)
827 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
830 ret
= qxl
->num_free_res
;
832 qxl_push_free_res(qxl
, 1);
837 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
839 /* called from spice server thread context only */
840 static void interface_async_complete_io(PCIQXLDevice
*qxl
, QXLCookie
*cookie
)
842 uint32_t current_async
;
844 qemu_mutex_lock(&qxl
->async_lock
);
845 current_async
= qxl
->current_async
;
846 qxl
->current_async
= QXL_UNDEFINED_IO
;
847 qemu_mutex_unlock(&qxl
->async_lock
);
849 trace_qxl_interface_async_complete_io(qxl
->id
, current_async
, cookie
);
851 fprintf(stderr
, "qxl: %s: error, cookie is NULL\n", __func__
);
854 if (cookie
&& current_async
!= cookie
->io
) {
856 "qxl: %s: error: current_async = %d != %"
857 PRId64
" = cookie->io\n", __func__
, current_async
, cookie
->io
);
859 switch (current_async
) {
860 case QXL_IO_MEMSLOT_ADD_ASYNC
:
861 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
862 case QXL_IO_UPDATE_AREA_ASYNC
:
863 case QXL_IO_FLUSH_SURFACES_ASYNC
:
864 case QXL_IO_MONITORS_CONFIG_ASYNC
:
866 case QXL_IO_CREATE_PRIMARY_ASYNC
:
867 qxl_create_guest_primary_complete(qxl
);
869 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
870 qxl_spice_destroy_surfaces_complete(qxl
);
872 case QXL_IO_DESTROY_SURFACE_ASYNC
:
873 qxl_spice_destroy_surface_wait_complete(qxl
, cookie
->u
.surface_id
);
876 fprintf(stderr
, "qxl: %s: unexpected current_async %d\n", __func__
,
879 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
882 /* called from spice server thread context only */
883 static void interface_update_area_complete(QXLInstance
*sin
,
885 QXLRect
*dirty
, uint32_t num_updated_rects
)
887 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
891 qemu_mutex_lock(&qxl
->ssd
.lock
);
892 if (surface_id
!= 0 || !qxl
->render_update_cookie_num
) {
893 qemu_mutex_unlock(&qxl
->ssd
.lock
);
896 trace_qxl_interface_update_area_complete(qxl
->id
, surface_id
, dirty
->left
,
897 dirty
->right
, dirty
->top
, dirty
->bottom
);
898 trace_qxl_interface_update_area_complete_rest(qxl
->id
, num_updated_rects
);
899 if (qxl
->num_dirty_rects
+ num_updated_rects
> QXL_NUM_DIRTY_RECTS
) {
901 * overflow - treat this as a full update. Not expected to be common.
903 trace_qxl_interface_update_area_complete_overflow(qxl
->id
,
904 QXL_NUM_DIRTY_RECTS
);
905 qxl
->guest_primary
.resized
= 1;
907 if (qxl
->guest_primary
.resized
) {
909 * Don't bother copying or scheduling the bh since we will flip
910 * the whole area anyway on completion of the update_area async call
912 qemu_mutex_unlock(&qxl
->ssd
.lock
);
915 qxl_i
= qxl
->num_dirty_rects
;
916 for (i
= 0; i
< num_updated_rects
; i
++) {
917 qxl
->dirty
[qxl_i
++] = dirty
[i
];
919 qxl
->num_dirty_rects
+= num_updated_rects
;
920 trace_qxl_interface_update_area_complete_schedule_bh(qxl
->id
,
921 qxl
->num_dirty_rects
);
922 qemu_bh_schedule(qxl
->update_area_bh
);
923 qemu_mutex_unlock(&qxl
->ssd
.lock
);
926 /* called from spice server thread context only */
927 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie_token
)
929 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
930 QXLCookie
*cookie
= (QXLCookie
*)(uintptr_t)cookie_token
;
932 switch (cookie
->type
) {
933 case QXL_COOKIE_TYPE_IO
:
934 interface_async_complete_io(qxl
, cookie
);
937 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA
:
938 qxl_render_update_area_done(qxl
, cookie
);
940 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG
:
943 fprintf(stderr
, "qxl: %s: unexpected cookie type %d\n",
944 __func__
, cookie
->type
);
949 #if SPICE_SERVER_VERSION >= 0x000b04
951 /* called from spice server thread context only */
952 static void interface_set_client_capabilities(QXLInstance
*sin
,
953 uint8_t client_present
,
956 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
958 if (runstate_check(RUN_STATE_INMIGRATE
) ||
959 runstate_check(RUN_STATE_POSTMIGRATE
)) {
963 qxl
->shadow_rom
.client_present
= client_present
;
964 memcpy(qxl
->shadow_rom
.client_capabilities
, caps
, sizeof(caps
));
965 qxl
->rom
->client_present
= client_present
;
966 memcpy(qxl
->rom
->client_capabilities
, caps
, sizeof(caps
));
967 qxl_rom_set_dirty(qxl
);
969 qxl_send_events(qxl
, QXL_INTERRUPT_CLIENT
);
974 static const QXLInterface qxl_interface
= {
975 .base
.type
= SPICE_INTERFACE_QXL
,
976 .base
.description
= "qxl gpu",
977 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
978 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
980 .attache_worker
= interface_attach_worker
,
981 .set_compression_level
= interface_set_compression_level
,
982 .set_mm_time
= interface_set_mm_time
,
983 .get_init_info
= interface_get_init_info
,
985 /* the callbacks below are called from spice server thread context */
986 .get_command
= interface_get_command
,
987 .req_cmd_notification
= interface_req_cmd_notification
,
988 .release_resource
= interface_release_resource
,
989 .get_cursor_command
= interface_get_cursor_command
,
990 .req_cursor_notification
= interface_req_cursor_notification
,
991 .notify_update
= interface_notify_update
,
992 .flush_resources
= interface_flush_resources
,
993 .async_complete
= interface_async_complete
,
994 .update_area_complete
= interface_update_area_complete
,
995 #if SPICE_SERVER_VERSION >= 0x000b04
996 .set_client_capabilities
= interface_set_client_capabilities
,
1000 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
1002 if (d
->mode
== QXL_MODE_VGA
) {
1005 trace_qxl_enter_vga_mode(d
->id
);
1006 qemu_spice_create_host_primary(&d
->ssd
);
1007 d
->mode
= QXL_MODE_VGA
;
1008 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1009 vga_dirty_log_start(&d
->vga
);
1012 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
1014 if (d
->mode
!= QXL_MODE_VGA
) {
1017 trace_qxl_exit_vga_mode(d
->id
);
1018 vga_dirty_log_stop(&d
->vga
);
1019 qxl_destroy_primary(d
, QXL_SYNC
);
1022 static void qxl_update_irq(PCIQXLDevice
*d
)
1024 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
1025 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
1026 int level
= !!(pending
& mask
);
1027 qemu_set_irq(d
->pci
.irq
[0], level
);
1028 qxl_ring_set_dirty(d
);
1031 static void qxl_check_state(PCIQXLDevice
*d
)
1033 QXLRam
*ram
= d
->ram
;
1034 int spice_display_running
= qemu_spice_display_is_running(&d
->ssd
);
1036 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
1037 assert(!spice_display_running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
1040 static void qxl_reset_state(PCIQXLDevice
*d
)
1042 QXLRom
*rom
= d
->rom
;
1045 d
->shadow_rom
.update_id
= cpu_to_le32(0);
1046 *rom
= d
->shadow_rom
;
1047 qxl_rom_set_dirty(d
);
1049 d
->num_free_res
= 0;
1050 d
->last_release
= NULL
;
1051 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
1054 static void qxl_soft_reset(PCIQXLDevice
*d
)
1056 trace_qxl_soft_reset(d
->id
);
1058 qxl_clear_guest_bug(d
);
1059 d
->current_async
= QXL_UNDEFINED_IO
;
1062 qxl_enter_vga_mode(d
);
1064 d
->mode
= QXL_MODE_UNDEFINED
;
1068 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
1070 trace_qxl_hard_reset(d
->id
, loadvm
);
1072 qxl_spice_reset_cursor(d
);
1073 qxl_spice_reset_image_cache(d
);
1074 qxl_reset_surfaces(d
);
1075 qxl_reset_memslots(d
);
1077 /* pre loadvm reset must not touch QXLRam. This lives in
1078 * device memory, is migrated together with RAM and thus
1079 * already loaded at this point */
1083 qemu_spice_create_host_memslot(&d
->ssd
);
1087 static void qxl_reset_handler(DeviceState
*dev
)
1089 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
1091 qxl_hard_reset(d
, 0);
1094 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1096 VGACommonState
*vga
= opaque
;
1097 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
1099 trace_qxl_io_write_vga(qxl
->id
, qxl_mode_to_string(qxl
->mode
), addr
, val
);
1100 if (qxl
->mode
!= QXL_MODE_VGA
) {
1101 qxl_destroy_primary(qxl
, QXL_SYNC
);
1102 qxl_soft_reset(qxl
);
1104 vga_ioport_write(opaque
, addr
, val
);
1107 static const MemoryRegionPortio qxl_vga_portio_list
[] = {
1108 { 0x04, 2, 1, .read
= vga_ioport_read
,
1109 .write
= qxl_vga_ioport_write
}, /* 3b4 */
1110 { 0x0a, 1, 1, .read
= vga_ioport_read
,
1111 .write
= qxl_vga_ioport_write
}, /* 3ba */
1112 { 0x10, 16, 1, .read
= vga_ioport_read
,
1113 .write
= qxl_vga_ioport_write
}, /* 3c0 */
1114 { 0x24, 2, 1, .read
= vga_ioport_read
,
1115 .write
= qxl_vga_ioport_write
}, /* 3d4 */
1116 { 0x2a, 1, 1, .read
= vga_ioport_read
,
1117 .write
= qxl_vga_ioport_write
}, /* 3da */
1118 PORTIO_END_OF_LIST(),
1121 static int qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
1124 static const int regions
[] = {
1125 QXL_RAM_RANGE_INDEX
,
1126 QXL_VRAM_RANGE_INDEX
,
1127 QXL_VRAM64_RANGE_INDEX
,
1129 uint64_t guest_start
;
1134 intptr_t virt_start
;
1135 QXLDevMemSlot memslot
;
1138 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
1139 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
1141 trace_qxl_memslot_add_guest(d
->id
, slot_id
, guest_start
, guest_end
);
1143 if (slot_id
>= NUM_MEMSLOTS
) {
1144 qxl_set_guest_bug(d
, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__
,
1145 slot_id
, NUM_MEMSLOTS
);
1148 if (guest_start
> guest_end
) {
1149 qxl_set_guest_bug(d
, "%s: guest_start > guest_end 0x%" PRIx64
1150 " > 0x%" PRIx64
, __func__
, guest_start
, guest_end
);
1154 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
1155 pci_region
= regions
[i
];
1156 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
1157 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
1159 if (pci_start
== -1) {
1162 /* start address in range ? */
1163 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
1166 /* end address in range ? */
1167 if (guest_end
> pci_end
) {
1173 if (i
== ARRAY_SIZE(regions
)) {
1174 qxl_set_guest_bug(d
, "%s: finished loop without match", __func__
);
1178 switch (pci_region
) {
1179 case QXL_RAM_RANGE_INDEX
:
1180 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
1182 case QXL_VRAM_RANGE_INDEX
:
1183 case 4 /* vram 64bit */:
1184 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
1187 /* should not happen */
1188 qxl_set_guest_bug(d
, "%s: pci_region = %d", __func__
, pci_region
);
1192 memslot
.slot_id
= slot_id
;
1193 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
1194 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
1195 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
1196 memslot
.addr_delta
= memslot
.virt_start
- delta
;
1197 memslot
.generation
= d
->rom
->slot_generation
= 0;
1198 qxl_rom_set_dirty(d
);
1200 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
1201 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
1202 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
1203 d
->guest_slots
[slot_id
].delta
= delta
;
1204 d
->guest_slots
[slot_id
].active
= 1;
1208 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
1210 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
1211 d
->guest_slots
[slot_id
].active
= 0;
1214 static void qxl_reset_memslots(PCIQXLDevice
*d
)
1216 qxl_spice_reset_memslots(d
);
1217 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
1220 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1222 trace_qxl_reset_surfaces(d
->id
);
1223 d
->mode
= QXL_MODE_UNDEFINED
;
1224 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1227 /* can be also called from spice server thread context */
1228 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1230 uint64_t phys
= le64_to_cpu(pqxl
);
1231 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1232 uint64_t offset
= phys
& 0xffffffffffff;
1235 case MEMSLOT_GROUP_HOST
:
1236 return (void *)(intptr_t)offset
;
1237 case MEMSLOT_GROUP_GUEST
:
1238 if (slot
>= NUM_MEMSLOTS
) {
1239 qxl_set_guest_bug(qxl
, "slot too large %d >= %d", slot
,
1243 if (!qxl
->guest_slots
[slot
].active
) {
1244 qxl_set_guest_bug(qxl
, "inactive slot %d\n", slot
);
1247 if (offset
< qxl
->guest_slots
[slot
].delta
) {
1248 qxl_set_guest_bug(qxl
,
1249 "slot %d offset %"PRIu64
" < delta %"PRIu64
"\n",
1250 slot
, offset
, qxl
->guest_slots
[slot
].delta
);
1253 offset
-= qxl
->guest_slots
[slot
].delta
;
1254 if (offset
> qxl
->guest_slots
[slot
].size
) {
1255 qxl_set_guest_bug(qxl
,
1256 "slot %d offset %"PRIu64
" > size %"PRIu64
"\n",
1257 slot
, offset
, qxl
->guest_slots
[slot
].size
);
1260 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1265 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1267 /* for local rendering */
1268 qxl_render_resize(qxl
);
1271 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1274 QXLDevSurfaceCreate surface
;
1275 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1277 int requested_height
= le32_to_cpu(sc
->height
);
1278 int requested_stride
= le32_to_cpu(sc
->stride
);
1280 size
= abs(requested_stride
) * requested_height
;
1281 if (size
> qxl
->vgamem_size
) {
1282 qxl_set_guest_bug(qxl
, "%s: requested primary larger then framebuffer"
1287 if (qxl
->mode
== QXL_MODE_NATIVE
) {
1288 qxl_set_guest_bug(qxl
, "%s: nop since already in QXL_MODE_NATIVE",
1291 qxl_exit_vga_mode(qxl
);
1293 surface
.format
= le32_to_cpu(sc
->format
);
1294 surface
.height
= le32_to_cpu(sc
->height
);
1295 surface
.mem
= le64_to_cpu(sc
->mem
);
1296 surface
.position
= le32_to_cpu(sc
->position
);
1297 surface
.stride
= le32_to_cpu(sc
->stride
);
1298 surface
.width
= le32_to_cpu(sc
->width
);
1299 surface
.type
= le32_to_cpu(sc
->type
);
1300 surface
.flags
= le32_to_cpu(sc
->flags
);
1301 trace_qxl_create_guest_primary(qxl
->id
, sc
->width
, sc
->height
, sc
->mem
,
1302 sc
->format
, sc
->position
);
1303 trace_qxl_create_guest_primary_rest(qxl
->id
, sc
->stride
, sc
->type
,
1306 surface
.mouse_mode
= true;
1307 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1309 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1312 qxl
->mode
= QXL_MODE_NATIVE
;
1314 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1316 if (async
== QXL_SYNC
) {
1317 qxl_create_guest_primary_complete(qxl
);
1321 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1322 * done (in QXL_SYNC case), 0 otherwise. */
1323 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1325 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1328 trace_qxl_destroy_primary(d
->id
);
1329 d
->mode
= QXL_MODE_UNDEFINED
;
1330 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1331 qxl_spice_reset_cursor(d
);
1335 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1337 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1338 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1339 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1340 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1345 QXLSurfaceCreate surface
= {
1346 .width
= mode
->x_res
,
1347 .height
= mode
->y_res
,
1348 .stride
= -mode
->x_res
* 4,
1349 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1350 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1352 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1355 trace_qxl_set_mode(d
->id
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
,
1358 qxl_hard_reset(d
, 0);
1361 d
->guest_slots
[0].slot
= slot
;
1362 assert(qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
) == 0);
1364 d
->guest_primary
.surface
= surface
;
1365 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1367 d
->mode
= QXL_MODE_COMPAT
;
1368 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1369 if (mode
->bits
== 16) {
1370 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1372 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1373 d
->rom
->mode
= cpu_to_le32(modenr
);
1374 qxl_rom_set_dirty(d
);
1377 static void ioport_write(void *opaque
, target_phys_addr_t addr
,
1378 uint64_t val
, unsigned size
)
1380 PCIQXLDevice
*d
= opaque
;
1381 uint32_t io_port
= addr
;
1382 qxl_async_io async
= QXL_SYNC
;
1383 uint32_t orig_io_port
= io_port
;
1385 if (d
->guest_bug
&& !io_port
== QXL_IO_RESET
) {
1389 if (d
->revision
<= QXL_REVISION_STABLE_V10
&&
1390 io_port
>= QXL_IO_FLUSH_SURFACES_ASYNC
) {
1391 qxl_set_guest_bug(d
, "unsupported io %d for revision %d\n",
1392 io_port
, d
->revision
);
1398 case QXL_IO_SET_MODE
:
1399 case QXL_IO_MEMSLOT_ADD
:
1400 case QXL_IO_MEMSLOT_DEL
:
1401 case QXL_IO_CREATE_PRIMARY
:
1402 case QXL_IO_UPDATE_IRQ
:
1404 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1405 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1408 if (d
->mode
!= QXL_MODE_VGA
) {
1411 trace_qxl_io_unexpected_vga_mode(d
->id
,
1412 addr
, val
, io_port_to_string(io_port
));
1413 /* be nice to buggy guest drivers */
1414 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1415 io_port
< QXL_IO_RANGE_SIZE
) {
1416 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1421 /* we change the io_port to avoid ifdeffery in the main switch */
1422 orig_io_port
= io_port
;
1424 case QXL_IO_UPDATE_AREA_ASYNC
:
1425 io_port
= QXL_IO_UPDATE_AREA
;
1427 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1428 io_port
= QXL_IO_MEMSLOT_ADD
;
1430 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1431 io_port
= QXL_IO_CREATE_PRIMARY
;
1433 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1434 io_port
= QXL_IO_DESTROY_PRIMARY
;
1436 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1437 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1439 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1440 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1442 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1443 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1446 qemu_mutex_lock(&d
->async_lock
);
1447 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1448 qxl_set_guest_bug(d
, "%d async started before last (%d) complete",
1449 io_port
, d
->current_async
);
1450 qemu_mutex_unlock(&d
->async_lock
);
1453 d
->current_async
= orig_io_port
;
1454 qemu_mutex_unlock(&d
->async_lock
);
1459 trace_qxl_io_write(d
->id
, qxl_mode_to_string(d
->mode
), addr
, val
, size
,
1463 case QXL_IO_UPDATE_AREA
:
1465 QXLCookie
*cookie
= NULL
;
1466 QXLRect update
= d
->ram
->update_area
;
1468 if (d
->ram
->update_surface
> d
->ssd
.num_surfaces
) {
1469 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1470 d
->ram
->update_surface
);
1473 if (update
.left
>= update
.right
|| update
.top
>= update
.bottom
) {
1474 qxl_set_guest_bug(d
,
1475 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1476 update
.left
, update
.top
, update
.right
, update
.bottom
);
1480 if (update
.left
< 0 || update
.top
< 0 || update
.left
>= update
.right
||
1481 update
.top
>= update
.bottom
) {
1482 qxl_set_guest_bug(d
, "QXL_IO_UPDATE_AREA: "
1483 "invalid area(%d,%d,%d,%d)\n", update
.left
,
1484 update
.right
, update
.top
, update
.bottom
);
1487 if (async
== QXL_ASYNC
) {
1488 cookie
= qxl_cookie_new(QXL_COOKIE_TYPE_IO
,
1489 QXL_IO_UPDATE_AREA_ASYNC
);
1490 cookie
->u
.area
= update
;
1492 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1493 cookie
? &cookie
->u
.area
: &update
,
1494 NULL
, 0, 0, async
, cookie
);
1497 case QXL_IO_NOTIFY_CMD
:
1498 qemu_spice_wakeup(&d
->ssd
);
1500 case QXL_IO_NOTIFY_CURSOR
:
1501 qemu_spice_wakeup(&d
->ssd
);
1503 case QXL_IO_UPDATE_IRQ
:
1506 case QXL_IO_NOTIFY_OOM
:
1507 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1514 case QXL_IO_SET_MODE
:
1515 qxl_set_mode(d
, val
, 0);
1518 trace_qxl_io_log(d
->id
, d
->ram
->log_buf
);
1519 if (d
->guestdebug
) {
1520 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1521 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1525 qxl_hard_reset(d
, 0);
1527 case QXL_IO_MEMSLOT_ADD
:
1528 if (val
>= NUM_MEMSLOTS
) {
1529 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1532 if (d
->guest_slots
[val
].active
) {
1533 qxl_set_guest_bug(d
,
1534 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1537 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1538 qxl_add_memslot(d
, val
, 0, async
);
1540 case QXL_IO_MEMSLOT_DEL
:
1541 if (val
>= NUM_MEMSLOTS
) {
1542 qxl_set_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1545 qxl_del_memslot(d
, val
);
1547 case QXL_IO_CREATE_PRIMARY
:
1549 qxl_set_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1553 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1554 qxl_create_guest_primary(d
, 0, async
);
1556 case QXL_IO_DESTROY_PRIMARY
:
1558 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1562 if (!qxl_destroy_primary(d
, async
)) {
1563 trace_qxl_io_destroy_primary_ignored(d
->id
,
1564 qxl_mode_to_string(d
->mode
));
1568 case QXL_IO_DESTROY_SURFACE_WAIT
:
1569 if (val
>= d
->ssd
.num_surfaces
) {
1570 qxl_set_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1571 "%" PRIu64
" >= NUM_SURFACES", async
, val
);
1574 qxl_spice_destroy_surface_wait(d
, val
, async
);
1576 case QXL_IO_FLUSH_RELEASE
: {
1577 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1578 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1580 "ERROR: no flush, full release ring [p%d,%dc]\n",
1581 ring
->prod
, ring
->cons
);
1583 qxl_push_free_res(d
, 1 /* flush */);
1586 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1587 qxl_spice_flush_surfaces_async(d
);
1589 case QXL_IO_DESTROY_ALL_SURFACES
:
1590 d
->mode
= QXL_MODE_UNDEFINED
;
1591 qxl_spice_destroy_surfaces(d
, async
);
1593 case QXL_IO_MONITORS_CONFIG_ASYNC
:
1594 qxl_spice_monitors_config_async(d
, 0);
1597 qxl_set_guest_bug(d
, "%s: unexpected ioport=0x%x\n", __func__
, io_port
);
1602 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1603 qemu_mutex_lock(&d
->async_lock
);
1604 d
->current_async
= QXL_UNDEFINED_IO
;
1605 qemu_mutex_unlock(&d
->async_lock
);
1609 static uint64_t ioport_read(void *opaque
, target_phys_addr_t addr
,
1612 PCIQXLDevice
*qxl
= opaque
;
1614 trace_qxl_io_read_unexpected(qxl
->id
);
1618 static const MemoryRegionOps qxl_io_ops
= {
1619 .read
= ioport_read
,
1620 .write
= ioport_write
,
1622 .min_access_size
= 1,
1623 .max_access_size
= 1,
1627 static void pipe_read(void *opaque
)
1629 PCIQXLDevice
*d
= opaque
;
1634 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1635 } while (len
== sizeof(dummy
));
1639 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1641 uint32_t old_pending
;
1642 uint32_t le_events
= cpu_to_le32(events
);
1644 trace_qxl_send_events(d
->id
, events
);
1645 assert(qemu_spice_display_is_running(&d
->ssd
));
1646 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1647 if ((old_pending
& le_events
) == le_events
) {
1650 if (qemu_thread_is_self(&d
->main
)) {
1653 if (write(d
->pipe
[1], d
, 1) != 1) {
1654 dprint(d
, 1, "%s: write to pipe failed\n", __func__
);
1659 static void init_pipe_signaling(PCIQXLDevice
*d
)
1661 if (pipe(d
->pipe
) < 0) {
1662 fprintf(stderr
, "%s:%s: qxl pipe creation failed\n",
1663 __FILE__
, __func__
);
1666 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1667 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1668 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1670 qemu_thread_get_self(&d
->main
);
1671 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1674 /* graphics console */
1676 static void qxl_hw_update(void *opaque
)
1678 PCIQXLDevice
*qxl
= opaque
;
1679 VGACommonState
*vga
= &qxl
->vga
;
1681 switch (qxl
->mode
) {
1685 case QXL_MODE_COMPAT
:
1686 case QXL_MODE_NATIVE
:
1687 qxl_render_update(qxl
);
1694 static void qxl_hw_invalidate(void *opaque
)
1696 PCIQXLDevice
*qxl
= opaque
;
1697 VGACommonState
*vga
= &qxl
->vga
;
1699 vga
->invalidate(vga
);
1702 static void qxl_hw_screen_dump(void *opaque
, const char *filename
, bool cswitch
,
1705 PCIQXLDevice
*qxl
= opaque
;
1706 VGACommonState
*vga
= &qxl
->vga
;
1708 switch (qxl
->mode
) {
1709 case QXL_MODE_COMPAT
:
1710 case QXL_MODE_NATIVE
:
1711 qxl_render_update(qxl
);
1712 ppm_save(filename
, qxl
->ssd
.ds
->surface
, errp
);
1715 vga
->screen_dump(vga
, filename
, cswitch
, errp
);
1722 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1724 PCIQXLDevice
*qxl
= opaque
;
1725 VGACommonState
*vga
= &qxl
->vga
;
1727 if (qxl
->mode
== QXL_MODE_VGA
) {
1728 vga
->text_update(vga
, chardata
);
1733 static void qxl_dirty_surfaces(PCIQXLDevice
*qxl
)
1735 intptr_t vram_start
;
1738 if (qxl
->mode
!= QXL_MODE_NATIVE
&& qxl
->mode
!= QXL_MODE_COMPAT
) {
1742 /* dirty the primary surface */
1743 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1744 qxl
->shadow_rom
.surface0_area_size
);
1746 vram_start
= (intptr_t)memory_region_get_ram_ptr(&qxl
->vram_bar
);
1748 /* dirty the off-screen surfaces */
1749 for (i
= 0; i
< qxl
->ssd
.num_surfaces
; i
++) {
1751 intptr_t surface_offset
;
1754 if (qxl
->guest_surfaces
.cmds
[i
] == 0) {
1758 cmd
= qxl_phys2virt(qxl
, qxl
->guest_surfaces
.cmds
[i
],
1759 MEMSLOT_GROUP_GUEST
);
1761 assert(cmd
->type
== QXL_SURFACE_CMD_CREATE
);
1762 surface_offset
= (intptr_t)qxl_phys2virt(qxl
,
1763 cmd
->u
.surface_create
.data
,
1764 MEMSLOT_GROUP_GUEST
);
1765 assert(surface_offset
);
1766 surface_offset
-= vram_start
;
1767 surface_size
= cmd
->u
.surface_create
.height
*
1768 abs(cmd
->u
.surface_create
.stride
);
1769 trace_qxl_surfaces_dirty(qxl
->id
, i
, (int)surface_offset
, surface_size
);
1770 qxl_set_dirty(&qxl
->vram_bar
, surface_offset
, surface_size
);
1774 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1777 PCIQXLDevice
*qxl
= opaque
;
1778 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, state
);
1782 * if qxl_send_events was called from spice server context before
1783 * migration ended, qxl_update_irq for these events might not have been
1786 qxl_update_irq(qxl
);
1788 /* make sure surfaces are saved before migration */
1789 qxl_dirty_surfaces(qxl
);
1793 /* display change listener */
1795 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1797 if (qxl0
->mode
== QXL_MODE_VGA
) {
1798 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1802 static void display_resize(struct DisplayState
*ds
)
1804 if (qxl0
->mode
== QXL_MODE_VGA
) {
1805 qemu_spice_display_resize(&qxl0
->ssd
);
1809 static void display_refresh(struct DisplayState
*ds
)
1811 if (qxl0
->mode
== QXL_MODE_VGA
) {
1812 qemu_spice_display_refresh(&qxl0
->ssd
);
1814 qemu_mutex_lock(&qxl0
->ssd
.lock
);
1815 qemu_spice_cursor_refresh_unlocked(&qxl0
->ssd
);
1816 qemu_mutex_unlock(&qxl0
->ssd
.lock
);
1820 static DisplayChangeListener display_listener
= {
1821 .dpy_update
= display_update
,
1822 .dpy_resize
= display_resize
,
1823 .dpy_refresh
= display_refresh
,
1826 static void qxl_init_ramsize(PCIQXLDevice
*qxl
)
1828 /* vga mode framebuffer / primary surface (bar 0, first part) */
1829 if (qxl
->vgamem_size_mb
< 8) {
1830 qxl
->vgamem_size_mb
= 8;
1832 qxl
->vgamem_size
= qxl
->vgamem_size_mb
* 1024 * 1024;
1834 /* vga ram (bar 0, total) */
1835 if (qxl
->ram_size_mb
!= -1) {
1836 qxl
->vga
.vram_size
= qxl
->ram_size_mb
* 1024 * 1024;
1838 if (qxl
->vga
.vram_size
< qxl
->vgamem_size
* 2) {
1839 qxl
->vga
.vram_size
= qxl
->vgamem_size
* 2;
1842 /* vram32 (surfaces, 32bit, bar 1) */
1843 if (qxl
->vram32_size_mb
!= -1) {
1844 qxl
->vram32_size
= qxl
->vram32_size_mb
* 1024 * 1024;
1846 if (qxl
->vram32_size
< 4096) {
1847 qxl
->vram32_size
= 4096;
1850 /* vram (surfaces, 64bit, bar 4+5) */
1851 if (qxl
->vram_size_mb
!= -1) {
1852 qxl
->vram_size
= qxl
->vram_size_mb
* 1024 * 1024;
1854 if (qxl
->vram_size
< qxl
->vram32_size
) {
1855 qxl
->vram_size
= qxl
->vram32_size
;
1858 if (qxl
->revision
== 1) {
1859 qxl
->vram32_size
= 4096;
1860 qxl
->vram_size
= 4096;
1862 qxl
->vgamem_size
= msb_mask(qxl
->vgamem_size
* 2 - 1);
1863 qxl
->vga
.vram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1864 qxl
->vram32_size
= msb_mask(qxl
->vram32_size
* 2 - 1);
1865 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1868 static int qxl_init_common(PCIQXLDevice
*qxl
)
1870 uint8_t* config
= qxl
->pci
.config
;
1871 uint32_t pci_device_rev
;
1874 qxl
->mode
= QXL_MODE_UNDEFINED
;
1875 qxl
->generation
= 1;
1876 qxl
->num_memslots
= NUM_MEMSLOTS
;
1877 qemu_mutex_init(&qxl
->track_lock
);
1878 qemu_mutex_init(&qxl
->async_lock
);
1879 qxl
->current_async
= QXL_UNDEFINED_IO
;
1882 switch (qxl
->revision
) {
1883 case 1: /* spice 0.4 -- qxl-1 */
1884 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1887 case 2: /* spice 0.6 -- qxl-2 */
1888 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1892 pci_device_rev
= QXL_REVISION_STABLE_V10
;
1893 io_size
= 32; /* PCI region size must be pow2 */
1895 /* 0x000b01 == 0.11.1 */
1896 #if SPICE_SERVER_VERSION >= 0x000b01 && \
1897 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
1899 pci_device_rev
= QXL_REVISION_STABLE_V12
;
1900 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1904 error_report("Invalid revision %d for qxl device (max %d)",
1905 qxl
->revision
, QXL_DEFAULT_REVISION
);
1909 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1910 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1912 qxl
->rom_size
= qxl_rom_size();
1913 memory_region_init_ram(&qxl
->rom_bar
, "qxl.vrom", qxl
->rom_size
);
1914 vmstate_register_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
);
1918 qxl
->guest_surfaces
.cmds
= g_new0(QXLPHYSICAL
, qxl
->ssd
.num_surfaces
);
1919 memory_region_init_ram(&qxl
->vram_bar
, "qxl.vram", qxl
->vram_size
);
1920 vmstate_register_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
);
1921 memory_region_init_alias(&qxl
->vram32_bar
, "qxl.vram32", &qxl
->vram_bar
,
1922 0, qxl
->vram32_size
);
1924 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1925 "qxl-ioports", io_size
);
1927 vga_dirty_log_start(&qxl
->vga
);
1931 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1932 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1934 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1935 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1937 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1938 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1940 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
1941 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram32_bar
);
1943 if (qxl
->vram32_size
< qxl
->vram_size
) {
1945 * Make the 64bit vram bar show up only in case it is
1946 * configured to be larger than the 32bit vram bar.
1948 pci_register_bar(&qxl
->pci
, QXL_VRAM64_RANGE_INDEX
,
1949 PCI_BASE_ADDRESS_SPACE_MEMORY
|
1950 PCI_BASE_ADDRESS_MEM_TYPE_64
|
1951 PCI_BASE_ADDRESS_MEM_PREFETCH
,
1955 /* print pci bar details */
1956 dprint(qxl
, 1, "ram/%s: %d MB [region 0]\n",
1957 qxl
->id
== 0 ? "pri" : "sec",
1958 qxl
->vga
.vram_size
/ (1024*1024));
1959 dprint(qxl
, 1, "vram/32: %d MB [region 1]\n",
1960 qxl
->vram32_size
/ (1024*1024));
1961 dprint(qxl
, 1, "vram/64: %d MB %s\n",
1962 qxl
->vram_size
/ (1024*1024),
1963 qxl
->vram32_size
< qxl
->vram_size
? "[region 4]" : "[unmapped]");
1965 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1966 qxl
->ssd
.qxl
.id
= qxl
->id
;
1967 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1968 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1970 init_pipe_signaling(qxl
);
1971 qxl_reset_state(qxl
);
1973 qxl
->update_area_bh
= qemu_bh_new(qxl_render_update_area_bh
, qxl
);
1978 static int qxl_init_primary(PCIDevice
*dev
)
1980 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1981 VGACommonState
*vga
= &qxl
->vga
;
1982 PortioList
*qxl_vga_port_list
= g_new(PortioList
, 1);
1985 qxl_init_ramsize(qxl
);
1986 vga
->vram_size_mb
= qxl
->vga
.vram_size
>> 20;
1987 vga_common_init(vga
);
1988 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
1989 portio_list_init(qxl_vga_port_list
, qxl_vga_portio_list
, vga
, "vga");
1990 portio_list_add(qxl_vga_port_list
, pci_address_space_io(dev
), 0x3b0);
1992 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1993 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1994 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1997 register_displaychangelistener(vga
->ds
, &display_listener
);
1999 return qxl_init_common(qxl
);
2002 static int qxl_init_secondary(PCIDevice
*dev
)
2004 static int device_id
= 1;
2005 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
2007 qxl
->id
= device_id
++;
2008 qxl_init_ramsize(qxl
);
2009 memory_region_init_ram(&qxl
->vga
.vram
, "qxl.vgavram", qxl
->vga
.vram_size
);
2010 vmstate_register_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
);
2011 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
2013 return qxl_init_common(qxl
);
2016 static void qxl_pre_save(void *opaque
)
2018 PCIQXLDevice
* d
= opaque
;
2019 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2021 trace_qxl_pre_save(d
->id
);
2022 if (d
->last_release
== NULL
) {
2023 d
->last_release_offset
= 0;
2025 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
2027 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2030 static int qxl_pre_load(void *opaque
)
2032 PCIQXLDevice
* d
= opaque
;
2034 trace_qxl_pre_load(d
->id
);
2035 qxl_hard_reset(d
, 1);
2036 qxl_exit_vga_mode(d
);
2040 static void qxl_create_memslots(PCIQXLDevice
*d
)
2044 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
2045 if (!d
->guest_slots
[i
].active
) {
2048 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
2052 static int qxl_post_load(void *opaque
, int version
)
2054 PCIQXLDevice
* d
= opaque
;
2055 uint8_t *ram_start
= d
->vga
.vram_ptr
;
2056 QXLCommandExt
*cmds
;
2057 int in
, out
, newmode
;
2059 assert(d
->last_release_offset
< d
->vga
.vram_size
);
2060 if (d
->last_release_offset
== 0) {
2061 d
->last_release
= NULL
;
2063 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
2066 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
2068 trace_qxl_post_load(d
->id
, qxl_mode_to_string(d
->mode
));
2070 d
->mode
= QXL_MODE_UNDEFINED
;
2073 case QXL_MODE_UNDEFINED
:
2076 qxl_create_memslots(d
);
2077 qxl_enter_vga_mode(d
);
2079 case QXL_MODE_NATIVE
:
2080 qxl_create_memslots(d
);
2081 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
2083 /* replay surface-create and cursor-set commands */
2084 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (d
->ssd
.num_surfaces
+ 1));
2085 for (in
= 0, out
= 0; in
< d
->ssd
.num_surfaces
; in
++) {
2086 if (d
->guest_surfaces
.cmds
[in
] == 0) {
2089 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
2090 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
2091 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2094 if (d
->guest_cursor
) {
2095 cmds
[out
].cmd
.data
= d
->guest_cursor
;
2096 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
2097 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
2100 qxl_spice_loadvm_commands(d
, cmds
, out
);
2102 if (d
->guest_monitors_config
) {
2103 qxl_spice_monitors_config_async(d
, 1);
2106 case QXL_MODE_COMPAT
:
2107 /* note: no need to call qxl_create_memslots, qxl_set_mode
2108 * creates the mem slot. */
2109 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
2115 #define QXL_SAVE_VERSION 21
2117 static bool qxl_monitors_config_needed(void *opaque
)
2119 PCIQXLDevice
*qxl
= opaque
;
2121 return qxl
->guest_monitors_config
!= 0;
2125 static VMStateDescription qxl_memslot
= {
2126 .name
= "qxl-memslot",
2127 .version_id
= QXL_SAVE_VERSION
,
2128 .minimum_version_id
= QXL_SAVE_VERSION
,
2129 .fields
= (VMStateField
[]) {
2130 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
2131 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
2132 VMSTATE_UINT32(active
, struct guest_slots
),
2133 VMSTATE_END_OF_LIST()
2137 static VMStateDescription qxl_surface
= {
2138 .name
= "qxl-surface",
2139 .version_id
= QXL_SAVE_VERSION
,
2140 .minimum_version_id
= QXL_SAVE_VERSION
,
2141 .fields
= (VMStateField
[]) {
2142 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
2143 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
2144 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
2145 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
2146 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
2147 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
2148 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
2149 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
2150 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
2151 VMSTATE_END_OF_LIST()
2155 static VMStateDescription qxl_vmstate_monitors_config
= {
2156 .name
= "qxl/monitors-config",
2158 .minimum_version_id
= 1,
2159 .fields
= (VMStateField
[]) {
2160 VMSTATE_UINT64(guest_monitors_config
, PCIQXLDevice
),
2161 VMSTATE_END_OF_LIST()
2165 static VMStateDescription qxl_vmstate
= {
2167 .version_id
= QXL_SAVE_VERSION
,
2168 .minimum_version_id
= QXL_SAVE_VERSION
,
2169 .pre_save
= qxl_pre_save
,
2170 .pre_load
= qxl_pre_load
,
2171 .post_load
= qxl_post_load
,
2172 .fields
= (VMStateField
[]) {
2173 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
2174 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
2175 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
2176 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
2177 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
2178 VMSTATE_UINT32(mode
, PCIQXLDevice
),
2179 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
2180 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
2181 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
2182 qxl_memslot
, struct guest_slots
),
2183 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
2184 qxl_surface
, QXLSurfaceCreate
),
2185 VMSTATE_INT32_EQUAL(ssd
.num_surfaces
, PCIQXLDevice
),
2186 VMSTATE_VARRAY_INT32(guest_surfaces
.cmds
, PCIQXLDevice
,
2187 ssd
.num_surfaces
, 0,
2188 vmstate_info_uint64
, uint64_t),
2189 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
2190 VMSTATE_END_OF_LIST()
2192 .subsections
= (VMStateSubsection
[]) {
2194 .vmsd
= &qxl_vmstate_monitors_config
,
2195 .needed
= qxl_monitors_config_needed
,
2202 static Property qxl_properties
[] = {
2203 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
2205 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram32_size
,
2207 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
2208 QXL_DEFAULT_REVISION
),
2209 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
2210 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
2211 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
2212 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice
, ram_size_mb
, -1),
2213 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice
, vram32_size_mb
, -1),
2214 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice
, vram_size_mb
, -1),
2215 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice
, vgamem_size_mb
, 16),
2216 DEFINE_PROP_INT32("surfaces", PCIQXLDevice
, ssd
.num_surfaces
, 1024),
2217 DEFINE_PROP_END_OF_LIST(),
2220 static void qxl_primary_class_init(ObjectClass
*klass
, void *data
)
2222 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2223 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2226 k
->init
= qxl_init_primary
;
2227 k
->romfile
= "vgabios-qxl.bin";
2228 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2229 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2230 k
->class_id
= PCI_CLASS_DISPLAY_VGA
;
2231 dc
->desc
= "Spice QXL GPU (primary, vga compatible)";
2232 dc
->reset
= qxl_reset_handler
;
2233 dc
->vmsd
= &qxl_vmstate
;
2234 dc
->props
= qxl_properties
;
2237 static TypeInfo qxl_primary_info
= {
2239 .parent
= TYPE_PCI_DEVICE
,
2240 .instance_size
= sizeof(PCIQXLDevice
),
2241 .class_init
= qxl_primary_class_init
,
2244 static void qxl_secondary_class_init(ObjectClass
*klass
, void *data
)
2246 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2247 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2249 k
->init
= qxl_init_secondary
;
2250 k
->vendor_id
= REDHAT_PCI_VENDOR_ID
;
2251 k
->device_id
= QXL_DEVICE_ID_STABLE
;
2252 k
->class_id
= PCI_CLASS_DISPLAY_OTHER
;
2253 dc
->desc
= "Spice QXL GPU (secondary)";
2254 dc
->reset
= qxl_reset_handler
;
2255 dc
->vmsd
= &qxl_vmstate
;
2256 dc
->props
= qxl_properties
;
2259 static TypeInfo qxl_secondary_info
= {
2261 .parent
= TYPE_PCI_DEVICE
,
2262 .instance_size
= sizeof(PCIQXLDevice
),
2263 .class_init
= qxl_secondary_class_init
,
2266 static void qxl_register_types(void)
2268 type_register_static(&qxl_primary_info
);
2269 type_register_static(&qxl_secondary_info
);
2272 type_init(qxl_register_types
)