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1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
24 #include "monitor.h"
25 #include "sysemu.h"
26 #include "trace.h"
27
28 #include "qxl.h"
29
30 /*
31 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
32 * such can be changed by the guest, so to avoid a guest trigerrable
33 * abort we just qxl_set_guest_bug and set the return to NULL. Still
34 * it may happen as a result of emulator bug as well.
35 */
36 #undef SPICE_RING_PROD_ITEM
37 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
38 typeof(r) start = r; \
39 typeof(r) end = r + 1; \
40 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
41 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
42 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
43 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
44 "! %p <= %p < %p", (uint8_t *)start, \
45 (uint8_t *)m_item, (uint8_t *)end); \
46 ret = NULL; \
47 } else { \
48 ret = &m_item->el; \
49 } \
50 }
51
52 #undef SPICE_RING_CONS_ITEM
53 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
54 typeof(r) start = r; \
55 typeof(r) end = r + 1; \
56 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
57 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
58 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
59 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
60 "! %p <= %p < %p", (uint8_t *)start, \
61 (uint8_t *)m_item, (uint8_t *)end); \
62 ret = NULL; \
63 } else { \
64 ret = &m_item->el; \
65 } \
66 }
67
68 #undef ALIGN
69 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
70
71 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
72
73 #define QXL_MODE(_x, _y, _b, _o) \
74 { .x_res = _x, \
75 .y_res = _y, \
76 .bits = _b, \
77 .stride = (_x) * (_b) / 8, \
78 .x_mili = PIXEL_SIZE * (_x), \
79 .y_mili = PIXEL_SIZE * (_y), \
80 .orientation = _o, \
81 }
82
83 #define QXL_MODE_16_32(x_res, y_res, orientation) \
84 QXL_MODE(x_res, y_res, 16, orientation), \
85 QXL_MODE(x_res, y_res, 32, orientation)
86
87 #define QXL_MODE_EX(x_res, y_res) \
88 QXL_MODE_16_32(x_res, y_res, 0), \
89 QXL_MODE_16_32(y_res, x_res, 1), \
90 QXL_MODE_16_32(x_res, y_res, 2), \
91 QXL_MODE_16_32(y_res, x_res, 3)
92
93 static QXLMode qxl_modes[] = {
94 QXL_MODE_EX(640, 480),
95 QXL_MODE_EX(800, 480),
96 QXL_MODE_EX(800, 600),
97 QXL_MODE_EX(832, 624),
98 QXL_MODE_EX(960, 640),
99 QXL_MODE_EX(1024, 600),
100 QXL_MODE_EX(1024, 768),
101 QXL_MODE_EX(1152, 864),
102 QXL_MODE_EX(1152, 870),
103 QXL_MODE_EX(1280, 720),
104 QXL_MODE_EX(1280, 760),
105 QXL_MODE_EX(1280, 768),
106 QXL_MODE_EX(1280, 800),
107 QXL_MODE_EX(1280, 960),
108 QXL_MODE_EX(1280, 1024),
109 QXL_MODE_EX(1360, 768),
110 QXL_MODE_EX(1366, 768),
111 QXL_MODE_EX(1400, 1050),
112 QXL_MODE_EX(1440, 900),
113 QXL_MODE_EX(1600, 900),
114 QXL_MODE_EX(1600, 1200),
115 QXL_MODE_EX(1680, 1050),
116 QXL_MODE_EX(1920, 1080),
117 /* these modes need more than 8 MB video memory */
118 QXL_MODE_EX(1920, 1200),
119 QXL_MODE_EX(1920, 1440),
120 QXL_MODE_EX(2048, 1536),
121 QXL_MODE_EX(2560, 1440),
122 QXL_MODE_EX(2560, 1600),
123 /* these modes need more than 16 MB video memory */
124 QXL_MODE_EX(2560, 2048),
125 QXL_MODE_EX(2800, 2100),
126 QXL_MODE_EX(3200, 2400),
127 };
128
129 static PCIQXLDevice *qxl0;
130
131 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
132 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
133 static void qxl_reset_memslots(PCIQXLDevice *d);
134 static void qxl_reset_surfaces(PCIQXLDevice *d);
135 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
136
137 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
138 {
139 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
140 qxl->guest_bug = 1;
141 if (qxl->guestdebug) {
142 va_list ap;
143 va_start(ap, msg);
144 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
145 vfprintf(stderr, msg, ap);
146 fprintf(stderr, "\n");
147 va_end(ap);
148 }
149 }
150
151 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
152 {
153 qxl->guest_bug = 0;
154 }
155
156 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
157 struct QXLRect *area, struct QXLRect *dirty_rects,
158 uint32_t num_dirty_rects,
159 uint32_t clear_dirty_region,
160 qxl_async_io async, struct QXLCookie *cookie)
161 {
162 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
163 area->top, area->bottom);
164 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
165 clear_dirty_region);
166 if (async == QXL_SYNC) {
167 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
168 dirty_rects, num_dirty_rects, clear_dirty_region);
169 } else {
170 assert(cookie != NULL);
171 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
172 clear_dirty_region, (uintptr_t)cookie);
173 }
174 }
175
176 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
177 uint32_t id)
178 {
179 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
180 qemu_mutex_lock(&qxl->track_lock);
181 qxl->guest_surfaces.cmds[id] = 0;
182 qxl->guest_surfaces.count--;
183 qemu_mutex_unlock(&qxl->track_lock);
184 }
185
186 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
187 qxl_async_io async)
188 {
189 QXLCookie *cookie;
190
191 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
192 if (async) {
193 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
194 QXL_IO_DESTROY_SURFACE_ASYNC);
195 cookie->u.surface_id = id;
196 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
197 } else {
198 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
199 }
200 }
201
202 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
203 {
204 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
205 qxl->num_free_res);
206 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
207 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
208 QXL_IO_FLUSH_SURFACES_ASYNC));
209 }
210
211 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
212 uint32_t count)
213 {
214 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
215 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
216 }
217
218 void qxl_spice_oom(PCIQXLDevice *qxl)
219 {
220 trace_qxl_spice_oom(qxl->id);
221 qxl->ssd.worker->oom(qxl->ssd.worker);
222 }
223
224 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
225 {
226 trace_qxl_spice_reset_memslots(qxl->id);
227 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
228 }
229
230 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
231 {
232 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
233 qemu_mutex_lock(&qxl->track_lock);
234 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
235 qxl->guest_surfaces.count = 0;
236 qemu_mutex_unlock(&qxl->track_lock);
237 }
238
239 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
240 {
241 trace_qxl_spice_destroy_surfaces(qxl->id, async);
242 if (async) {
243 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
244 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
245 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
246 } else {
247 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
248 qxl_spice_destroy_surfaces_complete(qxl);
249 }
250 }
251
252 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
253 {
254 trace_qxl_spice_reset_image_cache(qxl->id);
255 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
256 }
257
258 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
259 {
260 trace_qxl_spice_reset_cursor(qxl->id);
261 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
262 qemu_mutex_lock(&qxl->track_lock);
263 qxl->guest_cursor = 0;
264 qemu_mutex_unlock(&qxl->track_lock);
265 }
266
267
268 static inline uint32_t msb_mask(uint32_t val)
269 {
270 uint32_t mask;
271
272 do {
273 mask = ~(val - 1) & val;
274 val &= ~mask;
275 } while (mask < val);
276
277 return mask;
278 }
279
280 static ram_addr_t qxl_rom_size(void)
281 {
282 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
283
284 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
285 rom_size = msb_mask(rom_size * 2 - 1);
286 return rom_size;
287 }
288
289 static void init_qxl_rom(PCIQXLDevice *d)
290 {
291 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
292 QXLModes *modes = (QXLModes *)(rom + 1);
293 uint32_t ram_header_size;
294 uint32_t surface0_area_size;
295 uint32_t num_pages;
296 uint32_t fb;
297 int i, n;
298
299 memset(rom, 0, d->rom_size);
300
301 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
302 rom->id = cpu_to_le32(d->id);
303 rom->log_level = cpu_to_le32(d->guestdebug);
304 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
305
306 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
307 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
308 rom->slots_start = 1;
309 rom->slots_end = NUM_MEMSLOTS - 1;
310 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
311
312 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
313 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
314 if (fb > d->vgamem_size) {
315 continue;
316 }
317 modes->modes[n].id = cpu_to_le32(i);
318 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
319 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
320 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
321 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
322 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
323 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
324 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
325 n++;
326 }
327 modes->n_modes = cpu_to_le32(n);
328
329 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
330 surface0_area_size = ALIGN(d->vgamem_size, 4096);
331 num_pages = d->vga.vram_size;
332 num_pages -= ram_header_size;
333 num_pages -= surface0_area_size;
334 num_pages = num_pages / TARGET_PAGE_SIZE;
335
336 rom->draw_area_offset = cpu_to_le32(0);
337 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
338 rom->pages_offset = cpu_to_le32(surface0_area_size);
339 rom->num_pages = cpu_to_le32(num_pages);
340 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
341
342 d->shadow_rom = *rom;
343 d->rom = rom;
344 d->modes = modes;
345 }
346
347 static void init_qxl_ram(PCIQXLDevice *d)
348 {
349 uint8_t *buf;
350 uint64_t *item;
351
352 buf = d->vga.vram_ptr;
353 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
354 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
355 d->ram->int_pending = cpu_to_le32(0);
356 d->ram->int_mask = cpu_to_le32(0);
357 d->ram->update_surface = 0;
358 SPICE_RING_INIT(&d->ram->cmd_ring);
359 SPICE_RING_INIT(&d->ram->cursor_ring);
360 SPICE_RING_INIT(&d->ram->release_ring);
361 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
362 assert(item);
363 *item = 0;
364 qxl_ring_set_dirty(d);
365 }
366
367 /* can be called from spice server thread context */
368 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
369 {
370 memory_region_set_dirty(mr, addr, end - addr);
371 }
372
373 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
374 {
375 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
376 }
377
378 /* called from spice server thread context only */
379 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
380 {
381 void *base = qxl->vga.vram_ptr;
382 intptr_t offset;
383
384 offset = ptr - base;
385 offset &= ~(TARGET_PAGE_SIZE-1);
386 assert(offset < qxl->vga.vram_size);
387 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
388 }
389
390 /* can be called from spice server thread context */
391 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
392 {
393 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
394 ram_addr_t end = qxl->vga.vram_size;
395 qxl_set_dirty(&qxl->vga.vram, addr, end);
396 }
397
398 /*
399 * keep track of some command state, for savevm/loadvm.
400 * called from spice server thread context only
401 */
402 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
403 {
404 switch (le32_to_cpu(ext->cmd.type)) {
405 case QXL_CMD_SURFACE:
406 {
407 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
408
409 if (!cmd) {
410 return 1;
411 }
412 uint32_t id = le32_to_cpu(cmd->surface_id);
413
414 if (id >= NUM_SURFACES) {
415 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
416 NUM_SURFACES);
417 return 1;
418 }
419 qemu_mutex_lock(&qxl->track_lock);
420 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
421 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
422 qxl->guest_surfaces.count++;
423 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
424 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
425 }
426 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
427 qxl->guest_surfaces.cmds[id] = 0;
428 qxl->guest_surfaces.count--;
429 }
430 qemu_mutex_unlock(&qxl->track_lock);
431 break;
432 }
433 case QXL_CMD_CURSOR:
434 {
435 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
436
437 if (!cmd) {
438 return 1;
439 }
440 if (cmd->type == QXL_CURSOR_SET) {
441 qemu_mutex_lock(&qxl->track_lock);
442 qxl->guest_cursor = ext->cmd.data;
443 qemu_mutex_unlock(&qxl->track_lock);
444 }
445 break;
446 }
447 }
448 return 0;
449 }
450
451 /* spice display interface callbacks */
452
453 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
454 {
455 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
456
457 trace_qxl_interface_attach_worker(qxl->id);
458 qxl->ssd.worker = qxl_worker;
459 }
460
461 static void interface_set_compression_level(QXLInstance *sin, int level)
462 {
463 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
464
465 trace_qxl_interface_set_compression_level(qxl->id, level);
466 qxl->shadow_rom.compression_level = cpu_to_le32(level);
467 qxl->rom->compression_level = cpu_to_le32(level);
468 qxl_rom_set_dirty(qxl);
469 }
470
471 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
472 {
473 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
474
475 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
476 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
477 qxl->rom->mm_clock = cpu_to_le32(mm_time);
478 qxl_rom_set_dirty(qxl);
479 }
480
481 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
482 {
483 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
484
485 trace_qxl_interface_get_init_info(qxl->id);
486 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
487 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
488 info->num_memslots = NUM_MEMSLOTS;
489 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
490 info->internal_groupslot_id = 0;
491 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
492 info->n_surfaces = NUM_SURFACES;
493 }
494
495 static const char *qxl_mode_to_string(int mode)
496 {
497 switch (mode) {
498 case QXL_MODE_COMPAT:
499 return "compat";
500 case QXL_MODE_NATIVE:
501 return "native";
502 case QXL_MODE_UNDEFINED:
503 return "undefined";
504 case QXL_MODE_VGA:
505 return "vga";
506 }
507 return "INVALID";
508 }
509
510 static const char *io_port_to_string(uint32_t io_port)
511 {
512 if (io_port >= QXL_IO_RANGE_SIZE) {
513 return "out of range";
514 }
515 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
516 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
517 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
518 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
519 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
520 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
521 [QXL_IO_RESET] = "QXL_IO_RESET",
522 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
523 [QXL_IO_LOG] = "QXL_IO_LOG",
524 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
525 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
526 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
527 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
528 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
529 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
530 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
531 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
532 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
533 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
534 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
535 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
536 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
537 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
538 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
539 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
540 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
541 };
542 return io_port_to_string[io_port];
543 }
544
545 /* called from spice server thread context only */
546 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
547 {
548 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
549 SimpleSpiceUpdate *update;
550 QXLCommandRing *ring;
551 QXLCommand *cmd;
552 int notify, ret;
553
554 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
555
556 switch (qxl->mode) {
557 case QXL_MODE_VGA:
558 ret = false;
559 qemu_mutex_lock(&qxl->ssd.lock);
560 if (qxl->ssd.update != NULL) {
561 update = qxl->ssd.update;
562 qxl->ssd.update = NULL;
563 *ext = update->ext;
564 ret = true;
565 }
566 qemu_mutex_unlock(&qxl->ssd.lock);
567 if (ret) {
568 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
569 qxl_log_command(qxl, "vga", ext);
570 }
571 return ret;
572 case QXL_MODE_COMPAT:
573 case QXL_MODE_NATIVE:
574 case QXL_MODE_UNDEFINED:
575 ring = &qxl->ram->cmd_ring;
576 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
577 return false;
578 }
579 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
580 if (!cmd) {
581 return false;
582 }
583 ext->cmd = *cmd;
584 ext->group_id = MEMSLOT_GROUP_GUEST;
585 ext->flags = qxl->cmdflags;
586 SPICE_RING_POP(ring, notify);
587 qxl_ring_set_dirty(qxl);
588 if (notify) {
589 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
590 }
591 qxl->guest_primary.commands++;
592 qxl_track_command(qxl, ext);
593 qxl_log_command(qxl, "cmd", ext);
594 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
595 return true;
596 default:
597 return false;
598 }
599 }
600
601 /* called from spice server thread context only */
602 static int interface_req_cmd_notification(QXLInstance *sin)
603 {
604 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
605 int wait = 1;
606
607 trace_qxl_ring_command_req_notification(qxl->id);
608 switch (qxl->mode) {
609 case QXL_MODE_COMPAT:
610 case QXL_MODE_NATIVE:
611 case QXL_MODE_UNDEFINED:
612 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
613 qxl_ring_set_dirty(qxl);
614 break;
615 default:
616 /* nothing */
617 break;
618 }
619 return wait;
620 }
621
622 /* called from spice server thread context only */
623 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
624 {
625 QXLReleaseRing *ring = &d->ram->release_ring;
626 uint64_t *item;
627 int notify;
628
629 #define QXL_FREE_BUNCH_SIZE 32
630
631 if (ring->prod - ring->cons + 1 == ring->num_items) {
632 /* ring full -- can't push */
633 return;
634 }
635 if (!flush && d->oom_running) {
636 /* collect everything from oom handler before pushing */
637 return;
638 }
639 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
640 /* collect a bit more before pushing */
641 return;
642 }
643
644 SPICE_RING_PUSH(ring, notify);
645 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
646 d->guest_surfaces.count, d->num_free_res,
647 d->last_release, notify ? "yes" : "no");
648 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
649 ring->num_items, ring->prod, ring->cons);
650 if (notify) {
651 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
652 }
653 SPICE_RING_PROD_ITEM(d, ring, item);
654 if (!item) {
655 return;
656 }
657 *item = 0;
658 d->num_free_res = 0;
659 d->last_release = NULL;
660 qxl_ring_set_dirty(d);
661 }
662
663 /* called from spice server thread context only */
664 static void interface_release_resource(QXLInstance *sin,
665 struct QXLReleaseInfoExt ext)
666 {
667 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
668 QXLReleaseRing *ring;
669 uint64_t *item, id;
670
671 if (ext.group_id == MEMSLOT_GROUP_HOST) {
672 /* host group -> vga mode update request */
673 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
674 return;
675 }
676
677 /*
678 * ext->info points into guest-visible memory
679 * pci bar 0, $command.release_info
680 */
681 ring = &qxl->ram->release_ring;
682 SPICE_RING_PROD_ITEM(qxl, ring, item);
683 if (!item) {
684 return;
685 }
686 if (*item == 0) {
687 /* stick head into the ring */
688 id = ext.info->id;
689 ext.info->next = 0;
690 qxl_ram_set_dirty(qxl, &ext.info->next);
691 *item = id;
692 qxl_ring_set_dirty(qxl);
693 } else {
694 /* append item to the list */
695 qxl->last_release->next = ext.info->id;
696 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
697 ext.info->next = 0;
698 qxl_ram_set_dirty(qxl, &ext.info->next);
699 }
700 qxl->last_release = ext.info;
701 qxl->num_free_res++;
702 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
703 qxl_push_free_res(qxl, 0);
704 }
705
706 /* called from spice server thread context only */
707 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
708 {
709 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
710 QXLCursorRing *ring;
711 QXLCommand *cmd;
712 int notify;
713
714 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
715
716 switch (qxl->mode) {
717 case QXL_MODE_COMPAT:
718 case QXL_MODE_NATIVE:
719 case QXL_MODE_UNDEFINED:
720 ring = &qxl->ram->cursor_ring;
721 if (SPICE_RING_IS_EMPTY(ring)) {
722 return false;
723 }
724 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
725 if (!cmd) {
726 return false;
727 }
728 ext->cmd = *cmd;
729 ext->group_id = MEMSLOT_GROUP_GUEST;
730 ext->flags = qxl->cmdflags;
731 SPICE_RING_POP(ring, notify);
732 qxl_ring_set_dirty(qxl);
733 if (notify) {
734 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
735 }
736 qxl->guest_primary.commands++;
737 qxl_track_command(qxl, ext);
738 qxl_log_command(qxl, "csr", ext);
739 if (qxl->id == 0) {
740 qxl_render_cursor(qxl, ext);
741 }
742 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
743 return true;
744 default:
745 return false;
746 }
747 }
748
749 /* called from spice server thread context only */
750 static int interface_req_cursor_notification(QXLInstance *sin)
751 {
752 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
753 int wait = 1;
754
755 trace_qxl_ring_cursor_req_notification(qxl->id);
756 switch (qxl->mode) {
757 case QXL_MODE_COMPAT:
758 case QXL_MODE_NATIVE:
759 case QXL_MODE_UNDEFINED:
760 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
761 qxl_ring_set_dirty(qxl);
762 break;
763 default:
764 /* nothing */
765 break;
766 }
767 return wait;
768 }
769
770 /* called from spice server thread context */
771 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
772 {
773 /*
774 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
775 * use by xf86-video-qxl and is defined out in the qxl windows driver.
776 * Probably was at some earlier version that is prior to git start (2009),
777 * and is still guest trigerrable.
778 */
779 fprintf(stderr, "%s: deprecated\n", __func__);
780 }
781
782 /* called from spice server thread context only */
783 static int interface_flush_resources(QXLInstance *sin)
784 {
785 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
786 int ret;
787
788 ret = qxl->num_free_res;
789 if (ret) {
790 qxl_push_free_res(qxl, 1);
791 }
792 return ret;
793 }
794
795 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
796
797 /* called from spice server thread context only */
798 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
799 {
800 uint32_t current_async;
801
802 qemu_mutex_lock(&qxl->async_lock);
803 current_async = qxl->current_async;
804 qxl->current_async = QXL_UNDEFINED_IO;
805 qemu_mutex_unlock(&qxl->async_lock);
806
807 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
808 if (!cookie) {
809 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
810 return;
811 }
812 if (cookie && current_async != cookie->io) {
813 fprintf(stderr,
814 "qxl: %s: error: current_async = %d != %"
815 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
816 }
817 switch (current_async) {
818 case QXL_IO_MEMSLOT_ADD_ASYNC:
819 case QXL_IO_DESTROY_PRIMARY_ASYNC:
820 case QXL_IO_UPDATE_AREA_ASYNC:
821 case QXL_IO_FLUSH_SURFACES_ASYNC:
822 break;
823 case QXL_IO_CREATE_PRIMARY_ASYNC:
824 qxl_create_guest_primary_complete(qxl);
825 break;
826 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
827 qxl_spice_destroy_surfaces_complete(qxl);
828 break;
829 case QXL_IO_DESTROY_SURFACE_ASYNC:
830 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
831 break;
832 default:
833 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
834 current_async);
835 }
836 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
837 }
838
839 /* called from spice server thread context only */
840 static void interface_update_area_complete(QXLInstance *sin,
841 uint32_t surface_id,
842 QXLRect *dirty, uint32_t num_updated_rects)
843 {
844 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
845 int i;
846 int qxl_i;
847
848 qemu_mutex_lock(&qxl->ssd.lock);
849 if (surface_id != 0 || !qxl->render_update_cookie_num) {
850 qemu_mutex_unlock(&qxl->ssd.lock);
851 return;
852 }
853 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
854 dirty->right, dirty->top, dirty->bottom);
855 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
856 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
857 /*
858 * overflow - treat this as a full update. Not expected to be common.
859 */
860 trace_qxl_interface_update_area_complete_overflow(qxl->id,
861 QXL_NUM_DIRTY_RECTS);
862 qxl->guest_primary.resized = 1;
863 }
864 if (qxl->guest_primary.resized) {
865 /*
866 * Don't bother copying or scheduling the bh since we will flip
867 * the whole area anyway on completion of the update_area async call
868 */
869 qemu_mutex_unlock(&qxl->ssd.lock);
870 return;
871 }
872 qxl_i = qxl->num_dirty_rects;
873 for (i = 0; i < num_updated_rects; i++) {
874 qxl->dirty[qxl_i++] = dirty[i];
875 }
876 qxl->num_dirty_rects += num_updated_rects;
877 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
878 qxl->num_dirty_rects);
879 qemu_bh_schedule(qxl->update_area_bh);
880 qemu_mutex_unlock(&qxl->ssd.lock);
881 }
882
883 /* called from spice server thread context only */
884 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
885 {
886 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
887 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
888
889 switch (cookie->type) {
890 case QXL_COOKIE_TYPE_IO:
891 interface_async_complete_io(qxl, cookie);
892 g_free(cookie);
893 break;
894 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
895 qxl_render_update_area_done(qxl, cookie);
896 break;
897 default:
898 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
899 __func__, cookie->type);
900 g_free(cookie);
901 }
902 }
903
904 static const QXLInterface qxl_interface = {
905 .base.type = SPICE_INTERFACE_QXL,
906 .base.description = "qxl gpu",
907 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
908 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
909
910 .attache_worker = interface_attach_worker,
911 .set_compression_level = interface_set_compression_level,
912 .set_mm_time = interface_set_mm_time,
913 .get_init_info = interface_get_init_info,
914
915 /* the callbacks below are called from spice server thread context */
916 .get_command = interface_get_command,
917 .req_cmd_notification = interface_req_cmd_notification,
918 .release_resource = interface_release_resource,
919 .get_cursor_command = interface_get_cursor_command,
920 .req_cursor_notification = interface_req_cursor_notification,
921 .notify_update = interface_notify_update,
922 .flush_resources = interface_flush_resources,
923 .async_complete = interface_async_complete,
924 .update_area_complete = interface_update_area_complete,
925 };
926
927 static void qxl_enter_vga_mode(PCIQXLDevice *d)
928 {
929 if (d->mode == QXL_MODE_VGA) {
930 return;
931 }
932 trace_qxl_enter_vga_mode(d->id);
933 qemu_spice_create_host_primary(&d->ssd);
934 d->mode = QXL_MODE_VGA;
935 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
936 vga_dirty_log_start(&d->vga);
937 }
938
939 static void qxl_exit_vga_mode(PCIQXLDevice *d)
940 {
941 if (d->mode != QXL_MODE_VGA) {
942 return;
943 }
944 trace_qxl_exit_vga_mode(d->id);
945 vga_dirty_log_stop(&d->vga);
946 qxl_destroy_primary(d, QXL_SYNC);
947 }
948
949 static void qxl_update_irq(PCIQXLDevice *d)
950 {
951 uint32_t pending = le32_to_cpu(d->ram->int_pending);
952 uint32_t mask = le32_to_cpu(d->ram->int_mask);
953 int level = !!(pending & mask);
954 qemu_set_irq(d->pci.irq[0], level);
955 qxl_ring_set_dirty(d);
956 }
957
958 static void qxl_check_state(PCIQXLDevice *d)
959 {
960 QXLRam *ram = d->ram;
961 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
962
963 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
964 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
965 }
966
967 static void qxl_reset_state(PCIQXLDevice *d)
968 {
969 QXLRom *rom = d->rom;
970
971 qxl_check_state(d);
972 d->shadow_rom.update_id = cpu_to_le32(0);
973 *rom = d->shadow_rom;
974 qxl_rom_set_dirty(d);
975 init_qxl_ram(d);
976 d->num_free_res = 0;
977 d->last_release = NULL;
978 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
979 }
980
981 static void qxl_soft_reset(PCIQXLDevice *d)
982 {
983 trace_qxl_soft_reset(d->id);
984 qxl_check_state(d);
985 qxl_clear_guest_bug(d);
986 d->current_async = QXL_UNDEFINED_IO;
987
988 if (d->id == 0) {
989 qxl_enter_vga_mode(d);
990 } else {
991 d->mode = QXL_MODE_UNDEFINED;
992 }
993 }
994
995 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
996 {
997 trace_qxl_hard_reset(d->id, loadvm);
998
999 qxl_spice_reset_cursor(d);
1000 qxl_spice_reset_image_cache(d);
1001 qxl_reset_surfaces(d);
1002 qxl_reset_memslots(d);
1003
1004 /* pre loadvm reset must not touch QXLRam. This lives in
1005 * device memory, is migrated together with RAM and thus
1006 * already loaded at this point */
1007 if (!loadvm) {
1008 qxl_reset_state(d);
1009 }
1010 qemu_spice_create_host_memslot(&d->ssd);
1011 qxl_soft_reset(d);
1012 }
1013
1014 static void qxl_reset_handler(DeviceState *dev)
1015 {
1016 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
1017
1018 qxl_hard_reset(d, 0);
1019 }
1020
1021 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1022 {
1023 VGACommonState *vga = opaque;
1024 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1025
1026 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1027 if (qxl->mode != QXL_MODE_VGA) {
1028 qxl_destroy_primary(qxl, QXL_SYNC);
1029 qxl_soft_reset(qxl);
1030 }
1031 vga_ioport_write(opaque, addr, val);
1032 }
1033
1034 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1035 { 0x04, 2, 1, .read = vga_ioport_read,
1036 .write = qxl_vga_ioport_write }, /* 3b4 */
1037 { 0x0a, 1, 1, .read = vga_ioport_read,
1038 .write = qxl_vga_ioport_write }, /* 3ba */
1039 { 0x10, 16, 1, .read = vga_ioport_read,
1040 .write = qxl_vga_ioport_write }, /* 3c0 */
1041 { 0x24, 2, 1, .read = vga_ioport_read,
1042 .write = qxl_vga_ioport_write }, /* 3d4 */
1043 { 0x2a, 1, 1, .read = vga_ioport_read,
1044 .write = qxl_vga_ioport_write }, /* 3da */
1045 PORTIO_END_OF_LIST(),
1046 };
1047
1048 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1049 qxl_async_io async)
1050 {
1051 static const int regions[] = {
1052 QXL_RAM_RANGE_INDEX,
1053 QXL_VRAM_RANGE_INDEX,
1054 QXL_VRAM64_RANGE_INDEX,
1055 };
1056 uint64_t guest_start;
1057 uint64_t guest_end;
1058 int pci_region;
1059 pcibus_t pci_start;
1060 pcibus_t pci_end;
1061 intptr_t virt_start;
1062 QXLDevMemSlot memslot;
1063 int i;
1064
1065 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1066 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1067
1068 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1069
1070 if (slot_id >= NUM_MEMSLOTS) {
1071 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1072 slot_id, NUM_MEMSLOTS);
1073 return 1;
1074 }
1075 if (guest_start > guest_end) {
1076 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1077 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1078 return 1;
1079 }
1080
1081 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1082 pci_region = regions[i];
1083 pci_start = d->pci.io_regions[pci_region].addr;
1084 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1085 /* mapped? */
1086 if (pci_start == -1) {
1087 continue;
1088 }
1089 /* start address in range ? */
1090 if (guest_start < pci_start || guest_start > pci_end) {
1091 continue;
1092 }
1093 /* end address in range ? */
1094 if (guest_end > pci_end) {
1095 continue;
1096 }
1097 /* passed */
1098 break;
1099 }
1100 if (i == ARRAY_SIZE(regions)) {
1101 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1102 return 1;
1103 }
1104
1105 switch (pci_region) {
1106 case QXL_RAM_RANGE_INDEX:
1107 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1108 break;
1109 case QXL_VRAM_RANGE_INDEX:
1110 case 4 /* vram 64bit */:
1111 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1112 break;
1113 default:
1114 /* should not happen */
1115 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1116 return 1;
1117 }
1118
1119 memslot.slot_id = slot_id;
1120 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1121 memslot.virt_start = virt_start + (guest_start - pci_start);
1122 memslot.virt_end = virt_start + (guest_end - pci_start);
1123 memslot.addr_delta = memslot.virt_start - delta;
1124 memslot.generation = d->rom->slot_generation = 0;
1125 qxl_rom_set_dirty(d);
1126
1127 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1128 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1129 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1130 d->guest_slots[slot_id].delta = delta;
1131 d->guest_slots[slot_id].active = 1;
1132 return 0;
1133 }
1134
1135 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1136 {
1137 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1138 d->guest_slots[slot_id].active = 0;
1139 }
1140
1141 static void qxl_reset_memslots(PCIQXLDevice *d)
1142 {
1143 qxl_spice_reset_memslots(d);
1144 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1145 }
1146
1147 static void qxl_reset_surfaces(PCIQXLDevice *d)
1148 {
1149 trace_qxl_reset_surfaces(d->id);
1150 d->mode = QXL_MODE_UNDEFINED;
1151 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1152 }
1153
1154 /* can be also called from spice server thread context */
1155 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1156 {
1157 uint64_t phys = le64_to_cpu(pqxl);
1158 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1159 uint64_t offset = phys & 0xffffffffffff;
1160
1161 switch (group_id) {
1162 case MEMSLOT_GROUP_HOST:
1163 return (void *)(intptr_t)offset;
1164 case MEMSLOT_GROUP_GUEST:
1165 if (slot >= NUM_MEMSLOTS) {
1166 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1167 NUM_MEMSLOTS);
1168 return NULL;
1169 }
1170 if (!qxl->guest_slots[slot].active) {
1171 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1172 return NULL;
1173 }
1174 if (offset < qxl->guest_slots[slot].delta) {
1175 qxl_set_guest_bug(qxl,
1176 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1177 slot, offset, qxl->guest_slots[slot].delta);
1178 return NULL;
1179 }
1180 offset -= qxl->guest_slots[slot].delta;
1181 if (offset > qxl->guest_slots[slot].size) {
1182 qxl_set_guest_bug(qxl,
1183 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1184 slot, offset, qxl->guest_slots[slot].size);
1185 return NULL;
1186 }
1187 return qxl->guest_slots[slot].ptr + offset;
1188 }
1189 return NULL;
1190 }
1191
1192 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1193 {
1194 /* for local rendering */
1195 qxl_render_resize(qxl);
1196 }
1197
1198 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1199 qxl_async_io async)
1200 {
1201 QXLDevSurfaceCreate surface;
1202 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1203 int size;
1204 int requested_height = le32_to_cpu(sc->height);
1205 int requested_stride = le32_to_cpu(sc->stride);
1206
1207 size = abs(requested_stride) * requested_height;
1208 if (size > qxl->vgamem_size) {
1209 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1210 " size", __func__);
1211 return;
1212 }
1213
1214 if (qxl->mode == QXL_MODE_NATIVE) {
1215 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1216 __func__);
1217 }
1218 qxl_exit_vga_mode(qxl);
1219
1220 surface.format = le32_to_cpu(sc->format);
1221 surface.height = le32_to_cpu(sc->height);
1222 surface.mem = le64_to_cpu(sc->mem);
1223 surface.position = le32_to_cpu(sc->position);
1224 surface.stride = le32_to_cpu(sc->stride);
1225 surface.width = le32_to_cpu(sc->width);
1226 surface.type = le32_to_cpu(sc->type);
1227 surface.flags = le32_to_cpu(sc->flags);
1228 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1229 sc->format, sc->position);
1230 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1231 sc->flags);
1232
1233 surface.mouse_mode = true;
1234 surface.group_id = MEMSLOT_GROUP_GUEST;
1235 if (loadvm) {
1236 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1237 }
1238
1239 qxl->mode = QXL_MODE_NATIVE;
1240 qxl->cmdflags = 0;
1241 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1242
1243 if (async == QXL_SYNC) {
1244 qxl_create_guest_primary_complete(qxl);
1245 }
1246 }
1247
1248 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1249 * done (in QXL_SYNC case), 0 otherwise. */
1250 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1251 {
1252 if (d->mode == QXL_MODE_UNDEFINED) {
1253 return 0;
1254 }
1255 trace_qxl_destroy_primary(d->id);
1256 d->mode = QXL_MODE_UNDEFINED;
1257 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1258 qxl_spice_reset_cursor(d);
1259 return 1;
1260 }
1261
1262 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1263 {
1264 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1265 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1266 QXLMode *mode = d->modes->modes + modenr;
1267 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1268 QXLMemSlot slot = {
1269 .mem_start = start,
1270 .mem_end = end
1271 };
1272 QXLSurfaceCreate surface = {
1273 .width = mode->x_res,
1274 .height = mode->y_res,
1275 .stride = -mode->x_res * 4,
1276 .format = SPICE_SURFACE_FMT_32_xRGB,
1277 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1278 .mouse_mode = true,
1279 .mem = devmem + d->shadow_rom.draw_area_offset,
1280 };
1281
1282 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1283 devmem);
1284 if (!loadvm) {
1285 qxl_hard_reset(d, 0);
1286 }
1287
1288 d->guest_slots[0].slot = slot;
1289 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1290
1291 d->guest_primary.surface = surface;
1292 qxl_create_guest_primary(d, 0, QXL_SYNC);
1293
1294 d->mode = QXL_MODE_COMPAT;
1295 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1296 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1297 if (mode->bits == 16) {
1298 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1299 }
1300 #endif
1301 d->shadow_rom.mode = cpu_to_le32(modenr);
1302 d->rom->mode = cpu_to_le32(modenr);
1303 qxl_rom_set_dirty(d);
1304 }
1305
1306 static void ioport_write(void *opaque, target_phys_addr_t addr,
1307 uint64_t val, unsigned size)
1308 {
1309 PCIQXLDevice *d = opaque;
1310 uint32_t io_port = addr;
1311 qxl_async_io async = QXL_SYNC;
1312 uint32_t orig_io_port = io_port;
1313
1314 if (d->guest_bug && !io_port == QXL_IO_RESET) {
1315 return;
1316 }
1317
1318 switch (io_port) {
1319 case QXL_IO_RESET:
1320 case QXL_IO_SET_MODE:
1321 case QXL_IO_MEMSLOT_ADD:
1322 case QXL_IO_MEMSLOT_DEL:
1323 case QXL_IO_CREATE_PRIMARY:
1324 case QXL_IO_UPDATE_IRQ:
1325 case QXL_IO_LOG:
1326 case QXL_IO_MEMSLOT_ADD_ASYNC:
1327 case QXL_IO_CREATE_PRIMARY_ASYNC:
1328 break;
1329 default:
1330 if (d->mode != QXL_MODE_VGA) {
1331 break;
1332 }
1333 trace_qxl_io_unexpected_vga_mode(d->id,
1334 io_port, io_port_to_string(io_port));
1335 /* be nice to buggy guest drivers */
1336 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1337 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1338 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1339 }
1340 return;
1341 }
1342
1343 /* we change the io_port to avoid ifdeffery in the main switch */
1344 orig_io_port = io_port;
1345 switch (io_port) {
1346 case QXL_IO_UPDATE_AREA_ASYNC:
1347 io_port = QXL_IO_UPDATE_AREA;
1348 goto async_common;
1349 case QXL_IO_MEMSLOT_ADD_ASYNC:
1350 io_port = QXL_IO_MEMSLOT_ADD;
1351 goto async_common;
1352 case QXL_IO_CREATE_PRIMARY_ASYNC:
1353 io_port = QXL_IO_CREATE_PRIMARY;
1354 goto async_common;
1355 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1356 io_port = QXL_IO_DESTROY_PRIMARY;
1357 goto async_common;
1358 case QXL_IO_DESTROY_SURFACE_ASYNC:
1359 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1360 goto async_common;
1361 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1362 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1363 goto async_common;
1364 case QXL_IO_FLUSH_SURFACES_ASYNC:
1365 async_common:
1366 async = QXL_ASYNC;
1367 qemu_mutex_lock(&d->async_lock);
1368 if (d->current_async != QXL_UNDEFINED_IO) {
1369 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1370 io_port, d->current_async);
1371 qemu_mutex_unlock(&d->async_lock);
1372 return;
1373 }
1374 d->current_async = orig_io_port;
1375 qemu_mutex_unlock(&d->async_lock);
1376 break;
1377 default:
1378 break;
1379 }
1380 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1381 async);
1382
1383 switch (io_port) {
1384 case QXL_IO_UPDATE_AREA:
1385 {
1386 QXLCookie *cookie = NULL;
1387 QXLRect update = d->ram->update_area;
1388
1389 if (d->ram->update_surface > NUM_SURFACES) {
1390 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1391 d->ram->update_surface);
1392 return;
1393 }
1394 if (update.left >= update.right || update.top >= update.bottom) {
1395 qxl_set_guest_bug(d,
1396 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1397 update.left, update.top, update.right, update.bottom);
1398 return;
1399 }
1400
1401 if (async == QXL_ASYNC) {
1402 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1403 QXL_IO_UPDATE_AREA_ASYNC);
1404 cookie->u.area = update;
1405 }
1406 qxl_spice_update_area(d, d->ram->update_surface,
1407 cookie ? &cookie->u.area : &update,
1408 NULL, 0, 0, async, cookie);
1409 break;
1410 }
1411 case QXL_IO_NOTIFY_CMD:
1412 qemu_spice_wakeup(&d->ssd);
1413 break;
1414 case QXL_IO_NOTIFY_CURSOR:
1415 qemu_spice_wakeup(&d->ssd);
1416 break;
1417 case QXL_IO_UPDATE_IRQ:
1418 qxl_update_irq(d);
1419 break;
1420 case QXL_IO_NOTIFY_OOM:
1421 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1422 break;
1423 }
1424 d->oom_running = 1;
1425 qxl_spice_oom(d);
1426 d->oom_running = 0;
1427 break;
1428 case QXL_IO_SET_MODE:
1429 qxl_set_mode(d, val, 0);
1430 break;
1431 case QXL_IO_LOG:
1432 if (d->guestdebug) {
1433 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1434 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1435 }
1436 break;
1437 case QXL_IO_RESET:
1438 qxl_hard_reset(d, 0);
1439 break;
1440 case QXL_IO_MEMSLOT_ADD:
1441 if (val >= NUM_MEMSLOTS) {
1442 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1443 break;
1444 }
1445 if (d->guest_slots[val].active) {
1446 qxl_set_guest_bug(d,
1447 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1448 break;
1449 }
1450 d->guest_slots[val].slot = d->ram->mem_slot;
1451 qxl_add_memslot(d, val, 0, async);
1452 break;
1453 case QXL_IO_MEMSLOT_DEL:
1454 if (val >= NUM_MEMSLOTS) {
1455 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1456 break;
1457 }
1458 qxl_del_memslot(d, val);
1459 break;
1460 case QXL_IO_CREATE_PRIMARY:
1461 if (val != 0) {
1462 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1463 async);
1464 goto cancel_async;
1465 }
1466 d->guest_primary.surface = d->ram->create_surface;
1467 qxl_create_guest_primary(d, 0, async);
1468 break;
1469 case QXL_IO_DESTROY_PRIMARY:
1470 if (val != 0) {
1471 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1472 async);
1473 goto cancel_async;
1474 }
1475 if (!qxl_destroy_primary(d, async)) {
1476 trace_qxl_io_destroy_primary_ignored(d->id,
1477 qxl_mode_to_string(d->mode));
1478 goto cancel_async;
1479 }
1480 break;
1481 case QXL_IO_DESTROY_SURFACE_WAIT:
1482 if (val >= NUM_SURFACES) {
1483 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1484 "%" PRIu64 " >= NUM_SURFACES", async, val);
1485 goto cancel_async;
1486 }
1487 qxl_spice_destroy_surface_wait(d, val, async);
1488 break;
1489 case QXL_IO_FLUSH_RELEASE: {
1490 QXLReleaseRing *ring = &d->ram->release_ring;
1491 if (ring->prod - ring->cons + 1 == ring->num_items) {
1492 fprintf(stderr,
1493 "ERROR: no flush, full release ring [p%d,%dc]\n",
1494 ring->prod, ring->cons);
1495 }
1496 qxl_push_free_res(d, 1 /* flush */);
1497 break;
1498 }
1499 case QXL_IO_FLUSH_SURFACES_ASYNC:
1500 qxl_spice_flush_surfaces_async(d);
1501 break;
1502 case QXL_IO_DESTROY_ALL_SURFACES:
1503 d->mode = QXL_MODE_UNDEFINED;
1504 qxl_spice_destroy_surfaces(d, async);
1505 break;
1506 default:
1507 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1508 }
1509 return;
1510 cancel_async:
1511 if (async) {
1512 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1513 qemu_mutex_lock(&d->async_lock);
1514 d->current_async = QXL_UNDEFINED_IO;
1515 qemu_mutex_unlock(&d->async_lock);
1516 }
1517 }
1518
1519 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1520 unsigned size)
1521 {
1522 PCIQXLDevice *d = opaque;
1523
1524 trace_qxl_io_read_unexpected(d->id);
1525 return 0xff;
1526 }
1527
1528 static const MemoryRegionOps qxl_io_ops = {
1529 .read = ioport_read,
1530 .write = ioport_write,
1531 .valid = {
1532 .min_access_size = 1,
1533 .max_access_size = 1,
1534 },
1535 };
1536
1537 static void pipe_read(void *opaque)
1538 {
1539 PCIQXLDevice *d = opaque;
1540 char dummy;
1541 int len;
1542
1543 do {
1544 len = read(d->pipe[0], &dummy, sizeof(dummy));
1545 } while (len == sizeof(dummy));
1546 qxl_update_irq(d);
1547 }
1548
1549 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1550 {
1551 uint32_t old_pending;
1552 uint32_t le_events = cpu_to_le32(events);
1553
1554 assert(qemu_spice_display_is_running(&d->ssd));
1555 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1556 if ((old_pending & le_events) == le_events) {
1557 return;
1558 }
1559 if (qemu_thread_is_self(&d->main)) {
1560 qxl_update_irq(d);
1561 } else {
1562 if (write(d->pipe[1], d, 1) != 1) {
1563 dprint(d, 1, "%s: write to pipe failed\n", __func__);
1564 }
1565 }
1566 }
1567
1568 static void init_pipe_signaling(PCIQXLDevice *d)
1569 {
1570 if (pipe(d->pipe) < 0) {
1571 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1572 __FILE__, __func__);
1573 exit(1);
1574 }
1575 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1576 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1577 fcntl(d->pipe[0], F_SETOWN, getpid());
1578
1579 qemu_thread_get_self(&d->main);
1580 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1581 }
1582
1583 /* graphics console */
1584
1585 static void qxl_hw_update(void *opaque)
1586 {
1587 PCIQXLDevice *qxl = opaque;
1588 VGACommonState *vga = &qxl->vga;
1589
1590 switch (qxl->mode) {
1591 case QXL_MODE_VGA:
1592 vga->update(vga);
1593 break;
1594 case QXL_MODE_COMPAT:
1595 case QXL_MODE_NATIVE:
1596 qxl_render_update(qxl);
1597 break;
1598 default:
1599 break;
1600 }
1601 }
1602
1603 static void qxl_hw_invalidate(void *opaque)
1604 {
1605 PCIQXLDevice *qxl = opaque;
1606 VGACommonState *vga = &qxl->vga;
1607
1608 vga->invalidate(vga);
1609 }
1610
1611 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch)
1612 {
1613 PCIQXLDevice *qxl = opaque;
1614 VGACommonState *vga = &qxl->vga;
1615
1616 switch (qxl->mode) {
1617 case QXL_MODE_COMPAT:
1618 case QXL_MODE_NATIVE:
1619 qxl_render_update(qxl);
1620 ppm_save(filename, qxl->ssd.ds->surface);
1621 break;
1622 case QXL_MODE_VGA:
1623 vga->screen_dump(vga, filename, cswitch);
1624 break;
1625 default:
1626 break;
1627 }
1628 }
1629
1630 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1631 {
1632 PCIQXLDevice *qxl = opaque;
1633 VGACommonState *vga = &qxl->vga;
1634
1635 if (qxl->mode == QXL_MODE_VGA) {
1636 vga->text_update(vga, chardata);
1637 return;
1638 }
1639 }
1640
1641 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1642 {
1643 intptr_t vram_start;
1644 int i;
1645
1646 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1647 return;
1648 }
1649
1650 /* dirty the primary surface */
1651 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1652 qxl->shadow_rom.surface0_area_size);
1653
1654 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1655
1656 /* dirty the off-screen surfaces */
1657 for (i = 0; i < NUM_SURFACES; i++) {
1658 QXLSurfaceCmd *cmd;
1659 intptr_t surface_offset;
1660 int surface_size;
1661
1662 if (qxl->guest_surfaces.cmds[i] == 0) {
1663 continue;
1664 }
1665
1666 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1667 MEMSLOT_GROUP_GUEST);
1668 assert(cmd);
1669 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1670 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1671 cmd->u.surface_create.data,
1672 MEMSLOT_GROUP_GUEST);
1673 assert(surface_offset);
1674 surface_offset -= vram_start;
1675 surface_size = cmd->u.surface_create.height *
1676 abs(cmd->u.surface_create.stride);
1677 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1678 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1679 }
1680 }
1681
1682 static void qxl_vm_change_state_handler(void *opaque, int running,
1683 RunState state)
1684 {
1685 PCIQXLDevice *qxl = opaque;
1686 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1687
1688 if (running) {
1689 /*
1690 * if qxl_send_events was called from spice server context before
1691 * migration ended, qxl_update_irq for these events might not have been
1692 * called
1693 */
1694 qxl_update_irq(qxl);
1695 } else {
1696 /* make sure surfaces are saved before migration */
1697 qxl_dirty_surfaces(qxl);
1698 }
1699 }
1700
1701 /* display change listener */
1702
1703 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1704 {
1705 if (qxl0->mode == QXL_MODE_VGA) {
1706 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1707 }
1708 }
1709
1710 static void display_resize(struct DisplayState *ds)
1711 {
1712 if (qxl0->mode == QXL_MODE_VGA) {
1713 qemu_spice_display_resize(&qxl0->ssd);
1714 }
1715 }
1716
1717 static void display_refresh(struct DisplayState *ds)
1718 {
1719 if (qxl0->mode == QXL_MODE_VGA) {
1720 qemu_spice_display_refresh(&qxl0->ssd);
1721 } else {
1722 qemu_mutex_lock(&qxl0->ssd.lock);
1723 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1724 qemu_mutex_unlock(&qxl0->ssd.lock);
1725 }
1726 }
1727
1728 static DisplayChangeListener display_listener = {
1729 .dpy_update = display_update,
1730 .dpy_resize = display_resize,
1731 .dpy_refresh = display_refresh,
1732 };
1733
1734 static void qxl_init_ramsize(PCIQXLDevice *qxl)
1735 {
1736 /* vga mode framebuffer / primary surface (bar 0, first part) */
1737 if (qxl->vgamem_size_mb < 8) {
1738 qxl->vgamem_size_mb = 8;
1739 }
1740 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1741
1742 /* vga ram (bar 0, total) */
1743 if (qxl->ram_size_mb != -1) {
1744 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1745 }
1746 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1747 qxl->vga.vram_size = qxl->vgamem_size * 2;
1748 }
1749
1750 /* vram32 (surfaces, 32bit, bar 1) */
1751 if (qxl->vram32_size_mb != -1) {
1752 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1753 }
1754 if (qxl->vram32_size < 4096) {
1755 qxl->vram32_size = 4096;
1756 }
1757
1758 /* vram (surfaces, 64bit, bar 4+5) */
1759 if (qxl->vram_size_mb != -1) {
1760 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1761 }
1762 if (qxl->vram_size < qxl->vram32_size) {
1763 qxl->vram_size = qxl->vram32_size;
1764 }
1765
1766 if (qxl->revision == 1) {
1767 qxl->vram32_size = 4096;
1768 qxl->vram_size = 4096;
1769 }
1770 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1771 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1772 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1773 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1774 }
1775
1776 static int qxl_init_common(PCIQXLDevice *qxl)
1777 {
1778 uint8_t* config = qxl->pci.config;
1779 uint32_t pci_device_rev;
1780 uint32_t io_size;
1781
1782 qxl->mode = QXL_MODE_UNDEFINED;
1783 qxl->generation = 1;
1784 qxl->num_memslots = NUM_MEMSLOTS;
1785 qxl->num_surfaces = NUM_SURFACES;
1786 qemu_mutex_init(&qxl->track_lock);
1787 qemu_mutex_init(&qxl->async_lock);
1788 qxl->current_async = QXL_UNDEFINED_IO;
1789 qxl->guest_bug = 0;
1790
1791 switch (qxl->revision) {
1792 case 1: /* spice 0.4 -- qxl-1 */
1793 pci_device_rev = QXL_REVISION_STABLE_V04;
1794 io_size = 8;
1795 break;
1796 case 2: /* spice 0.6 -- qxl-2 */
1797 pci_device_rev = QXL_REVISION_STABLE_V06;
1798 io_size = 16;
1799 break;
1800 case 3: /* qxl-3 */
1801 pci_device_rev = QXL_DEFAULT_REVISION;
1802 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1803 break;
1804 default:
1805 error_report("Invalid revision %d for qxl device (max %d)",
1806 qxl->revision, QXL_DEFAULT_REVISION);
1807 return -1;
1808 }
1809
1810 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1811 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1812
1813 qxl->rom_size = qxl_rom_size();
1814 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1815 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1816 init_qxl_rom(qxl);
1817 init_qxl_ram(qxl);
1818
1819 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1820 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
1821 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
1822 0, qxl->vram32_size);
1823
1824 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1825 "qxl-ioports", io_size);
1826 if (qxl->id == 0) {
1827 vga_dirty_log_start(&qxl->vga);
1828 }
1829
1830
1831 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1832 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1833
1834 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1835 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1836
1837 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1838 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1839
1840 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1841 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
1842
1843 if (qxl->vram32_size < qxl->vram_size) {
1844 /*
1845 * Make the 64bit vram bar show up only in case it is
1846 * configured to be larger than the 32bit vram bar.
1847 */
1848 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
1849 PCI_BASE_ADDRESS_SPACE_MEMORY |
1850 PCI_BASE_ADDRESS_MEM_TYPE_64 |
1851 PCI_BASE_ADDRESS_MEM_PREFETCH,
1852 &qxl->vram_bar);
1853 }
1854
1855 /* print pci bar details */
1856 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
1857 qxl->id == 0 ? "pri" : "sec",
1858 qxl->vga.vram_size / (1024*1024));
1859 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
1860 qxl->vram32_size / (1024*1024));
1861 dprint(qxl, 1, "vram/64: %d MB %s\n",
1862 qxl->vram_size / (1024*1024),
1863 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
1864
1865 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1866 qxl->ssd.qxl.id = qxl->id;
1867 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1868 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1869
1870 init_pipe_signaling(qxl);
1871 qxl_reset_state(qxl);
1872
1873 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
1874
1875 return 0;
1876 }
1877
1878 static int qxl_init_primary(PCIDevice *dev)
1879 {
1880 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1881 VGACommonState *vga = &qxl->vga;
1882 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
1883
1884 qxl->id = 0;
1885 qxl_init_ramsize(qxl);
1886 vga->vram_size_mb = qxl->vga.vram_size >> 20;
1887 vga_common_init(vga);
1888 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
1889 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
1890 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
1891
1892 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1893 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1894 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1895
1896 qxl0 = qxl;
1897 register_displaychangelistener(vga->ds, &display_listener);
1898
1899 return qxl_init_common(qxl);
1900 }
1901
1902 static int qxl_init_secondary(PCIDevice *dev)
1903 {
1904 static int device_id = 1;
1905 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1906
1907 qxl->id = device_id++;
1908 qxl_init_ramsize(qxl);
1909 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
1910 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
1911 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1912
1913 return qxl_init_common(qxl);
1914 }
1915
1916 static void qxl_pre_save(void *opaque)
1917 {
1918 PCIQXLDevice* d = opaque;
1919 uint8_t *ram_start = d->vga.vram_ptr;
1920
1921 trace_qxl_pre_save(d->id);
1922 if (d->last_release == NULL) {
1923 d->last_release_offset = 0;
1924 } else {
1925 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1926 }
1927 assert(d->last_release_offset < d->vga.vram_size);
1928 }
1929
1930 static int qxl_pre_load(void *opaque)
1931 {
1932 PCIQXLDevice* d = opaque;
1933
1934 trace_qxl_pre_load(d->id);
1935 qxl_hard_reset(d, 1);
1936 qxl_exit_vga_mode(d);
1937 return 0;
1938 }
1939
1940 static void qxl_create_memslots(PCIQXLDevice *d)
1941 {
1942 int i;
1943
1944 for (i = 0; i < NUM_MEMSLOTS; i++) {
1945 if (!d->guest_slots[i].active) {
1946 continue;
1947 }
1948 qxl_add_memslot(d, i, 0, QXL_SYNC);
1949 }
1950 }
1951
1952 static int qxl_post_load(void *opaque, int version)
1953 {
1954 PCIQXLDevice* d = opaque;
1955 uint8_t *ram_start = d->vga.vram_ptr;
1956 QXLCommandExt *cmds;
1957 int in, out, newmode;
1958
1959 assert(d->last_release_offset < d->vga.vram_size);
1960 if (d->last_release_offset == 0) {
1961 d->last_release = NULL;
1962 } else {
1963 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1964 }
1965
1966 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1967
1968 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
1969 newmode = d->mode;
1970 d->mode = QXL_MODE_UNDEFINED;
1971
1972 switch (newmode) {
1973 case QXL_MODE_UNDEFINED:
1974 break;
1975 case QXL_MODE_VGA:
1976 qxl_create_memslots(d);
1977 qxl_enter_vga_mode(d);
1978 break;
1979 case QXL_MODE_NATIVE:
1980 qxl_create_memslots(d);
1981 qxl_create_guest_primary(d, 1, QXL_SYNC);
1982
1983 /* replay surface-create and cursor-set commands */
1984 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1985 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1986 if (d->guest_surfaces.cmds[in] == 0) {
1987 continue;
1988 }
1989 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1990 cmds[out].cmd.type = QXL_CMD_SURFACE;
1991 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1992 out++;
1993 }
1994 if (d->guest_cursor) {
1995 cmds[out].cmd.data = d->guest_cursor;
1996 cmds[out].cmd.type = QXL_CMD_CURSOR;
1997 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1998 out++;
1999 }
2000 qxl_spice_loadvm_commands(d, cmds, out);
2001 g_free(cmds);
2002
2003 break;
2004 case QXL_MODE_COMPAT:
2005 /* note: no need to call qxl_create_memslots, qxl_set_mode
2006 * creates the mem slot. */
2007 qxl_set_mode(d, d->shadow_rom.mode, 1);
2008 break;
2009 }
2010 return 0;
2011 }
2012
2013 #define QXL_SAVE_VERSION 21
2014
2015 static VMStateDescription qxl_memslot = {
2016 .name = "qxl-memslot",
2017 .version_id = QXL_SAVE_VERSION,
2018 .minimum_version_id = QXL_SAVE_VERSION,
2019 .fields = (VMStateField[]) {
2020 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2021 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2022 VMSTATE_UINT32(active, struct guest_slots),
2023 VMSTATE_END_OF_LIST()
2024 }
2025 };
2026
2027 static VMStateDescription qxl_surface = {
2028 .name = "qxl-surface",
2029 .version_id = QXL_SAVE_VERSION,
2030 .minimum_version_id = QXL_SAVE_VERSION,
2031 .fields = (VMStateField[]) {
2032 VMSTATE_UINT32(width, QXLSurfaceCreate),
2033 VMSTATE_UINT32(height, QXLSurfaceCreate),
2034 VMSTATE_INT32(stride, QXLSurfaceCreate),
2035 VMSTATE_UINT32(format, QXLSurfaceCreate),
2036 VMSTATE_UINT32(position, QXLSurfaceCreate),
2037 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2038 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2039 VMSTATE_UINT32(type, QXLSurfaceCreate),
2040 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2041 VMSTATE_END_OF_LIST()
2042 }
2043 };
2044
2045 static VMStateDescription qxl_vmstate = {
2046 .name = "qxl",
2047 .version_id = QXL_SAVE_VERSION,
2048 .minimum_version_id = QXL_SAVE_VERSION,
2049 .pre_save = qxl_pre_save,
2050 .pre_load = qxl_pre_load,
2051 .post_load = qxl_post_load,
2052 .fields = (VMStateField []) {
2053 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2054 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2055 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2056 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2057 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2058 VMSTATE_UINT32(mode, PCIQXLDevice),
2059 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2060 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2061 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2062 qxl_memslot, struct guest_slots),
2063 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2064 qxl_surface, QXLSurfaceCreate),
2065 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
2066 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
2067 vmstate_info_uint64, uint64_t),
2068 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2069 VMSTATE_END_OF_LIST()
2070 },
2071 };
2072
2073 static Property qxl_properties[] = {
2074 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2075 64 * 1024 * 1024),
2076 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2077 64 * 1024 * 1024),
2078 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2079 QXL_DEFAULT_REVISION),
2080 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2081 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2082 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2083 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2084 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2085 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2086 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2087 DEFINE_PROP_END_OF_LIST(),
2088 };
2089
2090 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2091 {
2092 DeviceClass *dc = DEVICE_CLASS(klass);
2093 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2094
2095 k->no_hotplug = 1;
2096 k->init = qxl_init_primary;
2097 k->romfile = "vgabios-qxl.bin";
2098 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2099 k->device_id = QXL_DEVICE_ID_STABLE;
2100 k->class_id = PCI_CLASS_DISPLAY_VGA;
2101 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2102 dc->reset = qxl_reset_handler;
2103 dc->vmsd = &qxl_vmstate;
2104 dc->props = qxl_properties;
2105 }
2106
2107 static TypeInfo qxl_primary_info = {
2108 .name = "qxl-vga",
2109 .parent = TYPE_PCI_DEVICE,
2110 .instance_size = sizeof(PCIQXLDevice),
2111 .class_init = qxl_primary_class_init,
2112 };
2113
2114 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2115 {
2116 DeviceClass *dc = DEVICE_CLASS(klass);
2117 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2118
2119 k->init = qxl_init_secondary;
2120 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2121 k->device_id = QXL_DEVICE_ID_STABLE;
2122 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2123 dc->desc = "Spice QXL GPU (secondary)";
2124 dc->reset = qxl_reset_handler;
2125 dc->vmsd = &qxl_vmstate;
2126 dc->props = qxl_properties;
2127 }
2128
2129 static TypeInfo qxl_secondary_info = {
2130 .name = "qxl",
2131 .parent = TYPE_PCI_DEVICE,
2132 .instance_size = sizeof(PCIQXLDevice),
2133 .class_init = qxl_secondary_class_init,
2134 };
2135
2136 static void qxl_register_types(void)
2137 {
2138 type_register_static(&qxl_primary_info);
2139 type_register_static(&qxl_secondary_info);
2140 }
2141
2142 type_init(qxl_register_types)