2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
60 #define QXL_MODE(_x, _y, _b, _o) \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
80 static QXLMode qxl_modes
[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
120 static PCIQXLDevice
*qxl0
;
122 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
123 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
124 static void qxl_reset_memslots(PCIQXLDevice
*d
);
125 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
126 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
128 void qxl_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
130 #if SPICE_INTERFACE_QXL_MINOR >= 1
131 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
133 if (qxl
->guestdebug
) {
136 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
137 vfprintf(stderr
, msg
, ap
);
138 fprintf(stderr
, "\n");
144 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
145 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
146 uint32_t num_dirty_rects
,
147 uint32_t clear_dirty_region
,
150 if (async
== QXL_SYNC
) {
151 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
152 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
154 #if SPICE_INTERFACE_QXL_MINOR >= 1
155 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
156 clear_dirty_region
, 0);
163 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
166 qemu_mutex_lock(&qxl
->track_lock
);
167 qxl
->guest_surfaces
.cmds
[id
] = 0;
168 qxl
->guest_surfaces
.count
--;
169 qemu_mutex_unlock(&qxl
->track_lock
);
172 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
176 #if SPICE_INTERFACE_QXL_MINOR < 1
179 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
,
183 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
184 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
188 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
191 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
194 void qxl_spice_oom(PCIQXLDevice
*qxl
)
196 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
199 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
201 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
204 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
206 qemu_mutex_lock(&qxl
->track_lock
);
207 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
208 qxl
->guest_surfaces
.count
= 0;
209 qemu_mutex_unlock(&qxl
->track_lock
);
212 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
215 #if SPICE_INTERFACE_QXL_MINOR < 1
218 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
, 0);
221 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
222 qxl_spice_destroy_surfaces_complete(qxl
);
226 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
228 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
231 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
233 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
237 static inline uint32_t msb_mask(uint32_t val
)
242 mask
= ~(val
- 1) & val
;
244 } while (mask
< val
);
249 static ram_addr_t
qxl_rom_size(void)
251 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
252 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
253 rom_size
= msb_mask(rom_size
* 2 - 1);
257 static void init_qxl_rom(PCIQXLDevice
*d
)
259 QXLRom
*rom
= qemu_get_ram_ptr(d
->rom_offset
);
260 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
261 uint32_t ram_header_size
;
262 uint32_t surface0_area_size
;
264 uint32_t fb
, maxfb
= 0;
267 memset(rom
, 0, d
->rom_size
);
269 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
270 rom
->id
= cpu_to_le32(d
->id
);
271 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
272 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
274 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
275 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
276 rom
->slots_start
= 1;
277 rom
->slots_end
= NUM_MEMSLOTS
- 1;
278 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
280 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
281 for (i
= 0; i
< modes
->n_modes
; i
++) {
282 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
286 modes
->modes
[i
].id
= cpu_to_le32(i
);
287 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
288 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
289 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
290 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
291 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
292 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
293 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
295 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
296 maxfb
= VGA_RAM_SIZE
;
298 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
299 surface0_area_size
= ALIGN(maxfb
, 4096);
300 num_pages
= d
->vga
.vram_size
;
301 num_pages
-= ram_header_size
;
302 num_pages
-= surface0_area_size
;
303 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
305 rom
->draw_area_offset
= cpu_to_le32(0);
306 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
307 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
308 rom
->num_pages
= cpu_to_le32(num_pages
);
309 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
311 d
->shadow_rom
= *rom
;
316 static void init_qxl_ram(PCIQXLDevice
*d
)
321 buf
= d
->vga
.vram_ptr
;
322 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
323 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
324 d
->ram
->int_pending
= cpu_to_le32(0);
325 d
->ram
->int_mask
= cpu_to_le32(0);
326 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
327 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
328 SPICE_RING_INIT(&d
->ram
->release_ring
);
329 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
331 qxl_ring_set_dirty(d
);
334 /* can be called from spice server thread context */
335 static void qxl_set_dirty(ram_addr_t addr
, ram_addr_t end
)
338 cpu_physical_memory_set_dirty(addr
);
339 addr
+= TARGET_PAGE_SIZE
;
343 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
345 ram_addr_t addr
= qxl
->rom_offset
;
346 qxl_set_dirty(addr
, addr
+ qxl
->rom_size
);
349 /* called from spice server thread context only */
350 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
352 ram_addr_t addr
= qxl
->vga
.vram_offset
;
353 void *base
= qxl
->vga
.vram_ptr
;
357 offset
&= ~(TARGET_PAGE_SIZE
-1);
358 assert(offset
< qxl
->vga
.vram_size
);
359 qxl_set_dirty(addr
+ offset
, addr
+ offset
+ TARGET_PAGE_SIZE
);
362 /* can be called from spice server thread context */
363 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
365 ram_addr_t addr
= qxl
->vga
.vram_offset
+ qxl
->shadow_rom
.ram_header_offset
;
366 ram_addr_t end
= qxl
->vga
.vram_offset
+ qxl
->vga
.vram_size
;
367 qxl_set_dirty(addr
, end
);
371 * keep track of some command state, for savevm/loadvm.
372 * called from spice server thread context only
374 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
376 switch (le32_to_cpu(ext
->cmd
.type
)) {
377 case QXL_CMD_SURFACE
:
379 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
380 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
381 PANIC_ON(id
>= NUM_SURFACES
);
382 qemu_mutex_lock(&qxl
->track_lock
);
383 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
384 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
385 qxl
->guest_surfaces
.count
++;
386 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
387 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
389 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
390 qxl
->guest_surfaces
.cmds
[id
] = 0;
391 qxl
->guest_surfaces
.count
--;
393 qemu_mutex_unlock(&qxl
->track_lock
);
398 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
399 if (cmd
->type
== QXL_CURSOR_SET
) {
400 qxl
->guest_cursor
= ext
->cmd
.data
;
407 /* spice display interface callbacks */
409 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
411 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
413 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
414 qxl
->ssd
.worker
= qxl_worker
;
417 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
419 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
421 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
422 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
423 qxl
->rom
->compression_level
= cpu_to_le32(level
);
424 qxl_rom_set_dirty(qxl
);
427 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
429 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
431 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
432 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
433 qxl_rom_set_dirty(qxl
);
436 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
438 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
440 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
441 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
442 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
443 info
->num_memslots
= NUM_MEMSLOTS
;
444 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
445 info
->internal_groupslot_id
= 0;
446 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
447 info
->n_surfaces
= NUM_SURFACES
;
450 static const char *qxl_mode_to_string(int mode
)
453 case QXL_MODE_COMPAT
:
455 case QXL_MODE_NATIVE
:
457 case QXL_MODE_UNDEFINED
:
465 static const char *io_port_to_string(uint32_t io_port
)
467 if (io_port
>= QXL_IO_RANGE_SIZE
) {
468 return "out of range";
470 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
471 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
472 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
473 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
474 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
475 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
476 [QXL_IO_RESET
] = "QXL_IO_RESET",
477 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
478 [QXL_IO_LOG
] = "QXL_IO_LOG",
479 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
480 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
481 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
482 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
483 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
484 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
485 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
486 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
487 #if SPICE_INTERFACE_QXL_MINOR >= 1
488 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
489 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
490 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
491 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
492 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
493 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
494 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
495 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
496 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
499 return io_port_to_string
[io_port
];
502 /* called from spice server thread context only */
503 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
505 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
506 SimpleSpiceUpdate
*update
;
507 QXLCommandRing
*ring
;
513 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
515 qemu_mutex_lock(&qxl
->ssd
.lock
);
516 if (qxl
->ssd
.update
!= NULL
) {
517 update
= qxl
->ssd
.update
;
518 qxl
->ssd
.update
= NULL
;
522 qemu_mutex_unlock(&qxl
->ssd
.lock
);
524 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
525 qxl_log_command(qxl
, "vga", ext
);
528 case QXL_MODE_COMPAT
:
529 case QXL_MODE_NATIVE
:
530 case QXL_MODE_UNDEFINED
:
531 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
532 ring
= &qxl
->ram
->cmd_ring
;
533 if (SPICE_RING_IS_EMPTY(ring
)) {
536 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
537 SPICE_RING_CONS_ITEM(ring
, cmd
);
539 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
540 ext
->flags
= qxl
->cmdflags
;
541 SPICE_RING_POP(ring
, notify
);
542 qxl_ring_set_dirty(qxl
);
544 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
546 qxl
->guest_primary
.commands
++;
547 qxl_track_command(qxl
, ext
);
548 qxl_log_command(qxl
, "cmd", ext
);
555 /* called from spice server thread context only */
556 static int interface_req_cmd_notification(QXLInstance
*sin
)
558 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
562 case QXL_MODE_COMPAT
:
563 case QXL_MODE_NATIVE
:
564 case QXL_MODE_UNDEFINED
:
565 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
566 qxl_ring_set_dirty(qxl
);
575 /* called from spice server thread context only */
576 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
578 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
582 #define QXL_FREE_BUNCH_SIZE 32
584 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
585 /* ring full -- can't push */
588 if (!flush
&& d
->oom_running
) {
589 /* collect everything from oom handler before pushing */
592 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
593 /* collect a bit more before pushing */
597 SPICE_RING_PUSH(ring
, notify
);
598 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
599 d
->num_free_res
, notify
? "yes" : "no",
600 ring
->prod
- ring
->cons
, ring
->num_items
,
601 ring
->prod
, ring
->cons
);
603 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
605 SPICE_RING_PROD_ITEM(ring
, item
);
608 d
->last_release
= NULL
;
609 qxl_ring_set_dirty(d
);
612 /* called from spice server thread context only */
613 static void interface_release_resource(QXLInstance
*sin
,
614 struct QXLReleaseInfoExt ext
)
616 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
617 QXLReleaseRing
*ring
;
620 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
621 /* host group -> vga mode update request */
622 qemu_spice_destroy_update(&qxl
->ssd
, (void*)ext
.info
->id
);
627 * ext->info points into guest-visible memory
628 * pci bar 0, $command.release_info
630 ring
= &qxl
->ram
->release_ring
;
631 SPICE_RING_PROD_ITEM(ring
, item
);
633 /* stick head into the ring */
636 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
638 qxl_ring_set_dirty(qxl
);
640 /* append item to the list */
641 qxl
->last_release
->next
= ext
.info
->id
;
642 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
644 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
646 qxl
->last_release
= ext
.info
;
648 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
649 qxl_push_free_res(qxl
, 0);
652 /* called from spice server thread context only */
653 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
655 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
661 case QXL_MODE_COMPAT
:
662 case QXL_MODE_NATIVE
:
663 case QXL_MODE_UNDEFINED
:
664 ring
= &qxl
->ram
->cursor_ring
;
665 if (SPICE_RING_IS_EMPTY(ring
)) {
668 SPICE_RING_CONS_ITEM(ring
, cmd
);
670 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
671 ext
->flags
= qxl
->cmdflags
;
672 SPICE_RING_POP(ring
, notify
);
673 qxl_ring_set_dirty(qxl
);
675 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
677 qxl
->guest_primary
.commands
++;
678 qxl_track_command(qxl
, ext
);
679 qxl_log_command(qxl
, "csr", ext
);
681 qxl_render_cursor(qxl
, ext
);
689 /* called from spice server thread context only */
690 static int interface_req_cursor_notification(QXLInstance
*sin
)
692 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
696 case QXL_MODE_COMPAT
:
697 case QXL_MODE_NATIVE
:
698 case QXL_MODE_UNDEFINED
:
699 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
700 qxl_ring_set_dirty(qxl
);
709 /* called from spice server thread context */
710 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
712 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
716 /* called from spice server thread context only */
717 static int interface_flush_resources(QXLInstance
*sin
)
719 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
722 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
723 ret
= qxl
->num_free_res
;
725 qxl_push_free_res(qxl
, 1);
730 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
732 #if SPICE_INTERFACE_QXL_MINOR >= 1
734 /* called from spice server thread context only */
735 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie
)
737 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
738 uint32_t current_async
;
740 qemu_mutex_lock(&qxl
->async_lock
);
741 current_async
= qxl
->current_async
;
742 qxl
->current_async
= QXL_UNDEFINED_IO
;
743 qemu_mutex_unlock(&qxl
->async_lock
);
745 dprint(qxl
, 2, "async_complete: %d (%ld) done\n", current_async
, cookie
);
746 switch (current_async
) {
747 case QXL_IO_CREATE_PRIMARY_ASYNC
:
748 qxl_create_guest_primary_complete(qxl
);
750 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
751 qxl_spice_destroy_surfaces_complete(qxl
);
753 case QXL_IO_DESTROY_SURFACE_ASYNC
:
754 qxl_spice_destroy_surface_wait_complete(qxl
, (uint32_t)cookie
);
757 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
762 static const QXLInterface qxl_interface
= {
763 .base
.type
= SPICE_INTERFACE_QXL
,
764 .base
.description
= "qxl gpu",
765 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
766 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
768 .attache_worker
= interface_attach_worker
,
769 .set_compression_level
= interface_set_compression_level
,
770 .set_mm_time
= interface_set_mm_time
,
771 .get_init_info
= interface_get_init_info
,
773 /* the callbacks below are called from spice server thread context */
774 .get_command
= interface_get_command
,
775 .req_cmd_notification
= interface_req_cmd_notification
,
776 .release_resource
= interface_release_resource
,
777 .get_cursor_command
= interface_get_cursor_command
,
778 .req_cursor_notification
= interface_req_cursor_notification
,
779 .notify_update
= interface_notify_update
,
780 .flush_resources
= interface_flush_resources
,
781 #if SPICE_INTERFACE_QXL_MINOR >= 1
782 .async_complete
= interface_async_complete
,
786 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
788 if (d
->mode
== QXL_MODE_VGA
) {
791 dprint(d
, 1, "%s\n", __FUNCTION__
);
792 qemu_spice_create_host_primary(&d
->ssd
);
793 d
->mode
= QXL_MODE_VGA
;
794 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
797 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
799 if (d
->mode
!= QXL_MODE_VGA
) {
802 dprint(d
, 1, "%s\n", __FUNCTION__
);
803 qxl_destroy_primary(d
, QXL_SYNC
);
806 static void qxl_set_irq(PCIQXLDevice
*d
)
808 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
809 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
810 int level
= !!(pending
& mask
);
811 qemu_set_irq(d
->pci
.irq
[0], level
);
812 qxl_ring_set_dirty(d
);
815 static void qxl_write_config(PCIDevice
*d
, uint32_t address
,
816 uint32_t val
, int len
)
818 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, d
);
819 VGACommonState
*vga
= &qxl
->vga
;
821 vga_dirty_log_stop(vga
);
822 pci_default_write_config(d
, address
, val
, len
);
823 if (vga
->map_addr
&& qxl
->pci
.io_regions
[0].addr
== -1) {
826 vga_dirty_log_start(vga
);
829 static void qxl_check_state(PCIQXLDevice
*d
)
831 QXLRam
*ram
= d
->ram
;
833 assert(SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
834 assert(SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
837 static void qxl_reset_state(PCIQXLDevice
*d
)
839 QXLRam
*ram
= d
->ram
;
840 QXLRom
*rom
= d
->rom
;
842 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
843 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
844 d
->shadow_rom
.update_id
= cpu_to_le32(0);
845 *rom
= d
->shadow_rom
;
846 qxl_rom_set_dirty(d
);
849 d
->last_release
= NULL
;
850 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
853 static void qxl_soft_reset(PCIQXLDevice
*d
)
855 dprint(d
, 1, "%s:\n", __FUNCTION__
);
859 qxl_enter_vga_mode(d
);
861 d
->mode
= QXL_MODE_UNDEFINED
;
865 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
867 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
868 loadvm
? " (loadvm)" : "");
870 qxl_spice_reset_cursor(d
);
871 qxl_spice_reset_image_cache(d
);
872 qxl_reset_surfaces(d
);
873 qxl_reset_memslots(d
);
875 /* pre loadvm reset must not touch QXLRam. This lives in
876 * device memory, is migrated together with RAM and thus
877 * already loaded at this point */
881 qemu_spice_create_host_memslot(&d
->ssd
);
884 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
887 static void qxl_reset_handler(DeviceState
*dev
)
889 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
890 qxl_hard_reset(d
, 0);
893 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
895 VGACommonState
*vga
= opaque
;
896 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
898 if (qxl
->mode
!= QXL_MODE_VGA
) {
899 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
900 qxl_destroy_primary(qxl
, QXL_SYNC
);
903 vga_ioport_write(opaque
, addr
, val
);
906 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
909 static const int regions
[] = {
911 QXL_VRAM_RANGE_INDEX
,
913 uint64_t guest_start
;
919 QXLDevMemSlot memslot
;
922 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
923 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
925 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
926 __FUNCTION__
, slot_id
,
927 guest_start
, guest_end
);
929 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
930 PANIC_ON(guest_start
> guest_end
);
932 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
933 pci_region
= regions
[i
];
934 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
935 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
937 if (pci_start
== -1) {
940 /* start address in range ? */
941 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
944 /* end address in range ? */
945 if (guest_end
> pci_end
) {
951 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
953 switch (pci_region
) {
954 case QXL_RAM_RANGE_INDEX
:
955 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vga
.vram_offset
);
957 case QXL_VRAM_RANGE_INDEX
:
958 virt_start
= (intptr_t)qemu_get_ram_ptr(d
->vram_offset
);
961 /* should not happen */
965 memslot
.slot_id
= slot_id
;
966 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
967 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
968 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
969 memslot
.addr_delta
= memslot
.virt_start
- delta
;
970 memslot
.generation
= d
->rom
->slot_generation
= 0;
971 qxl_rom_set_dirty(d
);
973 dprint(d
, 1, "%s: slot %d: host virt 0x%" PRIx64
" - 0x%" PRIx64
"\n",
974 __FUNCTION__
, memslot
.slot_id
,
975 memslot
.virt_start
, memslot
.virt_end
);
977 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
978 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
979 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
980 d
->guest_slots
[slot_id
].delta
= delta
;
981 d
->guest_slots
[slot_id
].active
= 1;
984 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
986 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
987 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
988 d
->guest_slots
[slot_id
].active
= 0;
991 static void qxl_reset_memslots(PCIQXLDevice
*d
)
993 dprint(d
, 1, "%s:\n", __FUNCTION__
);
994 qxl_spice_reset_memslots(d
);
995 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
998 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
1000 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1001 d
->mode
= QXL_MODE_UNDEFINED
;
1002 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
1005 /* called from spice server thread context only */
1006 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
1008 uint64_t phys
= le64_to_cpu(pqxl
);
1009 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
1010 uint64_t offset
= phys
& 0xffffffffffff;
1013 case MEMSLOT_GROUP_HOST
:
1014 return (void*)offset
;
1015 case MEMSLOT_GROUP_GUEST
:
1016 PANIC_ON(slot
> NUM_MEMSLOTS
);
1017 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
1018 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
1019 offset
-= qxl
->guest_slots
[slot
].delta
;
1020 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
1021 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1027 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1029 /* for local rendering */
1030 qxl_render_resize(qxl
);
1033 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1036 QXLDevSurfaceCreate surface
;
1037 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1039 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
1040 qxl_exit_vga_mode(qxl
);
1042 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
1043 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
1045 surface
.format
= le32_to_cpu(sc
->format
);
1046 surface
.height
= le32_to_cpu(sc
->height
);
1047 surface
.mem
= le64_to_cpu(sc
->mem
);
1048 surface
.position
= le32_to_cpu(sc
->position
);
1049 surface
.stride
= le32_to_cpu(sc
->stride
);
1050 surface
.width
= le32_to_cpu(sc
->width
);
1051 surface
.type
= le32_to_cpu(sc
->type
);
1052 surface
.flags
= le32_to_cpu(sc
->flags
);
1054 surface
.mouse_mode
= true;
1055 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1057 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1060 qxl
->mode
= QXL_MODE_NATIVE
;
1062 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1064 if (async
== QXL_SYNC
) {
1065 qxl_create_guest_primary_complete(qxl
);
1069 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1070 * done (in QXL_SYNC case), 0 otherwise. */
1071 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1073 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1077 dprint(d
, 1, "%s\n", __FUNCTION__
);
1079 d
->mode
= QXL_MODE_UNDEFINED
;
1080 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1084 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1086 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1087 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1088 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1089 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1094 QXLSurfaceCreate surface
= {
1095 .width
= mode
->x_res
,
1096 .height
= mode
->y_res
,
1097 .stride
= -mode
->x_res
* 4,
1098 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1099 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1101 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1104 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__
,
1105 modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
1107 qxl_hard_reset(d
, 0);
1110 d
->guest_slots
[0].slot
= slot
;
1111 qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
);
1113 d
->guest_primary
.surface
= surface
;
1114 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1116 d
->mode
= QXL_MODE_COMPAT
;
1117 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1118 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1119 if (mode
->bits
== 16) {
1120 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1123 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1124 d
->rom
->mode
= cpu_to_le32(modenr
);
1125 qxl_rom_set_dirty(d
);
1128 static void ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
1130 PCIQXLDevice
*d
= opaque
;
1131 uint32_t io_port
= addr
- d
->io_base
;
1132 qxl_async_io async
= QXL_SYNC
;
1133 #if SPICE_INTERFACE_QXL_MINOR >= 1
1134 uint32_t orig_io_port
= io_port
;
1139 case QXL_IO_SET_MODE
:
1140 case QXL_IO_MEMSLOT_ADD
:
1141 case QXL_IO_MEMSLOT_DEL
:
1142 case QXL_IO_CREATE_PRIMARY
:
1143 case QXL_IO_UPDATE_IRQ
:
1145 #if SPICE_INTERFACE_QXL_MINOR >= 1
1146 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1147 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1151 if (d
->mode
!= QXL_MODE_VGA
) {
1154 dprint(d
, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1155 __func__
, io_port
, io_port_to_string(io_port
));
1156 #if SPICE_INTERFACE_QXL_MINOR >= 1
1157 /* be nice to buggy guest drivers */
1158 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1159 io_port
<= QXL_IO_DESTROY_ALL_SURFACES_ASYNC
) {
1160 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1166 #if SPICE_INTERFACE_QXL_MINOR >= 1
1167 /* we change the io_port to avoid ifdeffery in the main switch */
1168 orig_io_port
= io_port
;
1170 case QXL_IO_UPDATE_AREA_ASYNC
:
1171 io_port
= QXL_IO_UPDATE_AREA
;
1173 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1174 io_port
= QXL_IO_MEMSLOT_ADD
;
1176 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1177 io_port
= QXL_IO_CREATE_PRIMARY
;
1179 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1180 io_port
= QXL_IO_DESTROY_PRIMARY
;
1182 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1183 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1185 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1186 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1189 qemu_mutex_lock(&d
->async_lock
);
1190 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1191 qxl_guest_bug(d
, "%d async started before last (%d) complete",
1192 io_port
, d
->current_async
);
1193 qemu_mutex_unlock(&d
->async_lock
);
1196 d
->current_async
= orig_io_port
;
1197 qemu_mutex_unlock(&d
->async_lock
);
1198 dprint(d
, 2, "start async %d (%d)\n", io_port
, val
);
1206 case QXL_IO_UPDATE_AREA
:
1208 QXLRect update
= d
->ram
->update_area
;
1209 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1210 &update
, NULL
, 0, 0, async
);
1213 case QXL_IO_NOTIFY_CMD
:
1214 qemu_spice_wakeup(&d
->ssd
);
1216 case QXL_IO_NOTIFY_CURSOR
:
1217 qemu_spice_wakeup(&d
->ssd
);
1219 case QXL_IO_UPDATE_IRQ
:
1222 case QXL_IO_NOTIFY_OOM
:
1223 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1227 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1234 case QXL_IO_SET_MODE
:
1235 dprint(d
, 1, "QXL_SET_MODE %d\n", val
);
1236 qxl_set_mode(d
, val
, 0);
1239 if (d
->guestdebug
) {
1240 fprintf(stderr
, "qxl/guest-%d: %ld: %s", d
->id
,
1241 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1245 dprint(d
, 1, "QXL_IO_RESET\n");
1246 qxl_hard_reset(d
, 0);
1248 case QXL_IO_MEMSLOT_ADD
:
1249 if (val
>= NUM_MEMSLOTS
) {
1250 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1253 if (d
->guest_slots
[val
].active
) {
1254 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1257 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1258 qxl_add_memslot(d
, val
, 0, async
);
1260 case QXL_IO_MEMSLOT_DEL
:
1261 if (val
>= NUM_MEMSLOTS
) {
1262 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1265 qxl_del_memslot(d
, val
);
1267 case QXL_IO_CREATE_PRIMARY
:
1269 qxl_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1273 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async
);
1274 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1275 qxl_create_guest_primary(d
, 0, async
);
1277 case QXL_IO_DESTROY_PRIMARY
:
1279 qxl_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1283 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async
,
1284 qxl_mode_to_string(d
->mode
));
1285 if (!qxl_destroy_primary(d
, async
)) {
1286 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1287 qxl_mode_to_string(d
->mode
));
1291 case QXL_IO_DESTROY_SURFACE_WAIT
:
1292 if (val
>= NUM_SURFACES
) {
1293 qxl_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1294 "%d >= NUM_SURFACES", async
, val
);
1297 qxl_spice_destroy_surface_wait(d
, val
, async
);
1299 case QXL_IO_DESTROY_ALL_SURFACES
:
1300 d
->mode
= QXL_MODE_UNDEFINED
;
1301 qxl_spice_destroy_surfaces(d
, async
);
1304 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1309 #if SPICE_INTERFACE_QXL_MINOR >= 1
1311 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1312 qemu_mutex_lock(&d
->async_lock
);
1313 d
->current_async
= QXL_UNDEFINED_IO
;
1314 qemu_mutex_unlock(&d
->async_lock
);
1321 static uint32_t ioport_read(void *opaque
, uint32_t addr
)
1323 PCIQXLDevice
*d
= opaque
;
1325 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1329 static void qxl_map(PCIDevice
*pci
, int region_num
,
1330 pcibus_t addr
, pcibus_t size
, int type
)
1332 static const char *names
[] = {
1333 [ QXL_IO_RANGE_INDEX
] = "ioports",
1334 [ QXL_RAM_RANGE_INDEX
] = "devram",
1335 [ QXL_ROM_RANGE_INDEX
] = "rom",
1336 [ QXL_VRAM_RANGE_INDEX
] = "vram",
1338 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, pci
);
1340 dprint(qxl
, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__
,
1341 region_num
, names
[region_num
], addr
, size
);
1343 switch (region_num
) {
1344 case QXL_IO_RANGE_INDEX
:
1345 register_ioport_write(addr
, size
, 1, ioport_write
, pci
);
1346 register_ioport_read(addr
, size
, 1, ioport_read
, pci
);
1347 qxl
->io_base
= addr
;
1349 case QXL_RAM_RANGE_INDEX
:
1350 cpu_register_physical_memory(addr
, size
, qxl
->vga
.vram_offset
| IO_MEM_RAM
);
1351 qxl
->vga
.map_addr
= addr
;
1352 qxl
->vga
.map_end
= addr
+ size
;
1354 vga_dirty_log_start(&qxl
->vga
);
1357 case QXL_ROM_RANGE_INDEX
:
1358 cpu_register_physical_memory(addr
, size
, qxl
->rom_offset
| IO_MEM_ROM
);
1360 case QXL_VRAM_RANGE_INDEX
:
1361 cpu_register_physical_memory(addr
, size
, qxl
->vram_offset
| IO_MEM_RAM
);
1366 static void pipe_read(void *opaque
)
1368 PCIQXLDevice
*d
= opaque
;
1373 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1374 } while (len
== sizeof(dummy
));
1378 /* called from spice server thread context only */
1379 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1381 uint32_t old_pending
;
1382 uint32_t le_events
= cpu_to_le32(events
);
1384 assert(d
->ssd
.running
);
1385 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1386 if ((old_pending
& le_events
) == le_events
) {
1389 if (pthread_self() == d
->main
) {
1392 if (write(d
->pipe
[1], d
, 1) != 1) {
1393 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1398 static void init_pipe_signaling(PCIQXLDevice
*d
)
1400 if (pipe(d
->pipe
) < 0) {
1401 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1404 #ifdef CONFIG_IOTHREAD
1405 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1407 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
/* | O_ASYNC */);
1409 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1410 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1412 d
->main
= pthread_self();
1413 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1416 /* graphics console */
1418 static void qxl_hw_update(void *opaque
)
1420 PCIQXLDevice
*qxl
= opaque
;
1421 VGACommonState
*vga
= &qxl
->vga
;
1423 switch (qxl
->mode
) {
1427 case QXL_MODE_COMPAT
:
1428 case QXL_MODE_NATIVE
:
1429 qxl_render_update(qxl
);
1436 static void qxl_hw_invalidate(void *opaque
)
1438 PCIQXLDevice
*qxl
= opaque
;
1439 VGACommonState
*vga
= &qxl
->vga
;
1441 vga
->invalidate(vga
);
1444 static void qxl_hw_screen_dump(void *opaque
, const char *filename
)
1446 PCIQXLDevice
*qxl
= opaque
;
1447 VGACommonState
*vga
= &qxl
->vga
;
1449 switch (qxl
->mode
) {
1450 case QXL_MODE_COMPAT
:
1451 case QXL_MODE_NATIVE
:
1452 qxl_render_update(qxl
);
1453 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1456 vga
->screen_dump(vga
, filename
);
1463 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1465 PCIQXLDevice
*qxl
= opaque
;
1466 VGACommonState
*vga
= &qxl
->vga
;
1468 if (qxl
->mode
== QXL_MODE_VGA
) {
1469 vga
->text_update(vga
, chardata
);
1474 static void qxl_vm_change_state_handler(void *opaque
, int running
, int reason
)
1476 PCIQXLDevice
*qxl
= opaque
;
1477 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, reason
);
1479 if (!running
&& qxl
->mode
== QXL_MODE_NATIVE
) {
1480 /* dirty all vram (which holds surfaces) and devram (primary surface)
1481 * to make sure they are saved */
1482 /* FIXME #1: should go out during "live" stage */
1483 /* FIXME #2: we only need to save the areas which are actually used */
1484 ram_addr_t vram_addr
= qxl
->vram_offset
;
1485 ram_addr_t surface0_addr
= qxl
->vga
.vram_offset
+ qxl
->shadow_rom
.draw_area_offset
;
1486 qxl_set_dirty(vram_addr
, vram_addr
+ qxl
->vram_size
);
1487 qxl_set_dirty(surface0_addr
, surface0_addr
+ qxl
->shadow_rom
.surface0_area_size
);
1491 /* display change listener */
1493 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1495 if (qxl0
->mode
== QXL_MODE_VGA
) {
1496 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1500 static void display_resize(struct DisplayState
*ds
)
1502 if (qxl0
->mode
== QXL_MODE_VGA
) {
1503 qemu_spice_display_resize(&qxl0
->ssd
);
1507 static void display_refresh(struct DisplayState
*ds
)
1509 if (qxl0
->mode
== QXL_MODE_VGA
) {
1510 qemu_spice_display_refresh(&qxl0
->ssd
);
1514 static DisplayChangeListener display_listener
= {
1515 .dpy_update
= display_update
,
1516 .dpy_resize
= display_resize
,
1517 .dpy_refresh
= display_refresh
,
1520 static int qxl_init_common(PCIQXLDevice
*qxl
)
1522 uint8_t* config
= qxl
->pci
.config
;
1523 uint32_t pci_device_rev
;
1526 qxl
->mode
= QXL_MODE_UNDEFINED
;
1527 qxl
->generation
= 1;
1528 qxl
->num_memslots
= NUM_MEMSLOTS
;
1529 qxl
->num_surfaces
= NUM_SURFACES
;
1530 qemu_mutex_init(&qxl
->track_lock
);
1531 qemu_mutex_init(&qxl
->async_lock
);
1532 qxl
->current_async
= QXL_UNDEFINED_IO
;
1534 switch (qxl
->revision
) {
1535 case 1: /* spice 0.4 -- qxl-1 */
1536 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1538 case 2: /* spice 0.6 -- qxl-2 */
1540 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1544 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1545 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1547 qxl
->rom_size
= qxl_rom_size();
1548 qxl
->rom_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vrom", qxl
->rom_size
);
1552 if (qxl
->vram_size
< 16 * 1024 * 1024) {
1553 qxl
->vram_size
= 16 * 1024 * 1024;
1555 if (qxl
->revision
== 1) {
1556 qxl
->vram_size
= 4096;
1558 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1559 qxl
->vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vram", qxl
->vram_size
);
1561 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1562 if (qxl
->revision
== 1) {
1566 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1567 io_size
, PCI_BASE_ADDRESS_SPACE_IO
, qxl_map
);
1569 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1570 qxl
->rom_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1573 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1574 qxl
->vga
.vram_size
, PCI_BASE_ADDRESS_SPACE_MEMORY
,
1577 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
, qxl
->vram_size
,
1578 PCI_BASE_ADDRESS_SPACE_MEMORY
, qxl_map
);
1580 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1581 qxl
->ssd
.qxl
.id
= qxl
->id
;
1582 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1583 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1585 init_pipe_signaling(qxl
);
1586 qxl_reset_state(qxl
);
1591 static int qxl_init_primary(PCIDevice
*dev
)
1593 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1594 VGACommonState
*vga
= &qxl
->vga
;
1595 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1599 if (ram_size
< 32 * 1024 * 1024) {
1600 ram_size
= 32 * 1024 * 1024;
1602 vga_common_init(vga
, ram_size
);
1604 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write
, vga
);
1605 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write
, vga
);
1606 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write
, vga
);
1607 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write
, vga
);
1608 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write
, vga
);
1610 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1611 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1612 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1615 register_displaychangelistener(vga
->ds
, &display_listener
);
1617 return qxl_init_common(qxl
);
1620 static int qxl_init_secondary(PCIDevice
*dev
)
1622 static int device_id
= 1;
1623 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1624 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1626 qxl
->id
= device_id
++;
1628 if (ram_size
< 16 * 1024 * 1024) {
1629 ram_size
= 16 * 1024 * 1024;
1631 qxl
->vga
.vram_size
= ram_size
;
1632 qxl
->vga
.vram_offset
= qemu_ram_alloc(&qxl
->pci
.qdev
, "qxl.vgavram",
1633 qxl
->vga
.vram_size
);
1634 qxl
->vga
.vram_ptr
= qemu_get_ram_ptr(qxl
->vga
.vram_offset
);
1636 return qxl_init_common(qxl
);
1639 static void qxl_pre_save(void *opaque
)
1641 PCIQXLDevice
* d
= opaque
;
1642 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1644 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1645 if (d
->last_release
== NULL
) {
1646 d
->last_release_offset
= 0;
1648 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1650 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1653 static int qxl_pre_load(void *opaque
)
1655 PCIQXLDevice
* d
= opaque
;
1657 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1658 qxl_hard_reset(d
, 1);
1659 qxl_exit_vga_mode(d
);
1660 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1664 static int qxl_post_load(void *opaque
, int version
)
1666 PCIQXLDevice
* d
= opaque
;
1667 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1668 QXLCommandExt
*cmds
;
1669 int in
, out
, i
, newmode
;
1671 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1673 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1674 if (d
->last_release_offset
== 0) {
1675 d
->last_release
= NULL
;
1677 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1680 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1682 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1683 qxl_mode_to_string(d
->mode
));
1685 d
->mode
= QXL_MODE_UNDEFINED
;
1687 case QXL_MODE_UNDEFINED
:
1690 qxl_enter_vga_mode(d
);
1692 case QXL_MODE_NATIVE
:
1693 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1694 if (!d
->guest_slots
[i
].active
) {
1697 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
1699 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
1701 /* replay surface-create and cursor-set commands */
1702 cmds
= qemu_mallocz(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1703 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1704 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1707 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1708 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1709 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1712 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1713 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1714 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1716 qxl_spice_loadvm_commands(d
, cmds
, out
);
1720 case QXL_MODE_COMPAT
:
1721 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1724 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1729 #define QXL_SAVE_VERSION 21
1731 static VMStateDescription qxl_memslot
= {
1732 .name
= "qxl-memslot",
1733 .version_id
= QXL_SAVE_VERSION
,
1734 .minimum_version_id
= QXL_SAVE_VERSION
,
1735 .fields
= (VMStateField
[]) {
1736 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1737 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1738 VMSTATE_UINT32(active
, struct guest_slots
),
1739 VMSTATE_END_OF_LIST()
1743 static VMStateDescription qxl_surface
= {
1744 .name
= "qxl-surface",
1745 .version_id
= QXL_SAVE_VERSION
,
1746 .minimum_version_id
= QXL_SAVE_VERSION
,
1747 .fields
= (VMStateField
[]) {
1748 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1749 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1750 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1751 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1752 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1753 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1754 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1755 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1756 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1757 VMSTATE_END_OF_LIST()
1761 static VMStateDescription qxl_vmstate
= {
1763 .version_id
= QXL_SAVE_VERSION
,
1764 .minimum_version_id
= QXL_SAVE_VERSION
,
1765 .pre_save
= qxl_pre_save
,
1766 .pre_load
= qxl_pre_load
,
1767 .post_load
= qxl_post_load
,
1768 .fields
= (VMStateField
[]) {
1769 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1770 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1771 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1772 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1773 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1774 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1775 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1776 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1777 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1778 qxl_memslot
, struct guest_slots
),
1779 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1780 qxl_surface
, QXLSurfaceCreate
),
1781 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1782 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1783 vmstate_info_uint64
, uint64_t),
1784 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1785 VMSTATE_END_OF_LIST()
1789 static PCIDeviceInfo qxl_info_primary
= {
1790 .qdev
.name
= "qxl-vga",
1791 .qdev
.desc
= "Spice QXL GPU (primary, vga compatible)",
1792 .qdev
.size
= sizeof(PCIQXLDevice
),
1793 .qdev
.reset
= qxl_reset_handler
,
1794 .qdev
.vmsd
= &qxl_vmstate
,
1796 .init
= qxl_init_primary
,
1797 .config_write
= qxl_write_config
,
1798 .romfile
= "vgabios-qxl.bin",
1799 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1800 .device_id
= QXL_DEVICE_ID_STABLE
,
1801 .class_id
= PCI_CLASS_DISPLAY_VGA
,
1802 .qdev
.props
= (Property
[]) {
1803 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1804 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1805 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1806 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1807 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1808 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1809 DEFINE_PROP_END_OF_LIST(),
1813 static PCIDeviceInfo qxl_info_secondary
= {
1815 .qdev
.desc
= "Spice QXL GPU (secondary)",
1816 .qdev
.size
= sizeof(PCIQXLDevice
),
1817 .qdev
.reset
= qxl_reset_handler
,
1818 .qdev
.vmsd
= &qxl_vmstate
,
1819 .init
= qxl_init_secondary
,
1820 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1821 .device_id
= QXL_DEVICE_ID_STABLE
,
1822 .class_id
= PCI_CLASS_DISPLAY_OTHER
,
1823 .qdev
.props
= (Property
[]) {
1824 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
, 64 * 1024 * 1024),
1825 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
, 64 * 1024 * 1024),
1826 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
, 2),
1827 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1828 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1829 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1830 DEFINE_PROP_END_OF_LIST(),
1834 static void qxl_register(void)
1836 pci_qdev_register(&qxl_info_primary
);
1837 pci_qdev_register(&qxl_info_secondary
);
1840 device_init(qxl_register
);