2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu-common.h"
22 #include "qemu-timer.h"
23 #include "qemu-queue.h"
29 #undef SPICE_RING_PROD_ITEM
30 #define SPICE_RING_PROD_ITEM(r, ret) { \
31 typeof(r) start = r; \
32 typeof(r) end = r + 1; \
33 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
34 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
35 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
41 #undef SPICE_RING_CONS_ITEM
42 #define SPICE_RING_CONS_ITEM(r, ret) { \
43 typeof(r) start = r; \
44 typeof(r) end = r + 1; \
45 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
46 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
47 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
54 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
56 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
58 #define QXL_MODE(_x, _y, _b, _o) \
62 .stride = (_x) * (_b) / 8, \
63 .x_mili = PIXEL_SIZE * (_x), \
64 .y_mili = PIXEL_SIZE * (_y), \
68 #define QXL_MODE_16_32(x_res, y_res, orientation) \
69 QXL_MODE(x_res, y_res, 16, orientation), \
70 QXL_MODE(x_res, y_res, 32, orientation)
72 #define QXL_MODE_EX(x_res, y_res) \
73 QXL_MODE_16_32(x_res, y_res, 0), \
74 QXL_MODE_16_32(y_res, x_res, 1), \
75 QXL_MODE_16_32(x_res, y_res, 2), \
76 QXL_MODE_16_32(y_res, x_res, 3)
78 static QXLMode qxl_modes
[] = {
79 QXL_MODE_EX(640, 480),
80 QXL_MODE_EX(800, 480),
81 QXL_MODE_EX(800, 600),
82 QXL_MODE_EX(832, 624),
83 QXL_MODE_EX(960, 640),
84 QXL_MODE_EX(1024, 600),
85 QXL_MODE_EX(1024, 768),
86 QXL_MODE_EX(1152, 864),
87 QXL_MODE_EX(1152, 870),
88 QXL_MODE_EX(1280, 720),
89 QXL_MODE_EX(1280, 760),
90 QXL_MODE_EX(1280, 768),
91 QXL_MODE_EX(1280, 800),
92 QXL_MODE_EX(1280, 960),
93 QXL_MODE_EX(1280, 1024),
94 QXL_MODE_EX(1360, 768),
95 QXL_MODE_EX(1366, 768),
96 QXL_MODE_EX(1400, 1050),
97 QXL_MODE_EX(1440, 900),
98 QXL_MODE_EX(1600, 900),
99 QXL_MODE_EX(1600, 1200),
100 QXL_MODE_EX(1680, 1050),
101 QXL_MODE_EX(1920, 1080),
102 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
103 /* these modes need more than 8 MB video memory */
104 QXL_MODE_EX(1920, 1200),
105 QXL_MODE_EX(1920, 1440),
106 QXL_MODE_EX(2048, 1536),
107 QXL_MODE_EX(2560, 1440),
108 QXL_MODE_EX(2560, 1600),
110 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
111 /* these modes need more than 16 MB video memory */
112 QXL_MODE_EX(2560, 2048),
113 QXL_MODE_EX(2800, 2100),
114 QXL_MODE_EX(3200, 2400),
118 static PCIQXLDevice
*qxl0
;
120 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
);
121 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
);
122 static void qxl_reset_memslots(PCIQXLDevice
*d
);
123 static void qxl_reset_surfaces(PCIQXLDevice
*d
);
124 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
);
126 void qxl_guest_bug(PCIQXLDevice
*qxl
, const char *msg
, ...)
128 #if SPICE_INTERFACE_QXL_MINOR >= 1
129 qxl_send_events(qxl
, QXL_INTERRUPT_ERROR
);
131 if (qxl
->guestdebug
) {
134 fprintf(stderr
, "qxl-%d: guest bug: ", qxl
->id
);
135 vfprintf(stderr
, msg
, ap
);
136 fprintf(stderr
, "\n");
142 void qxl_spice_update_area(PCIQXLDevice
*qxl
, uint32_t surface_id
,
143 struct QXLRect
*area
, struct QXLRect
*dirty_rects
,
144 uint32_t num_dirty_rects
,
145 uint32_t clear_dirty_region
,
148 if (async
== QXL_SYNC
) {
149 qxl
->ssd
.worker
->update_area(qxl
->ssd
.worker
, surface_id
, area
,
150 dirty_rects
, num_dirty_rects
, clear_dirty_region
);
152 #if SPICE_INTERFACE_QXL_MINOR >= 1
153 spice_qxl_update_area_async(&qxl
->ssd
.qxl
, surface_id
, area
,
154 clear_dirty_region
, 0);
161 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice
*qxl
,
164 qemu_mutex_lock(&qxl
->track_lock
);
165 qxl
->guest_surfaces
.cmds
[id
] = 0;
166 qxl
->guest_surfaces
.count
--;
167 qemu_mutex_unlock(&qxl
->track_lock
);
170 static void qxl_spice_destroy_surface_wait(PCIQXLDevice
*qxl
, uint32_t id
,
174 #if SPICE_INTERFACE_QXL_MINOR < 1
177 spice_qxl_destroy_surface_async(&qxl
->ssd
.qxl
, id
,
181 qxl
->ssd
.worker
->destroy_surface_wait(qxl
->ssd
.worker
, id
);
182 qxl_spice_destroy_surface_wait_complete(qxl
, id
);
186 #if SPICE_INTERFACE_QXL_MINOR >= 1
187 static void qxl_spice_flush_surfaces_async(PCIQXLDevice
*qxl
)
189 spice_qxl_flush_surfaces_async(&qxl
->ssd
.qxl
, 0);
193 void qxl_spice_loadvm_commands(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
,
196 qxl
->ssd
.worker
->loadvm_commands(qxl
->ssd
.worker
, ext
, count
);
199 void qxl_spice_oom(PCIQXLDevice
*qxl
)
201 qxl
->ssd
.worker
->oom(qxl
->ssd
.worker
);
204 void qxl_spice_reset_memslots(PCIQXLDevice
*qxl
)
206 qxl
->ssd
.worker
->reset_memslots(qxl
->ssd
.worker
);
209 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice
*qxl
)
211 qemu_mutex_lock(&qxl
->track_lock
);
212 memset(&qxl
->guest_surfaces
.cmds
, 0, sizeof(qxl
->guest_surfaces
.cmds
));
213 qxl
->guest_surfaces
.count
= 0;
214 qemu_mutex_unlock(&qxl
->track_lock
);
217 static void qxl_spice_destroy_surfaces(PCIQXLDevice
*qxl
, qxl_async_io async
)
220 #if SPICE_INTERFACE_QXL_MINOR < 1
223 spice_qxl_destroy_surfaces_async(&qxl
->ssd
.qxl
, 0);
226 qxl
->ssd
.worker
->destroy_surfaces(qxl
->ssd
.worker
);
227 qxl_spice_destroy_surfaces_complete(qxl
);
231 void qxl_spice_reset_image_cache(PCIQXLDevice
*qxl
)
233 qxl
->ssd
.worker
->reset_image_cache(qxl
->ssd
.worker
);
236 void qxl_spice_reset_cursor(PCIQXLDevice
*qxl
)
238 qxl
->ssd
.worker
->reset_cursor(qxl
->ssd
.worker
);
242 static inline uint32_t msb_mask(uint32_t val
)
247 mask
= ~(val
- 1) & val
;
249 } while (mask
< val
);
254 static ram_addr_t
qxl_rom_size(void)
256 uint32_t rom_size
= sizeof(QXLRom
) + sizeof(QXLModes
) + sizeof(qxl_modes
);
257 rom_size
= MAX(rom_size
, TARGET_PAGE_SIZE
);
258 rom_size
= msb_mask(rom_size
* 2 - 1);
262 static void init_qxl_rom(PCIQXLDevice
*d
)
264 QXLRom
*rom
= memory_region_get_ram_ptr(&d
->rom_bar
);
265 QXLModes
*modes
= (QXLModes
*)(rom
+ 1);
266 uint32_t ram_header_size
;
267 uint32_t surface0_area_size
;
269 uint32_t fb
, maxfb
= 0;
272 memset(rom
, 0, d
->rom_size
);
274 rom
->magic
= cpu_to_le32(QXL_ROM_MAGIC
);
275 rom
->id
= cpu_to_le32(d
->id
);
276 rom
->log_level
= cpu_to_le32(d
->guestdebug
);
277 rom
->modes_offset
= cpu_to_le32(sizeof(QXLRom
));
279 rom
->slot_gen_bits
= MEMSLOT_GENERATION_BITS
;
280 rom
->slot_id_bits
= MEMSLOT_SLOT_BITS
;
281 rom
->slots_start
= 1;
282 rom
->slots_end
= NUM_MEMSLOTS
- 1;
283 rom
->n_surfaces
= cpu_to_le32(NUM_SURFACES
);
285 modes
->n_modes
= cpu_to_le32(ARRAY_SIZE(qxl_modes
));
286 for (i
= 0; i
< modes
->n_modes
; i
++) {
287 fb
= qxl_modes
[i
].y_res
* qxl_modes
[i
].stride
;
291 modes
->modes
[i
].id
= cpu_to_le32(i
);
292 modes
->modes
[i
].x_res
= cpu_to_le32(qxl_modes
[i
].x_res
);
293 modes
->modes
[i
].y_res
= cpu_to_le32(qxl_modes
[i
].y_res
);
294 modes
->modes
[i
].bits
= cpu_to_le32(qxl_modes
[i
].bits
);
295 modes
->modes
[i
].stride
= cpu_to_le32(qxl_modes
[i
].stride
);
296 modes
->modes
[i
].x_mili
= cpu_to_le32(qxl_modes
[i
].x_mili
);
297 modes
->modes
[i
].y_mili
= cpu_to_le32(qxl_modes
[i
].y_mili
);
298 modes
->modes
[i
].orientation
= cpu_to_le32(qxl_modes
[i
].orientation
);
300 if (maxfb
< VGA_RAM_SIZE
&& d
->id
== 0)
301 maxfb
= VGA_RAM_SIZE
;
303 ram_header_size
= ALIGN(sizeof(QXLRam
), 4096);
304 surface0_area_size
= ALIGN(maxfb
, 4096);
305 num_pages
= d
->vga
.vram_size
;
306 num_pages
-= ram_header_size
;
307 num_pages
-= surface0_area_size
;
308 num_pages
= num_pages
/ TARGET_PAGE_SIZE
;
310 rom
->draw_area_offset
= cpu_to_le32(0);
311 rom
->surface0_area_size
= cpu_to_le32(surface0_area_size
);
312 rom
->pages_offset
= cpu_to_le32(surface0_area_size
);
313 rom
->num_pages
= cpu_to_le32(num_pages
);
314 rom
->ram_header_offset
= cpu_to_le32(d
->vga
.vram_size
- ram_header_size
);
316 d
->shadow_rom
= *rom
;
321 static void init_qxl_ram(PCIQXLDevice
*d
)
326 buf
= d
->vga
.vram_ptr
;
327 d
->ram
= (QXLRam
*)(buf
+ le32_to_cpu(d
->shadow_rom
.ram_header_offset
));
328 d
->ram
->magic
= cpu_to_le32(QXL_RAM_MAGIC
);
329 d
->ram
->int_pending
= cpu_to_le32(0);
330 d
->ram
->int_mask
= cpu_to_le32(0);
331 SPICE_RING_INIT(&d
->ram
->cmd_ring
);
332 SPICE_RING_INIT(&d
->ram
->cursor_ring
);
333 SPICE_RING_INIT(&d
->ram
->release_ring
);
334 SPICE_RING_PROD_ITEM(&d
->ram
->release_ring
, item
);
336 qxl_ring_set_dirty(d
);
339 /* can be called from spice server thread context */
340 static void qxl_set_dirty(MemoryRegion
*mr
, ram_addr_t addr
, ram_addr_t end
)
343 memory_region_set_dirty(mr
, addr
);
344 addr
+= TARGET_PAGE_SIZE
;
348 static void qxl_rom_set_dirty(PCIQXLDevice
*qxl
)
350 qxl_set_dirty(&qxl
->rom_bar
, 0, qxl
->rom_size
);
353 /* called from spice server thread context only */
354 static void qxl_ram_set_dirty(PCIQXLDevice
*qxl
, void *ptr
)
356 void *base
= qxl
->vga
.vram_ptr
;
360 offset
&= ~(TARGET_PAGE_SIZE
-1);
361 assert(offset
< qxl
->vga
.vram_size
);
362 qxl_set_dirty(&qxl
->vga
.vram
, offset
, offset
+ TARGET_PAGE_SIZE
);
365 /* can be called from spice server thread context */
366 static void qxl_ring_set_dirty(PCIQXLDevice
*qxl
)
368 ram_addr_t addr
= qxl
->shadow_rom
.ram_header_offset
;
369 ram_addr_t end
= qxl
->vga
.vram_size
;
370 qxl_set_dirty(&qxl
->vga
.vram
, addr
, end
);
374 * keep track of some command state, for savevm/loadvm.
375 * called from spice server thread context only
377 static void qxl_track_command(PCIQXLDevice
*qxl
, struct QXLCommandExt
*ext
)
379 switch (le32_to_cpu(ext
->cmd
.type
)) {
380 case QXL_CMD_SURFACE
:
382 QXLSurfaceCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
383 uint32_t id
= le32_to_cpu(cmd
->surface_id
);
384 PANIC_ON(id
>= NUM_SURFACES
);
385 qemu_mutex_lock(&qxl
->track_lock
);
386 if (cmd
->type
== QXL_SURFACE_CMD_CREATE
) {
387 qxl
->guest_surfaces
.cmds
[id
] = ext
->cmd
.data
;
388 qxl
->guest_surfaces
.count
++;
389 if (qxl
->guest_surfaces
.max
< qxl
->guest_surfaces
.count
)
390 qxl
->guest_surfaces
.max
= qxl
->guest_surfaces
.count
;
392 if (cmd
->type
== QXL_SURFACE_CMD_DESTROY
) {
393 qxl
->guest_surfaces
.cmds
[id
] = 0;
394 qxl
->guest_surfaces
.count
--;
396 qemu_mutex_unlock(&qxl
->track_lock
);
401 QXLCursorCmd
*cmd
= qxl_phys2virt(qxl
, ext
->cmd
.data
, ext
->group_id
);
402 if (cmd
->type
== QXL_CURSOR_SET
) {
403 qxl
->guest_cursor
= ext
->cmd
.data
;
410 /* spice display interface callbacks */
412 static void interface_attach_worker(QXLInstance
*sin
, QXLWorker
*qxl_worker
)
414 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
416 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
417 qxl
->ssd
.worker
= qxl_worker
;
420 static void interface_set_compression_level(QXLInstance
*sin
, int level
)
422 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
424 dprint(qxl
, 1, "%s: %d\n", __FUNCTION__
, level
);
425 qxl
->shadow_rom
.compression_level
= cpu_to_le32(level
);
426 qxl
->rom
->compression_level
= cpu_to_le32(level
);
427 qxl_rom_set_dirty(qxl
);
430 static void interface_set_mm_time(QXLInstance
*sin
, uint32_t mm_time
)
432 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
434 qxl
->shadow_rom
.mm_clock
= cpu_to_le32(mm_time
);
435 qxl
->rom
->mm_clock
= cpu_to_le32(mm_time
);
436 qxl_rom_set_dirty(qxl
);
439 static void interface_get_init_info(QXLInstance
*sin
, QXLDevInitInfo
*info
)
441 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
443 dprint(qxl
, 1, "%s:\n", __FUNCTION__
);
444 info
->memslot_gen_bits
= MEMSLOT_GENERATION_BITS
;
445 info
->memslot_id_bits
= MEMSLOT_SLOT_BITS
;
446 info
->num_memslots
= NUM_MEMSLOTS
;
447 info
->num_memslots_groups
= NUM_MEMSLOTS_GROUPS
;
448 info
->internal_groupslot_id
= 0;
449 info
->qxl_ram_size
= le32_to_cpu(qxl
->shadow_rom
.num_pages
) << TARGET_PAGE_BITS
;
450 info
->n_surfaces
= NUM_SURFACES
;
453 static const char *qxl_mode_to_string(int mode
)
456 case QXL_MODE_COMPAT
:
458 case QXL_MODE_NATIVE
:
460 case QXL_MODE_UNDEFINED
:
468 static const char *io_port_to_string(uint32_t io_port
)
470 if (io_port
>= QXL_IO_RANGE_SIZE
) {
471 return "out of range";
473 static const char *io_port_to_string
[QXL_IO_RANGE_SIZE
+ 1] = {
474 [QXL_IO_NOTIFY_CMD
] = "QXL_IO_NOTIFY_CMD",
475 [QXL_IO_NOTIFY_CURSOR
] = "QXL_IO_NOTIFY_CURSOR",
476 [QXL_IO_UPDATE_AREA
] = "QXL_IO_UPDATE_AREA",
477 [QXL_IO_UPDATE_IRQ
] = "QXL_IO_UPDATE_IRQ",
478 [QXL_IO_NOTIFY_OOM
] = "QXL_IO_NOTIFY_OOM",
479 [QXL_IO_RESET
] = "QXL_IO_RESET",
480 [QXL_IO_SET_MODE
] = "QXL_IO_SET_MODE",
481 [QXL_IO_LOG
] = "QXL_IO_LOG",
482 [QXL_IO_MEMSLOT_ADD
] = "QXL_IO_MEMSLOT_ADD",
483 [QXL_IO_MEMSLOT_DEL
] = "QXL_IO_MEMSLOT_DEL",
484 [QXL_IO_DETACH_PRIMARY
] = "QXL_IO_DETACH_PRIMARY",
485 [QXL_IO_ATTACH_PRIMARY
] = "QXL_IO_ATTACH_PRIMARY",
486 [QXL_IO_CREATE_PRIMARY
] = "QXL_IO_CREATE_PRIMARY",
487 [QXL_IO_DESTROY_PRIMARY
] = "QXL_IO_DESTROY_PRIMARY",
488 [QXL_IO_DESTROY_SURFACE_WAIT
] = "QXL_IO_DESTROY_SURFACE_WAIT",
489 [QXL_IO_DESTROY_ALL_SURFACES
] = "QXL_IO_DESTROY_ALL_SURFACES",
490 #if SPICE_INTERFACE_QXL_MINOR >= 1
491 [QXL_IO_UPDATE_AREA_ASYNC
] = "QXL_IO_UPDATE_AREA_ASYNC",
492 [QXL_IO_MEMSLOT_ADD_ASYNC
] = "QXL_IO_MEMSLOT_ADD_ASYNC",
493 [QXL_IO_CREATE_PRIMARY_ASYNC
] = "QXL_IO_CREATE_PRIMARY_ASYNC",
494 [QXL_IO_DESTROY_PRIMARY_ASYNC
] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
495 [QXL_IO_DESTROY_SURFACE_ASYNC
] = "QXL_IO_DESTROY_SURFACE_ASYNC",
496 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC
]
497 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
498 [QXL_IO_FLUSH_SURFACES_ASYNC
] = "QXL_IO_FLUSH_SURFACES_ASYNC",
499 [QXL_IO_FLUSH_RELEASE
] = "QXL_IO_FLUSH_RELEASE",
502 return io_port_to_string
[io_port
];
505 /* called from spice server thread context only */
506 static int interface_get_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
508 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
509 SimpleSpiceUpdate
*update
;
510 QXLCommandRing
*ring
;
516 dprint(qxl
, 2, "%s: vga\n", __FUNCTION__
);
518 qemu_mutex_lock(&qxl
->ssd
.lock
);
519 if (qxl
->ssd
.update
!= NULL
) {
520 update
= qxl
->ssd
.update
;
521 qxl
->ssd
.update
= NULL
;
525 qemu_mutex_unlock(&qxl
->ssd
.lock
);
527 dprint(qxl
, 2, "%s %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
528 qxl_log_command(qxl
, "vga", ext
);
531 case QXL_MODE_COMPAT
:
532 case QXL_MODE_NATIVE
:
533 case QXL_MODE_UNDEFINED
:
534 dprint(qxl
, 4, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
535 ring
= &qxl
->ram
->cmd_ring
;
536 if (SPICE_RING_IS_EMPTY(ring
)) {
539 dprint(qxl
, 2, "%s: %s\n", __FUNCTION__
, qxl_mode_to_string(qxl
->mode
));
540 SPICE_RING_CONS_ITEM(ring
, cmd
);
542 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
543 ext
->flags
= qxl
->cmdflags
;
544 SPICE_RING_POP(ring
, notify
);
545 qxl_ring_set_dirty(qxl
);
547 qxl_send_events(qxl
, QXL_INTERRUPT_DISPLAY
);
549 qxl
->guest_primary
.commands
++;
550 qxl_track_command(qxl
, ext
);
551 qxl_log_command(qxl
, "cmd", ext
);
558 /* called from spice server thread context only */
559 static int interface_req_cmd_notification(QXLInstance
*sin
)
561 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
565 case QXL_MODE_COMPAT
:
566 case QXL_MODE_NATIVE
:
567 case QXL_MODE_UNDEFINED
:
568 SPICE_RING_CONS_WAIT(&qxl
->ram
->cmd_ring
, wait
);
569 qxl_ring_set_dirty(qxl
);
578 /* called from spice server thread context only */
579 static inline void qxl_push_free_res(PCIQXLDevice
*d
, int flush
)
581 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
585 #define QXL_FREE_BUNCH_SIZE 32
587 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
588 /* ring full -- can't push */
591 if (!flush
&& d
->oom_running
) {
592 /* collect everything from oom handler before pushing */
595 if (!flush
&& d
->num_free_res
< QXL_FREE_BUNCH_SIZE
) {
596 /* collect a bit more before pushing */
600 SPICE_RING_PUSH(ring
, notify
);
601 dprint(d
, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
602 d
->num_free_res
, notify
? "yes" : "no",
603 ring
->prod
- ring
->cons
, ring
->num_items
,
604 ring
->prod
, ring
->cons
);
606 qxl_send_events(d
, QXL_INTERRUPT_DISPLAY
);
608 SPICE_RING_PROD_ITEM(ring
, item
);
611 d
->last_release
= NULL
;
612 qxl_ring_set_dirty(d
);
615 /* called from spice server thread context only */
616 static void interface_release_resource(QXLInstance
*sin
,
617 struct QXLReleaseInfoExt ext
)
619 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
620 QXLReleaseRing
*ring
;
623 if (ext
.group_id
== MEMSLOT_GROUP_HOST
) {
624 /* host group -> vga mode update request */
625 qemu_spice_destroy_update(&qxl
->ssd
, (void*)ext
.info
->id
);
630 * ext->info points into guest-visible memory
631 * pci bar 0, $command.release_info
633 ring
= &qxl
->ram
->release_ring
;
634 SPICE_RING_PROD_ITEM(ring
, item
);
636 /* stick head into the ring */
639 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
641 qxl_ring_set_dirty(qxl
);
643 /* append item to the list */
644 qxl
->last_release
->next
= ext
.info
->id
;
645 qxl_ram_set_dirty(qxl
, &qxl
->last_release
->next
);
647 qxl_ram_set_dirty(qxl
, &ext
.info
->next
);
649 qxl
->last_release
= ext
.info
;
651 dprint(qxl
, 3, "%4d\r", qxl
->num_free_res
);
652 qxl_push_free_res(qxl
, 0);
655 /* called from spice server thread context only */
656 static int interface_get_cursor_command(QXLInstance
*sin
, struct QXLCommandExt
*ext
)
658 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
664 case QXL_MODE_COMPAT
:
665 case QXL_MODE_NATIVE
:
666 case QXL_MODE_UNDEFINED
:
667 ring
= &qxl
->ram
->cursor_ring
;
668 if (SPICE_RING_IS_EMPTY(ring
)) {
671 SPICE_RING_CONS_ITEM(ring
, cmd
);
673 ext
->group_id
= MEMSLOT_GROUP_GUEST
;
674 ext
->flags
= qxl
->cmdflags
;
675 SPICE_RING_POP(ring
, notify
);
676 qxl_ring_set_dirty(qxl
);
678 qxl_send_events(qxl
, QXL_INTERRUPT_CURSOR
);
680 qxl
->guest_primary
.commands
++;
681 qxl_track_command(qxl
, ext
);
682 qxl_log_command(qxl
, "csr", ext
);
684 qxl_render_cursor(qxl
, ext
);
692 /* called from spice server thread context only */
693 static int interface_req_cursor_notification(QXLInstance
*sin
)
695 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
699 case QXL_MODE_COMPAT
:
700 case QXL_MODE_NATIVE
:
701 case QXL_MODE_UNDEFINED
:
702 SPICE_RING_CONS_WAIT(&qxl
->ram
->cursor_ring
, wait
);
703 qxl_ring_set_dirty(qxl
);
712 /* called from spice server thread context */
713 static void interface_notify_update(QXLInstance
*sin
, uint32_t update_id
)
715 fprintf(stderr
, "%s: abort()\n", __FUNCTION__
);
719 /* called from spice server thread context only */
720 static int interface_flush_resources(QXLInstance
*sin
)
722 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
725 dprint(qxl
, 1, "free: guest flush (have %d)\n", qxl
->num_free_res
);
726 ret
= qxl
->num_free_res
;
728 qxl_push_free_res(qxl
, 1);
733 static void qxl_create_guest_primary_complete(PCIQXLDevice
*d
);
735 #if SPICE_INTERFACE_QXL_MINOR >= 1
737 /* called from spice server thread context only */
738 static void interface_async_complete(QXLInstance
*sin
, uint64_t cookie
)
740 PCIQXLDevice
*qxl
= container_of(sin
, PCIQXLDevice
, ssd
.qxl
);
741 uint32_t current_async
;
743 qemu_mutex_lock(&qxl
->async_lock
);
744 current_async
= qxl
->current_async
;
745 qxl
->current_async
= QXL_UNDEFINED_IO
;
746 qemu_mutex_unlock(&qxl
->async_lock
);
748 dprint(qxl
, 2, "async_complete: %d (%ld) done\n", current_async
, cookie
);
749 switch (current_async
) {
750 case QXL_IO_CREATE_PRIMARY_ASYNC
:
751 qxl_create_guest_primary_complete(qxl
);
753 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
754 qxl_spice_destroy_surfaces_complete(qxl
);
756 case QXL_IO_DESTROY_SURFACE_ASYNC
:
757 qxl_spice_destroy_surface_wait_complete(qxl
, (uint32_t)cookie
);
760 qxl_send_events(qxl
, QXL_INTERRUPT_IO_CMD
);
765 static const QXLInterface qxl_interface
= {
766 .base
.type
= SPICE_INTERFACE_QXL
,
767 .base
.description
= "qxl gpu",
768 .base
.major_version
= SPICE_INTERFACE_QXL_MAJOR
,
769 .base
.minor_version
= SPICE_INTERFACE_QXL_MINOR
,
771 .attache_worker
= interface_attach_worker
,
772 .set_compression_level
= interface_set_compression_level
,
773 .set_mm_time
= interface_set_mm_time
,
774 .get_init_info
= interface_get_init_info
,
776 /* the callbacks below are called from spice server thread context */
777 .get_command
= interface_get_command
,
778 .req_cmd_notification
= interface_req_cmd_notification
,
779 .release_resource
= interface_release_resource
,
780 .get_cursor_command
= interface_get_cursor_command
,
781 .req_cursor_notification
= interface_req_cursor_notification
,
782 .notify_update
= interface_notify_update
,
783 .flush_resources
= interface_flush_resources
,
784 #if SPICE_INTERFACE_QXL_MINOR >= 1
785 .async_complete
= interface_async_complete
,
789 static void qxl_enter_vga_mode(PCIQXLDevice
*d
)
791 if (d
->mode
== QXL_MODE_VGA
) {
794 dprint(d
, 1, "%s\n", __FUNCTION__
);
795 qemu_spice_create_host_primary(&d
->ssd
);
796 d
->mode
= QXL_MODE_VGA
;
797 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
800 static void qxl_exit_vga_mode(PCIQXLDevice
*d
)
802 if (d
->mode
!= QXL_MODE_VGA
) {
805 dprint(d
, 1, "%s\n", __FUNCTION__
);
806 qxl_destroy_primary(d
, QXL_SYNC
);
809 static void qxl_update_irq(PCIQXLDevice
*d
)
811 uint32_t pending
= le32_to_cpu(d
->ram
->int_pending
);
812 uint32_t mask
= le32_to_cpu(d
->ram
->int_mask
);
813 int level
= !!(pending
& mask
);
814 qemu_set_irq(d
->pci
.irq
[0], level
);
815 qxl_ring_set_dirty(d
);
818 static void qxl_check_state(PCIQXLDevice
*d
)
820 QXLRam
*ram
= d
->ram
;
822 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cmd_ring
));
823 assert(!d
->ssd
.running
|| SPICE_RING_IS_EMPTY(&ram
->cursor_ring
));
826 static void qxl_reset_state(PCIQXLDevice
*d
)
828 QXLRom
*rom
= d
->rom
;
831 d
->shadow_rom
.update_id
= cpu_to_le32(0);
832 *rom
= d
->shadow_rom
;
833 qxl_rom_set_dirty(d
);
836 d
->last_release
= NULL
;
837 memset(&d
->ssd
.dirty
, 0, sizeof(d
->ssd
.dirty
));
840 static void qxl_soft_reset(PCIQXLDevice
*d
)
842 dprint(d
, 1, "%s:\n", __FUNCTION__
);
846 qxl_enter_vga_mode(d
);
848 d
->mode
= QXL_MODE_UNDEFINED
;
852 static void qxl_hard_reset(PCIQXLDevice
*d
, int loadvm
)
854 dprint(d
, 1, "%s: start%s\n", __FUNCTION__
,
855 loadvm
? " (loadvm)" : "");
857 qxl_spice_reset_cursor(d
);
858 qxl_spice_reset_image_cache(d
);
859 qxl_reset_surfaces(d
);
860 qxl_reset_memslots(d
);
862 /* pre loadvm reset must not touch QXLRam. This lives in
863 * device memory, is migrated together with RAM and thus
864 * already loaded at this point */
868 qemu_spice_create_host_memslot(&d
->ssd
);
871 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
874 static void qxl_reset_handler(DeviceState
*dev
)
876 PCIQXLDevice
*d
= DO_UPCAST(PCIQXLDevice
, pci
.qdev
, dev
);
877 qxl_hard_reset(d
, 0);
880 static void qxl_vga_ioport_write(void *opaque
, uint32_t addr
, uint32_t val
)
882 VGACommonState
*vga
= opaque
;
883 PCIQXLDevice
*qxl
= container_of(vga
, PCIQXLDevice
, vga
);
885 if (qxl
->mode
!= QXL_MODE_VGA
) {
886 dprint(qxl
, 1, "%s\n", __FUNCTION__
);
887 qxl_destroy_primary(qxl
, QXL_SYNC
);
890 vga_ioport_write(opaque
, addr
, val
);
893 static void qxl_add_memslot(PCIQXLDevice
*d
, uint32_t slot_id
, uint64_t delta
,
896 static const int regions
[] = {
898 QXL_VRAM_RANGE_INDEX
,
900 uint64_t guest_start
;
906 QXLDevMemSlot memslot
;
909 guest_start
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_start
);
910 guest_end
= le64_to_cpu(d
->guest_slots
[slot_id
].slot
.mem_end
);
912 dprint(d
, 1, "%s: slot %d: guest phys 0x%" PRIx64
" - 0x%" PRIx64
"\n",
913 __FUNCTION__
, slot_id
,
914 guest_start
, guest_end
);
916 PANIC_ON(slot_id
>= NUM_MEMSLOTS
);
917 PANIC_ON(guest_start
> guest_end
);
919 for (i
= 0; i
< ARRAY_SIZE(regions
); i
++) {
920 pci_region
= regions
[i
];
921 pci_start
= d
->pci
.io_regions
[pci_region
].addr
;
922 pci_end
= pci_start
+ d
->pci
.io_regions
[pci_region
].size
;
924 if (pci_start
== -1) {
927 /* start address in range ? */
928 if (guest_start
< pci_start
|| guest_start
> pci_end
) {
931 /* end address in range ? */
932 if (guest_end
> pci_end
) {
938 PANIC_ON(i
== ARRAY_SIZE(regions
)); /* finished loop without match */
940 switch (pci_region
) {
941 case QXL_RAM_RANGE_INDEX
:
942 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vga
.vram
);
944 case QXL_VRAM_RANGE_INDEX
:
945 virt_start
= (intptr_t)memory_region_get_ram_ptr(&d
->vram_bar
);
948 /* should not happen */
952 memslot
.slot_id
= slot_id
;
953 memslot
.slot_group_id
= MEMSLOT_GROUP_GUEST
; /* guest group */
954 memslot
.virt_start
= virt_start
+ (guest_start
- pci_start
);
955 memslot
.virt_end
= virt_start
+ (guest_end
- pci_start
);
956 memslot
.addr_delta
= memslot
.virt_start
- delta
;
957 memslot
.generation
= d
->rom
->slot_generation
= 0;
958 qxl_rom_set_dirty(d
);
960 dprint(d
, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
961 __FUNCTION__
, memslot
.slot_id
,
962 memslot
.virt_start
, memslot
.virt_end
);
964 qemu_spice_add_memslot(&d
->ssd
, &memslot
, async
);
965 d
->guest_slots
[slot_id
].ptr
= (void*)memslot
.virt_start
;
966 d
->guest_slots
[slot_id
].size
= memslot
.virt_end
- memslot
.virt_start
;
967 d
->guest_slots
[slot_id
].delta
= delta
;
968 d
->guest_slots
[slot_id
].active
= 1;
971 static void qxl_del_memslot(PCIQXLDevice
*d
, uint32_t slot_id
)
973 dprint(d
, 1, "%s: slot %d\n", __FUNCTION__
, slot_id
);
974 qemu_spice_del_memslot(&d
->ssd
, MEMSLOT_GROUP_HOST
, slot_id
);
975 d
->guest_slots
[slot_id
].active
= 0;
978 static void qxl_reset_memslots(PCIQXLDevice
*d
)
980 dprint(d
, 1, "%s:\n", __FUNCTION__
);
981 qxl_spice_reset_memslots(d
);
982 memset(&d
->guest_slots
, 0, sizeof(d
->guest_slots
));
985 static void qxl_reset_surfaces(PCIQXLDevice
*d
)
987 dprint(d
, 1, "%s:\n", __FUNCTION__
);
988 d
->mode
= QXL_MODE_UNDEFINED
;
989 qxl_spice_destroy_surfaces(d
, QXL_SYNC
);
992 /* called from spice server thread context only */
993 void *qxl_phys2virt(PCIQXLDevice
*qxl
, QXLPHYSICAL pqxl
, int group_id
)
995 uint64_t phys
= le64_to_cpu(pqxl
);
996 uint32_t slot
= (phys
>> (64 - 8)) & 0xff;
997 uint64_t offset
= phys
& 0xffffffffffff;
1000 case MEMSLOT_GROUP_HOST
:
1001 return (void*)offset
;
1002 case MEMSLOT_GROUP_GUEST
:
1003 PANIC_ON(slot
> NUM_MEMSLOTS
);
1004 PANIC_ON(!qxl
->guest_slots
[slot
].active
);
1005 PANIC_ON(offset
< qxl
->guest_slots
[slot
].delta
);
1006 offset
-= qxl
->guest_slots
[slot
].delta
;
1007 PANIC_ON(offset
> qxl
->guest_slots
[slot
].size
)
1008 return qxl
->guest_slots
[slot
].ptr
+ offset
;
1014 static void qxl_create_guest_primary_complete(PCIQXLDevice
*qxl
)
1016 /* for local rendering */
1017 qxl_render_resize(qxl
);
1020 static void qxl_create_guest_primary(PCIQXLDevice
*qxl
, int loadvm
,
1023 QXLDevSurfaceCreate surface
;
1024 QXLSurfaceCreate
*sc
= &qxl
->guest_primary
.surface
;
1026 assert(qxl
->mode
!= QXL_MODE_NATIVE
);
1027 qxl_exit_vga_mode(qxl
);
1029 dprint(qxl
, 1, "%s: %dx%d\n", __FUNCTION__
,
1030 le32_to_cpu(sc
->width
), le32_to_cpu(sc
->height
));
1032 surface
.format
= le32_to_cpu(sc
->format
);
1033 surface
.height
= le32_to_cpu(sc
->height
);
1034 surface
.mem
= le64_to_cpu(sc
->mem
);
1035 surface
.position
= le32_to_cpu(sc
->position
);
1036 surface
.stride
= le32_to_cpu(sc
->stride
);
1037 surface
.width
= le32_to_cpu(sc
->width
);
1038 surface
.type
= le32_to_cpu(sc
->type
);
1039 surface
.flags
= le32_to_cpu(sc
->flags
);
1041 surface
.mouse_mode
= true;
1042 surface
.group_id
= MEMSLOT_GROUP_GUEST
;
1044 surface
.flags
|= QXL_SURF_FLAG_KEEP_DATA
;
1047 qxl
->mode
= QXL_MODE_NATIVE
;
1049 qemu_spice_create_primary_surface(&qxl
->ssd
, 0, &surface
, async
);
1051 if (async
== QXL_SYNC
) {
1052 qxl_create_guest_primary_complete(qxl
);
1056 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1057 * done (in QXL_SYNC case), 0 otherwise. */
1058 static int qxl_destroy_primary(PCIQXLDevice
*d
, qxl_async_io async
)
1060 if (d
->mode
== QXL_MODE_UNDEFINED
) {
1064 dprint(d
, 1, "%s\n", __FUNCTION__
);
1066 d
->mode
= QXL_MODE_UNDEFINED
;
1067 qemu_spice_destroy_primary_surface(&d
->ssd
, 0, async
);
1071 static void qxl_set_mode(PCIQXLDevice
*d
, int modenr
, int loadvm
)
1073 pcibus_t start
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1074 pcibus_t end
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].size
+ start
;
1075 QXLMode
*mode
= d
->modes
->modes
+ modenr
;
1076 uint64_t devmem
= d
->pci
.io_regions
[QXL_RAM_RANGE_INDEX
].addr
;
1081 QXLSurfaceCreate surface
= {
1082 .width
= mode
->x_res
,
1083 .height
= mode
->y_res
,
1084 .stride
= -mode
->x_res
* 4,
1085 .format
= SPICE_SURFACE_FMT_32_xRGB
,
1086 .flags
= loadvm
? QXL_SURF_FLAG_KEEP_DATA
: 0,
1088 .mem
= devmem
+ d
->shadow_rom
.draw_area_offset
,
1091 dprint(d
, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64
" ]\n",
1092 __func__
, modenr
, mode
->x_res
, mode
->y_res
, mode
->bits
, devmem
);
1094 qxl_hard_reset(d
, 0);
1097 d
->guest_slots
[0].slot
= slot
;
1098 qxl_add_memslot(d
, 0, devmem
, QXL_SYNC
);
1100 d
->guest_primary
.surface
= surface
;
1101 qxl_create_guest_primary(d
, 0, QXL_SYNC
);
1103 d
->mode
= QXL_MODE_COMPAT
;
1104 d
->cmdflags
= QXL_COMMAND_FLAG_COMPAT
;
1105 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1106 if (mode
->bits
== 16) {
1107 d
->cmdflags
|= QXL_COMMAND_FLAG_COMPAT_16BPP
;
1110 d
->shadow_rom
.mode
= cpu_to_le32(modenr
);
1111 d
->rom
->mode
= cpu_to_le32(modenr
);
1112 qxl_rom_set_dirty(d
);
1115 static void ioport_write(void *opaque
, target_phys_addr_t addr
,
1116 uint64_t val
, unsigned size
)
1118 PCIQXLDevice
*d
= opaque
;
1119 uint32_t io_port
= addr
;
1120 qxl_async_io async
= QXL_SYNC
;
1121 #if SPICE_INTERFACE_QXL_MINOR >= 1
1122 uint32_t orig_io_port
= io_port
;
1127 case QXL_IO_SET_MODE
:
1128 case QXL_IO_MEMSLOT_ADD
:
1129 case QXL_IO_MEMSLOT_DEL
:
1130 case QXL_IO_CREATE_PRIMARY
:
1131 case QXL_IO_UPDATE_IRQ
:
1133 #if SPICE_INTERFACE_QXL_MINOR >= 1
1134 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1135 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1139 if (d
->mode
!= QXL_MODE_VGA
) {
1142 dprint(d
, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1143 __func__
, io_port
, io_port_to_string(io_port
));
1144 #if SPICE_INTERFACE_QXL_MINOR >= 1
1145 /* be nice to buggy guest drivers */
1146 if (io_port
>= QXL_IO_UPDATE_AREA_ASYNC
&&
1147 io_port
<= QXL_IO_DESTROY_ALL_SURFACES_ASYNC
) {
1148 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1154 #if SPICE_INTERFACE_QXL_MINOR >= 1
1155 /* we change the io_port to avoid ifdeffery in the main switch */
1156 orig_io_port
= io_port
;
1158 case QXL_IO_UPDATE_AREA_ASYNC
:
1159 io_port
= QXL_IO_UPDATE_AREA
;
1161 case QXL_IO_MEMSLOT_ADD_ASYNC
:
1162 io_port
= QXL_IO_MEMSLOT_ADD
;
1164 case QXL_IO_CREATE_PRIMARY_ASYNC
:
1165 io_port
= QXL_IO_CREATE_PRIMARY
;
1167 case QXL_IO_DESTROY_PRIMARY_ASYNC
:
1168 io_port
= QXL_IO_DESTROY_PRIMARY
;
1170 case QXL_IO_DESTROY_SURFACE_ASYNC
:
1171 io_port
= QXL_IO_DESTROY_SURFACE_WAIT
;
1173 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC
:
1174 io_port
= QXL_IO_DESTROY_ALL_SURFACES
;
1176 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1179 qemu_mutex_lock(&d
->async_lock
);
1180 if (d
->current_async
!= QXL_UNDEFINED_IO
) {
1181 qxl_guest_bug(d
, "%d async started before last (%d) complete",
1182 io_port
, d
->current_async
);
1183 qemu_mutex_unlock(&d
->async_lock
);
1186 d
->current_async
= orig_io_port
;
1187 qemu_mutex_unlock(&d
->async_lock
);
1188 dprint(d
, 2, "start async %d (%"PRId64
")\n", io_port
, val
);
1196 case QXL_IO_UPDATE_AREA
:
1198 QXLRect update
= d
->ram
->update_area
;
1199 qxl_spice_update_area(d
, d
->ram
->update_surface
,
1200 &update
, NULL
, 0, 0, async
);
1203 case QXL_IO_NOTIFY_CMD
:
1204 qemu_spice_wakeup(&d
->ssd
);
1206 case QXL_IO_NOTIFY_CURSOR
:
1207 qemu_spice_wakeup(&d
->ssd
);
1209 case QXL_IO_UPDATE_IRQ
:
1212 case QXL_IO_NOTIFY_OOM
:
1213 if (!SPICE_RING_IS_EMPTY(&d
->ram
->release_ring
)) {
1220 case QXL_IO_SET_MODE
:
1221 dprint(d
, 1, "QXL_SET_MODE %d\n", (int)val
);
1222 qxl_set_mode(d
, val
, 0);
1225 if (d
->guestdebug
) {
1226 fprintf(stderr
, "qxl/guest-%d: %" PRId64
": %s", d
->id
,
1227 qemu_get_clock_ns(vm_clock
), d
->ram
->log_buf
);
1231 dprint(d
, 1, "QXL_IO_RESET\n");
1232 qxl_hard_reset(d
, 0);
1234 case QXL_IO_MEMSLOT_ADD
:
1235 if (val
>= NUM_MEMSLOTS
) {
1236 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: val out of range");
1239 if (d
->guest_slots
[val
].active
) {
1240 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1243 d
->guest_slots
[val
].slot
= d
->ram
->mem_slot
;
1244 qxl_add_memslot(d
, val
, 0, async
);
1246 case QXL_IO_MEMSLOT_DEL
:
1247 if (val
>= NUM_MEMSLOTS
) {
1248 qxl_guest_bug(d
, "QXL_IO_MEMSLOT_DEL: val out of range");
1251 qxl_del_memslot(d
, val
);
1253 case QXL_IO_CREATE_PRIMARY
:
1255 qxl_guest_bug(d
, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1259 dprint(d
, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async
);
1260 d
->guest_primary
.surface
= d
->ram
->create_surface
;
1261 qxl_create_guest_primary(d
, 0, async
);
1263 case QXL_IO_DESTROY_PRIMARY
:
1265 qxl_guest_bug(d
, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1269 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async
,
1270 qxl_mode_to_string(d
->mode
));
1271 if (!qxl_destroy_primary(d
, async
)) {
1272 dprint(d
, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1273 qxl_mode_to_string(d
->mode
));
1277 case QXL_IO_DESTROY_SURFACE_WAIT
:
1278 if (val
>= NUM_SURFACES
) {
1279 qxl_guest_bug(d
, "QXL_IO_DESTROY_SURFACE (async=%d):"
1280 "%d >= NUM_SURFACES", async
, val
);
1283 qxl_spice_destroy_surface_wait(d
, val
, async
);
1285 #if SPICE_INTERFACE_QXL_MINOR >= 1
1286 case QXL_IO_FLUSH_RELEASE
: {
1287 QXLReleaseRing
*ring
= &d
->ram
->release_ring
;
1288 if (ring
->prod
- ring
->cons
+ 1 == ring
->num_items
) {
1290 "ERROR: no flush, full release ring [p%d,%dc]\n",
1291 ring
->prod
, ring
->cons
);
1293 qxl_push_free_res(d
, 1 /* flush */);
1294 dprint(d
, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1295 qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1296 d
->num_free_res
, d
->last_release
);
1299 case QXL_IO_FLUSH_SURFACES_ASYNC
:
1300 dprint(d
, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1301 " (%"PRId64
") (%s, s#=%d, res#=%d)\n",
1302 val
, qxl_mode_to_string(d
->mode
), d
->guest_surfaces
.count
,
1304 qxl_spice_flush_surfaces_async(d
);
1307 case QXL_IO_DESTROY_ALL_SURFACES
:
1308 d
->mode
= QXL_MODE_UNDEFINED
;
1309 qxl_spice_destroy_surfaces(d
, async
);
1312 fprintf(stderr
, "%s: ioport=0x%x, abort()\n", __FUNCTION__
, io_port
);
1317 #if SPICE_INTERFACE_QXL_MINOR >= 1
1319 qxl_send_events(d
, QXL_INTERRUPT_IO_CMD
);
1320 qemu_mutex_lock(&d
->async_lock
);
1321 d
->current_async
= QXL_UNDEFINED_IO
;
1322 qemu_mutex_unlock(&d
->async_lock
);
1329 static uint64_t ioport_read(void *opaque
, target_phys_addr_t addr
,
1332 PCIQXLDevice
*d
= opaque
;
1334 dprint(d
, 1, "%s: unexpected\n", __FUNCTION__
);
1338 static const MemoryRegionOps qxl_io_ops
= {
1339 .read
= ioport_read
,
1340 .write
= ioport_write
,
1342 .min_access_size
= 1,
1343 .max_access_size
= 1,
1347 static void pipe_read(void *opaque
)
1349 PCIQXLDevice
*d
= opaque
;
1354 len
= read(d
->pipe
[0], &dummy
, sizeof(dummy
));
1355 } while (len
== sizeof(dummy
));
1359 static void qxl_send_events(PCIQXLDevice
*d
, uint32_t events
)
1361 uint32_t old_pending
;
1362 uint32_t le_events
= cpu_to_le32(events
);
1364 assert(d
->ssd
.running
);
1365 old_pending
= __sync_fetch_and_or(&d
->ram
->int_pending
, le_events
);
1366 if ((old_pending
& le_events
) == le_events
) {
1369 if (qemu_thread_is_self(&d
->main
)) {
1372 if (write(d
->pipe
[1], d
, 1) != 1) {
1373 dprint(d
, 1, "%s: write to pipe failed\n", __FUNCTION__
);
1378 static void init_pipe_signaling(PCIQXLDevice
*d
)
1380 if (pipe(d
->pipe
) < 0) {
1381 dprint(d
, 1, "%s: pipe creation failed\n", __FUNCTION__
);
1384 fcntl(d
->pipe
[0], F_SETFL
, O_NONBLOCK
);
1385 fcntl(d
->pipe
[1], F_SETFL
, O_NONBLOCK
);
1386 fcntl(d
->pipe
[0], F_SETOWN
, getpid());
1388 qemu_thread_get_self(&d
->main
);
1389 qemu_set_fd_handler(d
->pipe
[0], pipe_read
, NULL
, d
);
1392 /* graphics console */
1394 static void qxl_hw_update(void *opaque
)
1396 PCIQXLDevice
*qxl
= opaque
;
1397 VGACommonState
*vga
= &qxl
->vga
;
1399 switch (qxl
->mode
) {
1403 case QXL_MODE_COMPAT
:
1404 case QXL_MODE_NATIVE
:
1405 qxl_render_update(qxl
);
1412 static void qxl_hw_invalidate(void *opaque
)
1414 PCIQXLDevice
*qxl
= opaque
;
1415 VGACommonState
*vga
= &qxl
->vga
;
1417 vga
->invalidate(vga
);
1420 static void qxl_hw_screen_dump(void *opaque
, const char *filename
)
1422 PCIQXLDevice
*qxl
= opaque
;
1423 VGACommonState
*vga
= &qxl
->vga
;
1425 switch (qxl
->mode
) {
1426 case QXL_MODE_COMPAT
:
1427 case QXL_MODE_NATIVE
:
1428 qxl_render_update(qxl
);
1429 ppm_save(filename
, qxl
->ssd
.ds
->surface
);
1432 vga
->screen_dump(vga
, filename
);
1439 static void qxl_hw_text_update(void *opaque
, console_ch_t
*chardata
)
1441 PCIQXLDevice
*qxl
= opaque
;
1442 VGACommonState
*vga
= &qxl
->vga
;
1444 if (qxl
->mode
== QXL_MODE_VGA
) {
1445 vga
->text_update(vga
, chardata
);
1450 static void qxl_vm_change_state_handler(void *opaque
, int running
,
1453 PCIQXLDevice
*qxl
= opaque
;
1454 qemu_spice_vm_change_state_handler(&qxl
->ssd
, running
, state
);
1458 * if qxl_send_events was called from spice server context before
1459 * migration ended, qxl_update_irq for these events might not have been
1462 qxl_update_irq(qxl
);
1463 } else if (qxl
->mode
== QXL_MODE_NATIVE
) {
1464 /* dirty all vram (which holds surfaces) and devram (primary surface)
1465 * to make sure they are saved */
1466 /* FIXME #1: should go out during "live" stage */
1467 /* FIXME #2: we only need to save the areas which are actually used */
1468 qxl_set_dirty(&qxl
->vram_bar
, 0, qxl
->vram_size
);
1469 qxl_set_dirty(&qxl
->vga
.vram
, qxl
->shadow_rom
.draw_area_offset
,
1470 qxl
->shadow_rom
.surface0_area_size
);
1474 /* display change listener */
1476 static void display_update(struct DisplayState
*ds
, int x
, int y
, int w
, int h
)
1478 if (qxl0
->mode
== QXL_MODE_VGA
) {
1479 qemu_spice_display_update(&qxl0
->ssd
, x
, y
, w
, h
);
1483 static void display_resize(struct DisplayState
*ds
)
1485 if (qxl0
->mode
== QXL_MODE_VGA
) {
1486 qemu_spice_display_resize(&qxl0
->ssd
);
1490 static void display_refresh(struct DisplayState
*ds
)
1492 if (qxl0
->mode
== QXL_MODE_VGA
) {
1493 qemu_spice_display_refresh(&qxl0
->ssd
);
1497 static DisplayChangeListener display_listener
= {
1498 .dpy_update
= display_update
,
1499 .dpy_resize
= display_resize
,
1500 .dpy_refresh
= display_refresh
,
1503 static int qxl_init_common(PCIQXLDevice
*qxl
)
1505 uint8_t* config
= qxl
->pci
.config
;
1506 uint32_t pci_device_rev
;
1509 qxl
->mode
= QXL_MODE_UNDEFINED
;
1510 qxl
->generation
= 1;
1511 qxl
->num_memslots
= NUM_MEMSLOTS
;
1512 qxl
->num_surfaces
= NUM_SURFACES
;
1513 qemu_mutex_init(&qxl
->track_lock
);
1514 qemu_mutex_init(&qxl
->async_lock
);
1515 qxl
->current_async
= QXL_UNDEFINED_IO
;
1517 switch (qxl
->revision
) {
1518 case 1: /* spice 0.4 -- qxl-1 */
1519 pci_device_rev
= QXL_REVISION_STABLE_V04
;
1521 case 2: /* spice 0.6 -- qxl-2 */
1522 pci_device_rev
= QXL_REVISION_STABLE_V06
;
1524 #if SPICE_INTERFACE_QXL_MINOR >= 1
1528 pci_device_rev
= QXL_DEFAULT_REVISION
;
1532 pci_set_byte(&config
[PCI_REVISION_ID
], pci_device_rev
);
1533 pci_set_byte(&config
[PCI_INTERRUPT_PIN
], 1);
1535 qxl
->rom_size
= qxl_rom_size();
1536 memory_region_init_ram(&qxl
->rom_bar
, &qxl
->pci
.qdev
, "qxl.vrom",
1541 if (qxl
->vram_size
< 16 * 1024 * 1024) {
1542 qxl
->vram_size
= 16 * 1024 * 1024;
1544 if (qxl
->revision
== 1) {
1545 qxl
->vram_size
= 4096;
1547 qxl
->vram_size
= msb_mask(qxl
->vram_size
* 2 - 1);
1548 memory_region_init_ram(&qxl
->vram_bar
, &qxl
->pci
.qdev
, "qxl.vram",
1551 io_size
= msb_mask(QXL_IO_RANGE_SIZE
* 2 - 1);
1552 if (qxl
->revision
== 1) {
1556 memory_region_init_io(&qxl
->io_bar
, &qxl_io_ops
, qxl
,
1557 "qxl-ioports", io_size
);
1559 vga_dirty_log_start(&qxl
->vga
);
1563 pci_register_bar(&qxl
->pci
, QXL_IO_RANGE_INDEX
,
1564 PCI_BASE_ADDRESS_SPACE_IO
, &qxl
->io_bar
);
1566 pci_register_bar(&qxl
->pci
, QXL_ROM_RANGE_INDEX
,
1567 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->rom_bar
);
1569 pci_register_bar(&qxl
->pci
, QXL_RAM_RANGE_INDEX
,
1570 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vga
.vram
);
1572 pci_register_bar(&qxl
->pci
, QXL_VRAM_RANGE_INDEX
,
1573 PCI_BASE_ADDRESS_SPACE_MEMORY
, &qxl
->vram_bar
);
1575 qxl
->ssd
.qxl
.base
.sif
= &qxl_interface
.base
;
1576 qxl
->ssd
.qxl
.id
= qxl
->id
;
1577 qemu_spice_add_interface(&qxl
->ssd
.qxl
.base
);
1578 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler
, qxl
);
1580 init_pipe_signaling(qxl
);
1581 qxl_reset_state(qxl
);
1586 static int qxl_init_primary(PCIDevice
*dev
)
1588 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1589 VGACommonState
*vga
= &qxl
->vga
;
1590 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1594 if (ram_size
< 32 * 1024 * 1024) {
1595 ram_size
= 32 * 1024 * 1024;
1597 vga_common_init(vga
, ram_size
);
1598 vga_init(vga
, pci_address_space(dev
), pci_address_space_io(dev
), false);
1599 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write
, vga
);
1600 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write
, vga
);
1601 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write
, vga
);
1602 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write
, vga
);
1603 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write
, vga
);
1605 vga
->ds
= graphic_console_init(qxl_hw_update
, qxl_hw_invalidate
,
1606 qxl_hw_screen_dump
, qxl_hw_text_update
, qxl
);
1607 qemu_spice_display_init_common(&qxl
->ssd
, vga
->ds
);
1610 register_displaychangelistener(vga
->ds
, &display_listener
);
1612 return qxl_init_common(qxl
);
1615 static int qxl_init_secondary(PCIDevice
*dev
)
1617 static int device_id
= 1;
1618 PCIQXLDevice
*qxl
= DO_UPCAST(PCIQXLDevice
, pci
, dev
);
1619 ram_addr_t ram_size
= msb_mask(qxl
->vga
.vram_size
* 2 - 1);
1621 qxl
->id
= device_id
++;
1623 if (ram_size
< 16 * 1024 * 1024) {
1624 ram_size
= 16 * 1024 * 1024;
1626 qxl
->vga
.vram_size
= ram_size
;
1627 memory_region_init_ram(&qxl
->vga
.vram
, &qxl
->pci
.qdev
, "qxl.vgavram",
1628 qxl
->vga
.vram_size
);
1629 qxl
->vga
.vram_ptr
= memory_region_get_ram_ptr(&qxl
->vga
.vram
);
1631 return qxl_init_common(qxl
);
1634 static void qxl_pre_save(void *opaque
)
1636 PCIQXLDevice
* d
= opaque
;
1637 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1639 dprint(d
, 1, "%s:\n", __FUNCTION__
);
1640 if (d
->last_release
== NULL
) {
1641 d
->last_release_offset
= 0;
1643 d
->last_release_offset
= (uint8_t *)d
->last_release
- ram_start
;
1645 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1648 static int qxl_pre_load(void *opaque
)
1650 PCIQXLDevice
* d
= opaque
;
1652 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1653 qxl_hard_reset(d
, 1);
1654 qxl_exit_vga_mode(d
);
1655 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1659 static int qxl_post_load(void *opaque
, int version
)
1661 PCIQXLDevice
* d
= opaque
;
1662 uint8_t *ram_start
= d
->vga
.vram_ptr
;
1663 QXLCommandExt
*cmds
;
1664 int in
, out
, i
, newmode
;
1666 dprint(d
, 1, "%s: start\n", __FUNCTION__
);
1668 assert(d
->last_release_offset
< d
->vga
.vram_size
);
1669 if (d
->last_release_offset
== 0) {
1670 d
->last_release
= NULL
;
1672 d
->last_release
= (QXLReleaseInfo
*)(ram_start
+ d
->last_release_offset
);
1675 d
->modes
= (QXLModes
*)((uint8_t*)d
->rom
+ d
->rom
->modes_offset
);
1677 dprint(d
, 1, "%s: restore mode (%s)\n", __FUNCTION__
,
1678 qxl_mode_to_string(d
->mode
));
1680 d
->mode
= QXL_MODE_UNDEFINED
;
1682 case QXL_MODE_UNDEFINED
:
1685 qxl_enter_vga_mode(d
);
1687 case QXL_MODE_NATIVE
:
1688 for (i
= 0; i
< NUM_MEMSLOTS
; i
++) {
1689 if (!d
->guest_slots
[i
].active
) {
1692 qxl_add_memslot(d
, i
, 0, QXL_SYNC
);
1694 qxl_create_guest_primary(d
, 1, QXL_SYNC
);
1696 /* replay surface-create and cursor-set commands */
1697 cmds
= g_malloc0(sizeof(QXLCommandExt
) * (NUM_SURFACES
+ 1));
1698 for (in
= 0, out
= 0; in
< NUM_SURFACES
; in
++) {
1699 if (d
->guest_surfaces
.cmds
[in
] == 0) {
1702 cmds
[out
].cmd
.data
= d
->guest_surfaces
.cmds
[in
];
1703 cmds
[out
].cmd
.type
= QXL_CMD_SURFACE
;
1704 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1707 cmds
[out
].cmd
.data
= d
->guest_cursor
;
1708 cmds
[out
].cmd
.type
= QXL_CMD_CURSOR
;
1709 cmds
[out
].group_id
= MEMSLOT_GROUP_GUEST
;
1711 qxl_spice_loadvm_commands(d
, cmds
, out
);
1715 case QXL_MODE_COMPAT
:
1716 qxl_set_mode(d
, d
->shadow_rom
.mode
, 1);
1719 dprint(d
, 1, "%s: done\n", __FUNCTION__
);
1724 #define QXL_SAVE_VERSION 21
1726 static VMStateDescription qxl_memslot
= {
1727 .name
= "qxl-memslot",
1728 .version_id
= QXL_SAVE_VERSION
,
1729 .minimum_version_id
= QXL_SAVE_VERSION
,
1730 .fields
= (VMStateField
[]) {
1731 VMSTATE_UINT64(slot
.mem_start
, struct guest_slots
),
1732 VMSTATE_UINT64(slot
.mem_end
, struct guest_slots
),
1733 VMSTATE_UINT32(active
, struct guest_slots
),
1734 VMSTATE_END_OF_LIST()
1738 static VMStateDescription qxl_surface
= {
1739 .name
= "qxl-surface",
1740 .version_id
= QXL_SAVE_VERSION
,
1741 .minimum_version_id
= QXL_SAVE_VERSION
,
1742 .fields
= (VMStateField
[]) {
1743 VMSTATE_UINT32(width
, QXLSurfaceCreate
),
1744 VMSTATE_UINT32(height
, QXLSurfaceCreate
),
1745 VMSTATE_INT32(stride
, QXLSurfaceCreate
),
1746 VMSTATE_UINT32(format
, QXLSurfaceCreate
),
1747 VMSTATE_UINT32(position
, QXLSurfaceCreate
),
1748 VMSTATE_UINT32(mouse_mode
, QXLSurfaceCreate
),
1749 VMSTATE_UINT32(flags
, QXLSurfaceCreate
),
1750 VMSTATE_UINT32(type
, QXLSurfaceCreate
),
1751 VMSTATE_UINT64(mem
, QXLSurfaceCreate
),
1752 VMSTATE_END_OF_LIST()
1756 static VMStateDescription qxl_vmstate
= {
1758 .version_id
= QXL_SAVE_VERSION
,
1759 .minimum_version_id
= QXL_SAVE_VERSION
,
1760 .pre_save
= qxl_pre_save
,
1761 .pre_load
= qxl_pre_load
,
1762 .post_load
= qxl_post_load
,
1763 .fields
= (VMStateField
[]) {
1764 VMSTATE_PCI_DEVICE(pci
, PCIQXLDevice
),
1765 VMSTATE_STRUCT(vga
, PCIQXLDevice
, 0, vmstate_vga_common
, VGACommonState
),
1766 VMSTATE_UINT32(shadow_rom
.mode
, PCIQXLDevice
),
1767 VMSTATE_UINT32(num_free_res
, PCIQXLDevice
),
1768 VMSTATE_UINT32(last_release_offset
, PCIQXLDevice
),
1769 VMSTATE_UINT32(mode
, PCIQXLDevice
),
1770 VMSTATE_UINT32(ssd
.unique
, PCIQXLDevice
),
1771 VMSTATE_INT32_EQUAL(num_memslots
, PCIQXLDevice
),
1772 VMSTATE_STRUCT_ARRAY(guest_slots
, PCIQXLDevice
, NUM_MEMSLOTS
, 0,
1773 qxl_memslot
, struct guest_slots
),
1774 VMSTATE_STRUCT(guest_primary
.surface
, PCIQXLDevice
, 0,
1775 qxl_surface
, QXLSurfaceCreate
),
1776 VMSTATE_INT32_EQUAL(num_surfaces
, PCIQXLDevice
),
1777 VMSTATE_ARRAY(guest_surfaces
.cmds
, PCIQXLDevice
, NUM_SURFACES
, 0,
1778 vmstate_info_uint64
, uint64_t),
1779 VMSTATE_UINT64(guest_cursor
, PCIQXLDevice
),
1780 VMSTATE_END_OF_LIST()
1784 static Property qxl_properties
[] = {
1785 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice
, vga
.vram_size
,
1787 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice
, vram_size
,
1789 DEFINE_PROP_UINT32("revision", PCIQXLDevice
, revision
,
1790 QXL_DEFAULT_REVISION
),
1791 DEFINE_PROP_UINT32("debug", PCIQXLDevice
, debug
, 0),
1792 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice
, guestdebug
, 0),
1793 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice
, cmdlog
, 0),
1794 DEFINE_PROP_END_OF_LIST(),
1797 static PCIDeviceInfo qxl_info_primary
= {
1798 .qdev
.name
= "qxl-vga",
1799 .qdev
.desc
= "Spice QXL GPU (primary, vga compatible)",
1800 .qdev
.size
= sizeof(PCIQXLDevice
),
1801 .qdev
.reset
= qxl_reset_handler
,
1802 .qdev
.vmsd
= &qxl_vmstate
,
1804 .init
= qxl_init_primary
,
1805 .romfile
= "vgabios-qxl.bin",
1806 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1807 .device_id
= QXL_DEVICE_ID_STABLE
,
1808 .class_id
= PCI_CLASS_DISPLAY_VGA
,
1809 .qdev
.props
= qxl_properties
,
1812 static PCIDeviceInfo qxl_info_secondary
= {
1814 .qdev
.desc
= "Spice QXL GPU (secondary)",
1815 .qdev
.size
= sizeof(PCIQXLDevice
),
1816 .qdev
.reset
= qxl_reset_handler
,
1817 .qdev
.vmsd
= &qxl_vmstate
,
1818 .init
= qxl_init_secondary
,
1819 .vendor_id
= REDHAT_PCI_VENDOR_ID
,
1820 .device_id
= QXL_DEVICE_ID_STABLE
,
1821 .class_id
= PCI_CLASS_DISPLAY_OTHER
,
1822 .qdev
.props
= qxl_properties
,
1825 static void qxl_register(void)
1827 pci_qdev_register(&qxl_info_primary
);
1828 pci_qdev_register(&qxl_info_secondary
);
1831 device_init(qxl_register
);