hw/r2d.c

   1 /*
   2  * Renesas SH7751R R2D-PLUS emulation
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Copyright (c) 2008 Paul Mundt
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "hw.h"
  27 #include "sh.h"
  28 #include "devices.h"
  29 #include "sysemu.h"
  30 #include "boards.h"
  31 #include "pci.h"
  32 #include "net.h"
  33 #include "sh7750_regs.h"
  34 #include "ide.h"
  35
  36 #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
  37 #define SDRAM_SIZE 0x04000000
  38
  39 #define SM501_VRAM_SIZE 0x800000
  40
  41 /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
  42 #define LINUX_LOAD_OFFSET 0x800000
  43
  44 #define PA_IRLMSK       0x00
  45 #define PA_POWOFF       0x30
  46 #define PA_VERREG       0x32
  47 #define PA_OUTPORT      0x36
  48
  49 typedef struct {
  50     uint16_t bcr;
  51     uint16_t irlmsk;
  52     uint16_t irlmon;
  53     uint16_t cfctl;
  54     uint16_t cfpow;
  55     uint16_t dispctl;
  56     uint16_t sdmpow;
  57     uint16_t rtcce;
  58     uint16_t pcicd;
  59     uint16_t voyagerrts;
  60     uint16_t cfrst;
  61     uint16_t admrts;
  62     uint16_t extrst;
  63     uint16_t cfcdintclr;
  64     uint16_t keyctlclr;
  65     uint16_t pad0;
  66     uint16_t pad1;
  67     uint16_t powoff;
  68     uint16_t verreg;
  69     uint16_t inport;
  70     uint16_t outport;
  71     uint16_t bverreg;
  72
  73 /* output pin */
  74     qemu_irq irl;
  75 } r2d_fpga_t;
  76
  77 enum r2d_fpga_irq {
  78     PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
  79     SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
  80     NR_IRQS
  81 };
  82
  83 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
  84     [CF_IDE]    = {  1, 1<<9 },
  85     [CF_CD]     = {  2, 1<<8 },
  86     [PCI_INTA]  = {  9, 1<<14 },
  87     [PCI_INTB]  = { 10, 1<<13 },
  88     [PCI_INTC]  = {  3, 1<<12 },
  89     [PCI_INTD]  = {  0, 1<<11 },
  90     [SM501]     = {  4, 1<<10 },
  91     [KEY]       = {  5, 1<<6 },
  92     [RTC_A]     = {  6, 1<<5 },
  93     [RTC_T]     = {  7, 1<<4 },
  94     [SDCARD]    = {  8, 1<<7 },
  95     [EXT]       = { 11, 1<<0 },
  96     [TP]        = { 12, 1<<15 },
  97 };
  98
  99 static void update_irl(r2d_fpga_t *fpga)
 100 {
 101     int i, irl = 15;
 102     for (i = 0; i < NR_IRQS; i++)
 103         if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
 104             if (irqtab[i].irl < irl)
 105                 irl = irqtab[i].irl;
 106     qemu_set_irq(fpga->irl, irl ^ 15);
 107 }
 108
 109 static void r2d_fpga_irq_set(void *opaque, int n, int level)
 110 {
 111     r2d_fpga_t *fpga = opaque;
 112     if (level)
 113         fpga->irlmon |= irqtab[n].msk;
 114     else
 115         fpga->irlmon &= ~irqtab[n].msk;
 116     update_irl(fpga);
 117 }
 118
 119 static uint32_t r2d_fpga_read(void *opaque, target_phys_addr_t addr)
 120 {
 121     r2d_fpga_t *s = opaque;
 122
 123     switch (addr) {
 124     case PA_IRLMSK:
 125         return s->irlmsk;
 126     case PA_OUTPORT:
 127         return s->outport;
 128     case PA_POWOFF:
 129         return s->powoff;
 130     case PA_VERREG:
 131         return 0x10;
 132     }
 133
 134     return 0;
 135 }
 136
 137 static void
 138 r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value)
 139 {
 140     r2d_fpga_t *s = opaque;
 141
 142     switch (addr) {
 143     case PA_IRLMSK:
 144         s->irlmsk = value;
 145         update_irl(s);
 146         break;
 147     case PA_OUTPORT:
 148         s->outport = value;
 149         break;
 150     case PA_POWOFF:
 151         s->powoff = value;
 152         break;
 153     case PA_VERREG:
 154         /* Discard writes */
 155         break;
 156     }
 157 }
 158
 159 static CPUReadMemoryFunc * const r2d_fpga_readfn[] = {
 160     r2d_fpga_read,
 161     r2d_fpga_read,
 162     NULL,
 163 };
 164
 165 static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = {
 166     r2d_fpga_write,
 167     r2d_fpga_write,
 168     NULL,
 169 };
 170
 171 static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl)
 172 {
 173     int iomemtype;
 174     r2d_fpga_t *s;
 175
 176     s = qemu_mallocz(sizeof(r2d_fpga_t));
 177
 178     s->irl = irl;
 179
 180     iomemtype = cpu_register_io_memory(r2d_fpga_readfn,
 181                                        r2d_fpga_writefn, s);
 182     cpu_register_physical_memory(base, 0x40, iomemtype);
 183     return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
 184 }
 185
 186 static void r2d_pci_set_irq(qemu_irq *p, int n, int l)
 187 {
 188     qemu_set_irq(p[n], l);
 189 }
 190
 191 static int r2d_pci_map_irq(PCIDevice *d, int irq_num)
 192 {
 193     const int intx[] = { PCI_INTA, PCI_INTB, PCI_INTC, PCI_INTD };
 194     return intx[d->devfn >> 3];
 195 }
 196
 197 static void r2d_init(ram_addr_t ram_size,
 198               const char *boot_device,
 199               const char *kernel_filename, const char *kernel_cmdline,
 200               const char *initrd_filename, const char *cpu_model)
 201 {
 202     CPUState *env;
 203     struct SH7750State *s;
 204     ram_addr_t sdram_addr;
 205     qemu_irq *irq;
 206     PCIBus *pci;
 207     DriveInfo *dinfo;
 208     int i;
 209
 210     if (!cpu_model)
 211         cpu_model = "SH7751R";
 212
 213     env = cpu_init(cpu_model);
 214     if (!env) {
 215         fprintf(stderr, "Unable to find CPU definition\n");
 216         exit(1);
 217     }
 218
 219     /* Allocate memory space */
 220     sdram_addr = qemu_ram_alloc(SDRAM_SIZE);
 221     cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr);
 222     /* Register peripherals */
 223     s = sh7750_init(env);
 224     irq = r2d_fpga_init(0x04000000, sh7750_irl(s));
 225     pci = sh_pci_register_bus(r2d_pci_set_irq, r2d_pci_map_irq, irq, 0, 4);
 226
 227     sm501_init(0x10000000, SM501_VRAM_SIZE, irq[SM501], serial_hds[2]);
 228
 229     /* onboard CF (True IDE mode, Master only). */
 230     if ((dinfo = drive_get(IF_IDE, 0, 0)) != NULL)
 231         mmio_ide_init(0x14001000, 0x1400080c, irq[CF_IDE], 1,
 232                       dinfo->bdrv, NULL);
 233
 234     /* NIC: rtl8139 on-board, and 2 slots. */
 235     for (i = 0; i < nb_nics; i++)
 236         pci_nic_init(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
 237
 238     /* Todo: register on board registers */
 239     if (kernel_filename) {
 240       int kernel_size;
 241       /* initialization which should be done by firmware */
 242       stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
 243       stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
 244
 245       if (kernel_cmdline) {
 246           kernel_size = load_image_targphys(kernel_filename,
 247                                    SDRAM_BASE + LINUX_LOAD_OFFSET,
 248                                    SDRAM_SIZE - LINUX_LOAD_OFFSET);
 249           env->pc = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000;
 250           pstrcpy_targphys(SDRAM_BASE + 0x10100, 256, kernel_cmdline);
 251       } else {
 252           kernel_size = load_image_targphys(kernel_filename, SDRAM_BASE, SDRAM_SIZE);
 253           env->pc = SDRAM_BASE | 0xa0000000; /* Start from P2 area */
 254       }
 255
 256       if (kernel_size < 0) {
 257         fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
 258         exit(1);
 259       }
 260     }
 261 }
 262
 263 static QEMUMachine r2d_machine = {
 264     .name = "r2d",
 265     .desc = "r2d-plus board",
 266     .init = r2d_init,
 267 };
 268
 269 static void r2d_machine_init(void)
 270 {
 271     qemu_register_machine(&r2d_machine);
 272 }
 273
 274 machine_init(r2d_machine_init);