hw/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "primecell.h"
  13 #include "devices.h"
  14 #include "pci.h"
  15 #include "net.h"
  16 #include "sysemu.h"
  17 #include "boards.h"
  18
  19 #define SMP_BOOT_ADDR 0xe0000000
  20 /* Board init.  */
  21
  22 static struct arm_boot_info realview_binfo = {
  23     .smp_loader_start = SMP_BOOT_ADDR,
  24 };
  25
  26 static void secondary_cpu_reset(void *opaque)
  27 {
  28   CPUState *env = opaque;
  29
  30   cpu_reset(env);
  31   /* Set entry point for secondary CPUs.  This assumes we're using
  32      the init code from arm_boot.c.  Real hardware resets all CPUs
  33      the same.  */
  34   env->regs[15] = SMP_BOOT_ADDR;
  35 }
  36
  37 enum realview_board_type {
  38     BOARD_EB,
  39     BOARD_EB_MPCORE,
  40     BOARD_PB_A8
  41 };
  42
  43 static void realview_init(ram_addr_t ram_size,
  44                      const char *boot_device,
  45                      const char *kernel_filename, const char *kernel_cmdline,
  46                      const char *initrd_filename, const char *cpu_model,
  47                      enum realview_board_type board_type)
  48 {
  49     CPUState *env = NULL;
  50     ram_addr_t ram_offset;
  51     DeviceState *dev;
  52     SysBusDevice *busdev;
  53     qemu_irq *irqp;
  54     qemu_irq pic[64];
  55     PCIBus *pci_bus;
  56     NICInfo *nd;
  57     int n;
  58     int done_nic = 0;
  59     qemu_irq cpu_irq[4];
  60     int is_mpcore = (board_type == BOARD_EB_MPCORE);
  61     int is_pb = (board_type == BOARD_PB_A8);
  62     uint32_t proc_id = 0;
  63     uint32_t sys_id;
  64     ram_addr_t low_ram_size;
  65
  66     for (n = 0; n < smp_cpus; n++) {
  67         env = cpu_init(cpu_model);
  68         if (!env) {
  69             fprintf(stderr, "Unable to find CPU definition\n");
  70             exit(1);
  71         }
  72         irqp = arm_pic_init_cpu(env);
  73         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
  74         if (n > 0) {
  75             qemu_register_reset(secondary_cpu_reset, env);
  76         }
  77     }
  78     if (arm_feature(env, ARM_FEATURE_V7)) {
  79         proc_id = 0x0e000000;
  80     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
  81         proc_id = 0x06000000;
  82     } else if (arm_feature(env, ARM_FEATURE_V6)) {
  83         proc_id = 0x04000000;
  84     } else {
  85         proc_id = 0x02000000;
  86     }
  87
  88     ram_offset = qemu_ram_alloc(ram_size);
  89     low_ram_size = ram_size;
  90     if (low_ram_size > 0x10000000)
  91       low_ram_size = 0x10000000;
  92     /* ??? RAM should repeat to fill physical memory space.  */
  93     /* SDRAM at address zero.  */
  94     cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM);
  95     if (is_pb) {
  96         /* And again at a high address.  */
  97         cpu_register_physical_memory(0x70000000, ram_size,
  98                                      ram_offset | IO_MEM_RAM);
  99     } else {
 100         ram_size = low_ram_size;
 101     }
 102
 103     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 104     arm_sysctl_init(0x10000000, sys_id, proc_id);
 105
 106     if (is_mpcore) {
 107         dev = qdev_create(NULL, "realview_mpcore");
 108         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 109         qdev_init_nofail(dev);
 110         busdev = sysbus_from_qdev(dev);
 111         for (n = 0; n < smp_cpus; n++) {
 112             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 113         }
 114     } else {
 115         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 116         /* For now just create the nIRQ GIC, and ignore the others.  */
 117         dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
 118     }
 119     for (n = 0; n < 64; n++) {
 120         pic[n] = qdev_get_gpio_in(dev, n);
 121     }
 122
 123     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 124     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 125
 126     sysbus_create_simple("pl011", 0x10009000, pic[12]);
 127     sysbus_create_simple("pl011", 0x1000a000, pic[13]);
 128     sysbus_create_simple("pl011", 0x1000b000, pic[14]);
 129     sysbus_create_simple("pl011", 0x1000c000, pic[15]);
 130
 131     /* DMA controller is optional, apparently.  */
 132     sysbus_create_simple("pl081", 0x10030000, pic[24]);
 133
 134     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 135     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 136
 137     sysbus_create_simple("pl110_versatile", 0x10020000, pic[23]);
 138
 139     sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 140
 141     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 142
 143     if (!is_pb) {
 144         dev = sysbus_create_varargs("realview_pci", 0x60000000,
 145                                     pic[48], pic[49], pic[50], pic[51], NULL);
 146         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 147         if (usb_enabled) {
 148             usb_ohci_init_pci(pci_bus, -1);
 149         }
 150         n = drive_get_max_bus(IF_SCSI);
 151         while (n >= 0) {
 152             pci_create_simple(pci_bus, -1, "lsi53c895a");
 153             n--;
 154         }
 155     }
 156     for(n = 0; n < nb_nics; n++) {
 157         nd = &nd_table[n];
 158
 159         if ((!nd->model && !done_nic)
 160             || strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0) {
 161             if (is_pb) {
 162                 lan9118_init(nd, 0x4e000000, pic[28]);
 163             } else {
 164                 smc91c111_init(nd, 0x4e000000, pic[28]);
 165             }
 166             done_nic = 1;
 167         } else {
 168             pci_nic_init_nofail(nd, "rtl8139", NULL);
 169         }
 170     }
 171
 172     /* Memory map for RealView Emulation Baseboard:  */
 173     /* 0x10000000 System registers.  */
 174     /*  0x10001000 System controller.  */
 175     /*  0x10002000 Two-Wire Serial Bus.  */
 176     /* 0x10003000 Reserved.  */
 177     /*  0x10004000 AACI.  */
 178     /*  0x10005000 MCI.  */
 179     /* 0x10006000 KMI0.  */
 180     /* 0x10007000 KMI1.  */
 181     /*  0x10008000 Character LCD. (EB) */
 182     /* 0x10009000 UART0.  */
 183     /* 0x1000a000 UART1.  */
 184     /* 0x1000b000 UART2.  */
 185     /* 0x1000c000 UART3.  */
 186     /*  0x1000d000 SSPI.  */
 187     /*  0x1000e000 SCI.  */
 188     /* 0x1000f000 Reserved.  */
 189     /*  0x10010000 Watchdog.  */
 190     /* 0x10011000 Timer 0+1.  */
 191     /* 0x10012000 Timer 2+3.  */
 192     /*  0x10013000 GPIO 0.  */
 193     /*  0x10014000 GPIO 1.  */
 194     /*  0x10015000 GPIO 2.  */
 195     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 196     /* 0x10017000 RTC.  */
 197     /*  0x10018000 DMC.  */
 198     /*  0x10019000 PCI controller config.  */
 199     /*  0x10020000 CLCD.  */
 200     /* 0x10030000 DMA Controller.  */
 201     /* 0x10040000 GIC1. (EB) */
 202     /*  0x10050000 GIC2. (EB) */
 203     /*  0x10060000 GIC3. (EB) */
 204     /*  0x10070000 GIC4. (EB) */
 205     /*  0x10080000 SMC.  */
 206     /* 0x1e000000 GIC1. (PB) */
 207     /*  0x1e001000 GIC2. (PB) */
 208     /*  0x1e002000 GIC3. (PB) */
 209     /*  0x1e003000 GIC4. (PB) */
 210     /*  0x40000000 NOR flash.  */
 211     /*  0x44000000 DoC flash.  */
 212     /*  0x48000000 SRAM.  */
 213     /*  0x4c000000 Configuration flash.  */
 214     /* 0x4e000000 Ethernet.  */
 215     /*  0x4f000000 USB.  */
 216     /*  0x50000000 PISMO.  */
 217     /*  0x54000000 PISMO.  */
 218     /*  0x58000000 PISMO.  */
 219     /*  0x5c000000 PISMO.  */
 220     /* 0x60000000 PCI.  */
 221     /* 0x61000000 PCI Self Config.  */
 222     /* 0x62000000 PCI Config.  */
 223     /* 0x63000000 PCI IO.  */
 224     /* 0x64000000 PCI mem 0.  */
 225     /* 0x68000000 PCI mem 1.  */
 226     /* 0x6c000000 PCI mem 2.  */
 227
 228     /* ??? Hack to map an additional page of ram for the secondary CPU
 229        startup code.  I guess this works on real hardware because the
 230        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 231        until after Linux boots the secondary CPUs.  */
 232     ram_offset = qemu_ram_alloc(0x1000);
 233     cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000,
 234                                  ram_offset | IO_MEM_RAM);
 235
 236     realview_binfo.ram_size = ram_size;
 237     realview_binfo.kernel_filename = kernel_filename;
 238     realview_binfo.kernel_cmdline = kernel_cmdline;
 239     realview_binfo.initrd_filename = initrd_filename;
 240     realview_binfo.nb_cpus = smp_cpus;
 241     realview_binfo.board_id = is_pb ? 0x769 : 0x33b;
 242     realview_binfo.loader_start = is_pb ? 0x70000000 : 0;
 243     arm_load_kernel(first_cpu, &realview_binfo);
 244 }
 245
 246 static void realview_eb_init(ram_addr_t ram_size,
 247                      const char *boot_device,
 248                      const char *kernel_filename, const char *kernel_cmdline,
 249                      const char *initrd_filename, const char *cpu_model)
 250 {
 251     if (!cpu_model) {
 252         cpu_model = "arm926";
 253     }
 254     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 255                   initrd_filename, cpu_model, BOARD_EB);
 256 }
 257
 258 static void realview_eb_mpcore_init(ram_addr_t ram_size,
 259                      const char *boot_device,
 260                      const char *kernel_filename, const char *kernel_cmdline,
 261                      const char *initrd_filename, const char *cpu_model)
 262 {
 263     if (!cpu_model) {
 264         cpu_model = "arm11mpcore";
 265     }
 266     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 267                   initrd_filename, cpu_model, BOARD_EB_MPCORE);
 268 }
 269
 270 static void realview_pb_a8_init(ram_addr_t ram_size,
 271                      const char *boot_device,
 272                      const char *kernel_filename, const char *kernel_cmdline,
 273                      const char *initrd_filename, const char *cpu_model)
 274 {
 275     if (!cpu_model) {
 276         cpu_model = "cortex-a8";
 277     }
 278     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 279                   initrd_filename, cpu_model, BOARD_PB_A8);
 280 }
 281
 282 static QEMUMachine realview_eb_machine = {
 283     .name = "realview-eb",
 284     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
 285     .init = realview_eb_init,
 286     .use_scsi = 1,
 287 };
 288
 289 static QEMUMachine realview_eb_mpcore_machine = {
 290     .name = "realview-eb-mpcore",
 291     .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
 292     .init = realview_eb_mpcore_init,
 293     .use_scsi = 1,
 294     .max_cpus = 4,
 295 };
 296
 297 static QEMUMachine realview_pb_a8_machine = {
 298     .name = "realview-pb-a8",
 299     .desc = "ARM RealView Platform Baseboard for Cortex-A8",
 300     .init = realview_pb_a8_init,
 301     .use_scsi = 1,
 302 };
 303
 304 static void realview_machine_init(void)
 305 {
 306     qemu_register_machine(&realview_eb_machine);
 307     qemu_register_machine(&realview_eb_mpcore_machine);
 308     qemu_register_machine(&realview_pb_a8_machine);
 309 }
 310
 311 machine_init(realview_machine_init);