hw/realview.c

   1 /*
   2  * ARM RealView Baseboard System emulation.
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "primecell.h"
  13 #include "devices.h"
  14 #include "pci.h"
  15 #include "usb-ohci.h"
  16 #include "net.h"
  17 #include "sysemu.h"
  18 #include "boards.h"
  19 #include "bitbang_i2c.h"
  20 #include "blockdev.h"
  21 #include "exec-memory.h"
  22
  23 #define SMP_BOOT_ADDR 0xe0000000
  24
  25 typedef struct {
  26     SysBusDevice busdev;
  27     MemoryRegion iomem;
  28     bitbang_i2c_interface *bitbang;
  29     int out;
  30     int in;
  31 } RealViewI2CState;
  32
  33 static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset,
  34                                   unsigned size)
  35 {
  36     RealViewI2CState *s = (RealViewI2CState *)opaque;
  37
  38     if (offset == 0) {
  39         return (s->out & 1) | (s->in << 1);
  40     } else {
  41         hw_error("realview_i2c_read: Bad offset 0x%x\n", (int)offset);
  42         return -1;
  43     }
  44 }
  45
  46 static void realview_i2c_write(void *opaque, target_phys_addr_t offset,
  47                                uint64_t value, unsigned size)
  48 {
  49     RealViewI2CState *s = (RealViewI2CState *)opaque;
  50
  51     switch (offset) {
  52     case 0:
  53         s->out |= value & 3;
  54         break;
  55     case 4:
  56         s->out &= ~value;
  57         break;
  58     default:
  59         hw_error("realview_i2c_write: Bad offset 0x%x\n", (int)offset);
  60     }
  61     bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0);
  62     s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0);
  63 }
  64
  65 static const MemoryRegionOps realview_i2c_ops = {
  66     .read = realview_i2c_read,
  67     .write = realview_i2c_write,
  68     .endianness = DEVICE_NATIVE_ENDIAN,
  69 };
  70
  71 static int realview_i2c_init(SysBusDevice *dev)
  72 {
  73     RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev);
  74     i2c_bus *bus;
  75
  76     bus = i2c_init_bus(&dev->qdev, "i2c");
  77     s->bitbang = bitbang_i2c_init(bus);
  78     memory_region_init_io(&s->iomem, &realview_i2c_ops, s,
  79                           "realview-i2c", 0x1000);
  80     sysbus_init_mmio(dev, &s->iomem);
  81     return 0;
  82 }
  83
  84 static SysBusDeviceInfo realview_i2c_info = {
  85     .init = realview_i2c_init,
  86     .qdev.name  = "realview_i2c",
  87     .qdev.size  = sizeof(RealViewI2CState),
  88 };
  89
  90 static void realview_register_devices(void)
  91 {
  92     sysbus_register_withprop(&realview_i2c_info);
  93 }
  94
  95 /* Board init.  */
  96
  97 static struct arm_boot_info realview_binfo = {
  98     .smp_loader_start = SMP_BOOT_ADDR,
  99 };
 100
 101 /* The following two lists must be consistent.  */
 102 enum realview_board_type {
 103     BOARD_EB,
 104     BOARD_EB_MPCORE,
 105     BOARD_PB_A8,
 106     BOARD_PBX_A9,
 107 };
 108
 109 static const int realview_board_id[] = {
 110     0x33b,
 111     0x33b,
 112     0x769,
 113     0x76d
 114 };
 115
 116 static void realview_init(ram_addr_t ram_size,
 117                      const char *boot_device,
 118                      const char *kernel_filename, const char *kernel_cmdline,
 119                      const char *initrd_filename, const char *cpu_model,
 120                      enum realview_board_type board_type)
 121 {
 122     CPUState *env = NULL;
 123     MemoryRegion *sysmem = get_system_memory();
 124     MemoryRegion *ram_lo = g_new(MemoryRegion, 1);
 125     MemoryRegion *ram_hi = g_new(MemoryRegion, 1);
 126     MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
 127     MemoryRegion *ram_hack = g_new(MemoryRegion, 1);
 128     DeviceState *dev, *sysctl, *gpio2, *pl041;
 129     SysBusDevice *busdev;
 130     qemu_irq *irqp;
 131     qemu_irq pic[64];
 132     qemu_irq mmc_irq[2];
 133     PCIBus *pci_bus;
 134     NICInfo *nd;
 135     i2c_bus *i2c;
 136     int n;
 137     int done_nic = 0;
 138     qemu_irq cpu_irq[4];
 139     int is_mpcore = 0;
 140     int is_pb = 0;
 141     uint32_t proc_id = 0;
 142     uint32_t sys_id;
 143     ram_addr_t low_ram_size;
 144
 145     switch (board_type) {
 146     case BOARD_EB:
 147         break;
 148     case BOARD_EB_MPCORE:
 149         is_mpcore = 1;
 150         break;
 151     case BOARD_PB_A8:
 152         is_pb = 1;
 153         break;
 154     case BOARD_PBX_A9:
 155         is_mpcore = 1;
 156         is_pb = 1;
 157         break;
 158     }
 159     for (n = 0; n < smp_cpus; n++) {
 160         env = cpu_init(cpu_model);
 161         if (!env) {
 162             fprintf(stderr, "Unable to find CPU definition\n");
 163             exit(1);
 164         }
 165         irqp = arm_pic_init_cpu(env);
 166         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 167     }
 168     if (arm_feature(env, ARM_FEATURE_V7)) {
 169         if (is_mpcore) {
 170             proc_id = 0x0c000000;
 171         } else {
 172             proc_id = 0x0e000000;
 173         }
 174     } else if (arm_feature(env, ARM_FEATURE_V6K)) {
 175         proc_id = 0x06000000;
 176     } else if (arm_feature(env, ARM_FEATURE_V6)) {
 177         proc_id = 0x04000000;
 178     } else {
 179         proc_id = 0x02000000;
 180     }
 181
 182     if (is_pb && ram_size > 0x20000000) {
 183         /* Core tile RAM.  */
 184         low_ram_size = ram_size - 0x20000000;
 185         ram_size = 0x20000000;
 186         memory_region_init_ram(ram_lo, "realview.lowmem", low_ram_size);
 187         vmstate_register_ram_global(ram_lo);
 188         memory_region_add_subregion(sysmem, 0x20000000, ram_lo);
 189     }
 190
 191     memory_region_init_ram(ram_hi, "realview.highmem", ram_size);
 192     vmstate_register_ram_global(ram_hi);
 193     low_ram_size = ram_size;
 194     if (low_ram_size > 0x10000000)
 195       low_ram_size = 0x10000000;
 196     /* SDRAM at address zero.  */
 197     memory_region_init_alias(ram_alias, "realview.alias",
 198                              ram_hi, 0, low_ram_size);
 199     memory_region_add_subregion(sysmem, 0, ram_alias);
 200     if (is_pb) {
 201         /* And again at a high address.  */
 202         memory_region_add_subregion(sysmem, 0x70000000, ram_hi);
 203     } else {
 204         ram_size = low_ram_size;
 205     }
 206
 207     sys_id = is_pb ? 0x01780500 : 0xc1400400;
 208     sysctl = qdev_create(NULL, "realview_sysctl");
 209     qdev_prop_set_uint32(sysctl, "sys_id", sys_id);
 210     qdev_init_nofail(sysctl);
 211     qdev_prop_set_uint32(sysctl, "proc_id", proc_id);
 212     sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
 213
 214     if (is_mpcore) {
 215         dev = qdev_create(NULL, is_pb ? "a9mpcore_priv": "realview_mpcore");
 216         qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 217         qdev_init_nofail(dev);
 218         busdev = sysbus_from_qdev(dev);
 219         if (is_pb) {
 220             realview_binfo.smp_priv_base = 0x1f000000;
 221         } else {
 222             realview_binfo.smp_priv_base = 0x10100000;
 223         }
 224         sysbus_mmio_map(busdev, 0, realview_binfo.smp_priv_base);
 225         for (n = 0; n < smp_cpus; n++) {
 226             sysbus_connect_irq(busdev, n, cpu_irq[n]);
 227         }
 228     } else {
 229         uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000;
 230         /* For now just create the nIRQ GIC, and ignore the others.  */
 231         dev = sysbus_create_simple("realview_gic", gic_addr, cpu_irq[0]);
 232     }
 233     for (n = 0; n < 64; n++) {
 234         pic[n] = qdev_get_gpio_in(dev, n);
 235     }
 236
 237     pl041 = qdev_create(NULL, "pl041");
 238     qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
 239     qdev_init_nofail(pl041);
 240     sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
 241     sysbus_connect_irq(sysbus_from_qdev(pl041), 0, pic[19]);
 242
 243     sysbus_create_simple("pl050_keyboard", 0x10006000, pic[20]);
 244     sysbus_create_simple("pl050_mouse", 0x10007000, pic[21]);
 245
 246     sysbus_create_simple("pl011", 0x10009000, pic[12]);
 247     sysbus_create_simple("pl011", 0x1000a000, pic[13]);
 248     sysbus_create_simple("pl011", 0x1000b000, pic[14]);
 249     sysbus_create_simple("pl011", 0x1000c000, pic[15]);
 250
 251     /* DMA controller is optional, apparently.  */
 252     sysbus_create_simple("pl081", 0x10030000, pic[24]);
 253
 254     sysbus_create_simple("sp804", 0x10011000, pic[4]);
 255     sysbus_create_simple("sp804", 0x10012000, pic[5]);
 256
 257     sysbus_create_simple("pl061", 0x10013000, pic[6]);
 258     sysbus_create_simple("pl061", 0x10014000, pic[7]);
 259     gpio2 = sysbus_create_simple("pl061", 0x10015000, pic[8]);
 260
 261     sysbus_create_simple("pl111", 0x10020000, pic[23]);
 262
 263     dev = sysbus_create_varargs("pl181", 0x10005000, pic[17], pic[18], NULL);
 264     /* Wire up MMC card detect and read-only signals. These have
 265      * to go to both the PL061 GPIO and the sysctl register.
 266      * Note that the PL181 orders these lines (readonly,inserted)
 267      * and the PL061 has them the other way about. Also the card
 268      * detect line is inverted.
 269      */
 270     mmc_irq[0] = qemu_irq_split(
 271         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT),
 272         qdev_get_gpio_in(gpio2, 1));
 273     mmc_irq[1] = qemu_irq_split(
 274         qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN),
 275         qemu_irq_invert(qdev_get_gpio_in(gpio2, 0)));
 276     qdev_connect_gpio_out(dev, 0, mmc_irq[0]);
 277     qdev_connect_gpio_out(dev, 1, mmc_irq[1]);
 278
 279     sysbus_create_simple("pl031", 0x10017000, pic[10]);
 280
 281     if (!is_pb) {
 282         dev = qdev_create(NULL, "realview_pci");
 283         busdev = sysbus_from_qdev(dev);
 284         qdev_init_nofail(dev);
 285         sysbus_mmio_map(busdev, 0, 0x61000000); /* PCI self-config */
 286         sysbus_mmio_map(busdev, 1, 0x62000000); /* PCI config */
 287         sysbus_mmio_map(busdev, 2, 0x63000000); /* PCI I/O */
 288         sysbus_connect_irq(busdev, 0, pic[48]);
 289         sysbus_connect_irq(busdev, 1, pic[49]);
 290         sysbus_connect_irq(busdev, 2, pic[50]);
 291         sysbus_connect_irq(busdev, 3, pic[51]);
 292         pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 293         if (usb_enabled) {
 294             usb_ohci_init_pci(pci_bus, -1);
 295         }
 296         n = drive_get_max_bus(IF_SCSI);
 297         while (n >= 0) {
 298             pci_create_simple(pci_bus, -1, "lsi53c895a");
 299             n--;
 300         }
 301     }
 302     for(n = 0; n < nb_nics; n++) {
 303         nd = &nd_table[n];
 304
 305         if (!done_nic && (!nd->model ||
 306                     strcmp(nd->model, is_pb ? "lan9118" : "smc91c111") == 0)) {
 307             if (is_pb) {
 308                 lan9118_init(nd, 0x4e000000, pic[28]);
 309             } else {
 310                 smc91c111_init(nd, 0x4e000000, pic[28]);
 311             }
 312             done_nic = 1;
 313         } else {
 314             pci_nic_init_nofail(nd, "rtl8139", NULL);
 315         }
 316     }
 317
 318     dev = sysbus_create_simple("realview_i2c", 0x10002000, NULL);
 319     i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
 320     i2c_create_slave(i2c, "ds1338", 0x68);
 321
 322     /* Memory map for RealView Emulation Baseboard:  */
 323     /* 0x10000000 System registers.  */
 324     /*  0x10001000 System controller.  */
 325     /* 0x10002000 Two-Wire Serial Bus.  */
 326     /* 0x10003000 Reserved.  */
 327     /*  0x10004000 AACI.  */
 328     /*  0x10005000 MCI.  */
 329     /* 0x10006000 KMI0.  */
 330     /* 0x10007000 KMI1.  */
 331     /*  0x10008000 Character LCD. (EB) */
 332     /* 0x10009000 UART0.  */
 333     /* 0x1000a000 UART1.  */
 334     /* 0x1000b000 UART2.  */
 335     /* 0x1000c000 UART3.  */
 336     /*  0x1000d000 SSPI.  */
 337     /*  0x1000e000 SCI.  */
 338     /* 0x1000f000 Reserved.  */
 339     /*  0x10010000 Watchdog.  */
 340     /* 0x10011000 Timer 0+1.  */
 341     /* 0x10012000 Timer 2+3.  */
 342     /*  0x10013000 GPIO 0.  */
 343     /*  0x10014000 GPIO 1.  */
 344     /*  0x10015000 GPIO 2.  */
 345     /*  0x10002000 Two-Wire Serial Bus - DVI. (PB) */
 346     /* 0x10017000 RTC.  */
 347     /*  0x10018000 DMC.  */
 348     /*  0x10019000 PCI controller config.  */
 349     /*  0x10020000 CLCD.  */
 350     /* 0x10030000 DMA Controller.  */
 351     /* 0x10040000 GIC1. (EB) */
 352     /*  0x10050000 GIC2. (EB) */
 353     /*  0x10060000 GIC3. (EB) */
 354     /*  0x10070000 GIC4. (EB) */
 355     /*  0x10080000 SMC.  */
 356     /* 0x1e000000 GIC1. (PB) */
 357     /*  0x1e001000 GIC2. (PB) */
 358     /*  0x1e002000 GIC3. (PB) */
 359     /*  0x1e003000 GIC4. (PB) */
 360     /*  0x40000000 NOR flash.  */
 361     /*  0x44000000 DoC flash.  */
 362     /*  0x48000000 SRAM.  */
 363     /*  0x4c000000 Configuration flash.  */
 364     /* 0x4e000000 Ethernet.  */
 365     /*  0x4f000000 USB.  */
 366     /*  0x50000000 PISMO.  */
 367     /*  0x54000000 PISMO.  */
 368     /*  0x58000000 PISMO.  */
 369     /*  0x5c000000 PISMO.  */
 370     /* 0x60000000 PCI.  */
 371     /* 0x61000000 PCI Self Config.  */
 372     /* 0x62000000 PCI Config.  */
 373     /* 0x63000000 PCI IO.  */
 374     /* 0x64000000 PCI mem 0.  */
 375     /* 0x68000000 PCI mem 1.  */
 376     /* 0x6c000000 PCI mem 2.  */
 377
 378     /* ??? Hack to map an additional page of ram for the secondary CPU
 379        startup code.  I guess this works on real hardware because the
 380        BootROM happens to be in ROM/flash or in memory that isn't clobbered
 381        until after Linux boots the secondary CPUs.  */
 382     memory_region_init_ram(ram_hack, "realview.hack", 0x1000);
 383     vmstate_register_ram_global(ram_hack);
 384     memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack);
 385
 386     realview_binfo.ram_size = ram_size;
 387     realview_binfo.kernel_filename = kernel_filename;
 388     realview_binfo.kernel_cmdline = kernel_cmdline;
 389     realview_binfo.initrd_filename = initrd_filename;
 390     realview_binfo.nb_cpus = smp_cpus;
 391     realview_binfo.board_id = realview_board_id[board_type];
 392     realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0);
 393     arm_load_kernel(first_cpu, &realview_binfo);
 394 }
 395
 396 static void realview_eb_init(ram_addr_t ram_size,
 397                      const char *boot_device,
 398                      const char *kernel_filename, const char *kernel_cmdline,
 399                      const char *initrd_filename, const char *cpu_model)
 400 {
 401     if (!cpu_model) {
 402         cpu_model = "arm926";
 403     }
 404     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 405                   initrd_filename, cpu_model, BOARD_EB);
 406 }
 407
 408 static void realview_eb_mpcore_init(ram_addr_t ram_size,
 409                      const char *boot_device,
 410                      const char *kernel_filename, const char *kernel_cmdline,
 411                      const char *initrd_filename, const char *cpu_model)
 412 {
 413     if (!cpu_model) {
 414         cpu_model = "arm11mpcore";
 415     }
 416     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 417                   initrd_filename, cpu_model, BOARD_EB_MPCORE);
 418 }
 419
 420 static void realview_pb_a8_init(ram_addr_t ram_size,
 421                      const char *boot_device,
 422                      const char *kernel_filename, const char *kernel_cmdline,
 423                      const char *initrd_filename, const char *cpu_model)
 424 {
 425     if (!cpu_model) {
 426         cpu_model = "cortex-a8";
 427     }
 428     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 429                   initrd_filename, cpu_model, BOARD_PB_A8);
 430 }
 431
 432 static void realview_pbx_a9_init(ram_addr_t ram_size,
 433                      const char *boot_device,
 434                      const char *kernel_filename, const char *kernel_cmdline,
 435                      const char *initrd_filename, const char *cpu_model)
 436 {
 437     if (!cpu_model) {
 438         cpu_model = "cortex-a9";
 439     }
 440     realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline,
 441                   initrd_filename, cpu_model, BOARD_PBX_A9);
 442 }
 443
 444 static QEMUMachine realview_eb_machine = {
 445     .name = "realview-eb",
 446     .desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)",
 447     .init = realview_eb_init,
 448     .use_scsi = 1,
 449 };
 450
 451 static QEMUMachine realview_eb_mpcore_machine = {
 452     .name = "realview-eb-mpcore",
 453     .desc = "ARM RealView Emulation Baseboard (ARM11MPCore)",
 454     .init = realview_eb_mpcore_init,
 455     .use_scsi = 1,
 456     .max_cpus = 4,
 457 };
 458
 459 static QEMUMachine realview_pb_a8_machine = {
 460     .name = "realview-pb-a8",
 461     .desc = "ARM RealView Platform Baseboard for Cortex-A8",
 462     .init = realview_pb_a8_init,
 463 };
 464
 465 static QEMUMachine realview_pbx_a9_machine = {
 466     .name = "realview-pbx-a9",
 467     .desc = "ARM RealView Platform Baseboard Explore for Cortex-A9",
 468     .init = realview_pbx_a9_init,
 469     .use_scsi = 1,
 470     .max_cpus = 4,
 471 };
 472
 473 static void realview_machine_init(void)
 474 {
 475     qemu_register_machine(&realview_eb_machine);
 476     qemu_register_machine(&realview_eb_mpcore_machine);
 477     qemu_register_machine(&realview_pb_a8_machine);
 478     qemu_register_machine(&realview_pbx_a9_machine);
 479 }
 480
 481 machine_init(realview_machine_init);
 482 device_init(realview_register_devices)