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1 /**
2 * QEMU RTL8139 emulation
3 *
4 * Copyright (c) 2006 Igor Kovalenko
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23
24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
26 *
27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
29 *
30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
49 */
50
51 /* For crc32 */
52 #include <zlib.h>
53
54 #include "hw.h"
55 #include "pci.h"
56 #include "dma.h"
57 #include "qemu-timer.h"
58 #include "net.h"
59 #include "loader.h"
60 #include "sysemu.h"
61 #include "iov.h"
62
63 /* debug RTL8139 card */
64 //#define DEBUG_RTL8139 1
65
66 #define PCI_FREQUENCY 33000000L
67
68 #define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71 /* arg % size for size which is a power of 2 */
72 #define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
75 #define ETHER_ADDR_LEN 6
76 #define ETHER_TYPE_LEN 2
77 #define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78 #define ETH_P_IP 0x0800 /* Internet Protocol packet */
79 #define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80 #define ETH_MTU 1500
81
82 #define VLAN_TCI_LEN 2
83 #define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
85 #if defined (DEBUG_RTL8139)
86 # define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
88 #else
89 static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
90 {
91 return 0;
92 }
93 #endif
94
95 /* Symbolic offsets to registers. */
96 enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142 };
143
144 enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148 };
149
150 enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155 };
156
157 /* C+ mode */
158 enum CplusCmdBits {
159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
163 };
164
165 /* Interrupt register bits, using my own meaningful names. */
166 enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
170 RxUnderrun = 0x20,
171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178 };
179
180 enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187 };
188 enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198 };
199
200 /* Bits in RxConfig. */
201 enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208 };
209
210 /* Bits in TxConfig. */
211 enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227 };
228
229
230 /* Transmit Status of All Descriptors (TSAD) Register */
231 enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248 };
249
250
251 /* Bits in Config1 */
252 enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263 };
264
265 /* Bits in Config3 */
266 enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275 };
276
277 /* Bits in Config4 */
278 enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280 };
281
282 /* Bits in Config5 */
283 enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291 };
292
293 enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310 };
311
312 /* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314 /*
315 enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321 */
322 enum CSCRBits {
323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332 };
333
334 enum Cfg9346Bits {
335 Cfg9346_Lock = 0x00,
336 Cfg9346_Unlock = 0xC0,
337 };
338
339 typedef enum {
340 CH_8139 = 0,
341 CH_8139_K,
342 CH_8139A,
343 CH_8139A_G,
344 CH_8139B,
345 CH_8130,
346 CH_8139C,
347 CH_8100,
348 CH_8100B_8139D,
349 CH_8101,
350 } chip_t;
351
352 enum chip_flags {
353 HasHltClk = (1 << 0),
354 HasLWake = (1 << 1),
355 };
356
357 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
358 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
359 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
360
361 #define RTL8139_PCI_REVID_8139 0x10
362 #define RTL8139_PCI_REVID_8139CPLUS 0x20
363
364 #define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
365
366 /* Size is 64 * 16bit words */
367 #define EEPROM_9346_ADDR_BITS 6
368 #define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
369 #define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
370
371 enum Chip9346Operation
372 {
373 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
374 Chip9346_op_read = 0x80, /* 10 AAAAAA */
375 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
376 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
377 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
378 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
379 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
380 };
381
382 enum Chip9346Mode
383 {
384 Chip9346_none = 0,
385 Chip9346_enter_command_mode,
386 Chip9346_read_command,
387 Chip9346_data_read, /* from output register */
388 Chip9346_data_write, /* to input register, then to contents at specified address */
389 Chip9346_data_write_all, /* to input register, then filling contents */
390 };
391
392 typedef struct EEprom9346
393 {
394 uint16_t contents[EEPROM_9346_SIZE];
395 int mode;
396 uint32_t tick;
397 uint8_t address;
398 uint16_t input;
399 uint16_t output;
400
401 uint8_t eecs;
402 uint8_t eesk;
403 uint8_t eedi;
404 uint8_t eedo;
405 } EEprom9346;
406
407 typedef struct RTL8139TallyCounters
408 {
409 /* Tally counters */
410 uint64_t TxOk;
411 uint64_t RxOk;
412 uint64_t TxERR;
413 uint32_t RxERR;
414 uint16_t MissPkt;
415 uint16_t FAE;
416 uint32_t Tx1Col;
417 uint32_t TxMCol;
418 uint64_t RxOkPhy;
419 uint64_t RxOkBrd;
420 uint32_t RxOkMul;
421 uint16_t TxAbt;
422 uint16_t TxUndrn;
423 } RTL8139TallyCounters;
424
425 /* Clears all tally counters */
426 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
427
428 typedef struct RTL8139State {
429 PCIDevice dev;
430 uint8_t phys[8]; /* mac address */
431 uint8_t mult[8]; /* multicast mask array */
432
433 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
434 uint32_t TxAddr[4]; /* TxAddr0 */
435 uint32_t RxBuf; /* Receive buffer */
436 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
437 uint32_t RxBufPtr;
438 uint32_t RxBufAddr;
439
440 uint16_t IntrStatus;
441 uint16_t IntrMask;
442
443 uint32_t TxConfig;
444 uint32_t RxConfig;
445 uint32_t RxMissed;
446
447 uint16_t CSCR;
448
449 uint8_t Cfg9346;
450 uint8_t Config0;
451 uint8_t Config1;
452 uint8_t Config3;
453 uint8_t Config4;
454 uint8_t Config5;
455
456 uint8_t clock_enabled;
457 uint8_t bChipCmdState;
458
459 uint16_t MultiIntr;
460
461 uint16_t BasicModeCtrl;
462 uint16_t BasicModeStatus;
463 uint16_t NWayAdvert;
464 uint16_t NWayLPAR;
465 uint16_t NWayExpansion;
466
467 uint16_t CpCmd;
468 uint8_t TxThresh;
469
470 NICState *nic;
471 NICConf conf;
472
473 /* C ring mode */
474 uint32_t currTxDesc;
475
476 /* C+ mode */
477 uint32_t cplus_enabled;
478
479 uint32_t currCPlusRxDesc;
480 uint32_t currCPlusTxDesc;
481
482 uint32_t RxRingAddrLO;
483 uint32_t RxRingAddrHI;
484
485 EEprom9346 eeprom;
486
487 uint32_t TCTR;
488 uint32_t TimerInt;
489 int64_t TCTR_base;
490
491 /* Tally counters */
492 RTL8139TallyCounters tally_counters;
493
494 /* Non-persistent data */
495 uint8_t *cplus_txbuffer;
496 int cplus_txbuffer_len;
497 int cplus_txbuffer_offset;
498
499 /* PCI interrupt timer */
500 QEMUTimer *timer;
501 int64_t TimerExpire;
502
503 MemoryRegion bar_io;
504 MemoryRegion bar_mem;
505
506 /* Support migration to/from old versions */
507 int rtl8139_mmio_io_addr_dummy;
508 } RTL8139State;
509
510 /* Writes tally counters to memory via DMA */
511 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
512
513 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
514
515 static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
516 {
517 DPRINTF("eeprom command 0x%02x\n", command);
518
519 switch (command & Chip9346_op_mask)
520 {
521 case Chip9346_op_read:
522 {
523 eeprom->address = command & EEPROM_9346_ADDR_MASK;
524 eeprom->output = eeprom->contents[eeprom->address];
525 eeprom->eedo = 0;
526 eeprom->tick = 0;
527 eeprom->mode = Chip9346_data_read;
528 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
529 eeprom->address, eeprom->output);
530 }
531 break;
532
533 case Chip9346_op_write:
534 {
535 eeprom->address = command & EEPROM_9346_ADDR_MASK;
536 eeprom->input = 0;
537 eeprom->tick = 0;
538 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
539 DPRINTF("eeprom begin write to address 0x%02x\n",
540 eeprom->address);
541 }
542 break;
543 default:
544 eeprom->mode = Chip9346_none;
545 switch (command & Chip9346_op_ext_mask)
546 {
547 case Chip9346_op_write_enable:
548 DPRINTF("eeprom write enabled\n");
549 break;
550 case Chip9346_op_write_all:
551 DPRINTF("eeprom begin write all\n");
552 break;
553 case Chip9346_op_write_disable:
554 DPRINTF("eeprom write disabled\n");
555 break;
556 }
557 break;
558 }
559 }
560
561 static void prom9346_shift_clock(EEprom9346 *eeprom)
562 {
563 int bit = eeprom->eedi?1:0;
564
565 ++ eeprom->tick;
566
567 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
568 eeprom->eedo);
569
570 switch (eeprom->mode)
571 {
572 case Chip9346_enter_command_mode:
573 if (bit)
574 {
575 eeprom->mode = Chip9346_read_command;
576 eeprom->tick = 0;
577 eeprom->input = 0;
578 DPRINTF("eeprom: +++ synchronized, begin command read\n");
579 }
580 break;
581
582 case Chip9346_read_command:
583 eeprom->input = (eeprom->input << 1) | (bit & 1);
584 if (eeprom->tick == 8)
585 {
586 prom9346_decode_command(eeprom, eeprom->input & 0xff);
587 }
588 break;
589
590 case Chip9346_data_read:
591 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
592 eeprom->output <<= 1;
593 if (eeprom->tick == 16)
594 {
595 #if 1
596 // the FreeBSD drivers (rl and re) don't explicitly toggle
597 // CS between reads (or does setting Cfg9346 to 0 count too?),
598 // so we need to enter wait-for-command state here
599 eeprom->mode = Chip9346_enter_command_mode;
600 eeprom->input = 0;
601 eeprom->tick = 0;
602
603 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
604 #else
605 // original behaviour
606 ++eeprom->address;
607 eeprom->address &= EEPROM_9346_ADDR_MASK;
608 eeprom->output = eeprom->contents[eeprom->address];
609 eeprom->tick = 0;
610
611 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
612 eeprom->address, eeprom->output);
613 #endif
614 }
615 break;
616
617 case Chip9346_data_write:
618 eeprom->input = (eeprom->input << 1) | (bit & 1);
619 if (eeprom->tick == 16)
620 {
621 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
622 eeprom->address, eeprom->input);
623
624 eeprom->contents[eeprom->address] = eeprom->input;
625 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
626 eeprom->tick = 0;
627 eeprom->input = 0;
628 }
629 break;
630
631 case Chip9346_data_write_all:
632 eeprom->input = (eeprom->input << 1) | (bit & 1);
633 if (eeprom->tick == 16)
634 {
635 int i;
636 for (i = 0; i < EEPROM_9346_SIZE; i++)
637 {
638 eeprom->contents[i] = eeprom->input;
639 }
640 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
641
642 eeprom->mode = Chip9346_enter_command_mode;
643 eeprom->tick = 0;
644 eeprom->input = 0;
645 }
646 break;
647
648 default:
649 break;
650 }
651 }
652
653 static int prom9346_get_wire(RTL8139State *s)
654 {
655 EEprom9346 *eeprom = &s->eeprom;
656 if (!eeprom->eecs)
657 return 0;
658
659 return eeprom->eedo;
660 }
661
662 /* FIXME: This should be merged into/replaced by eeprom93xx.c. */
663 static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
664 {
665 EEprom9346 *eeprom = &s->eeprom;
666 uint8_t old_eecs = eeprom->eecs;
667 uint8_t old_eesk = eeprom->eesk;
668
669 eeprom->eecs = eecs;
670 eeprom->eesk = eesk;
671 eeprom->eedi = eedi;
672
673 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
674 eeprom->eesk, eeprom->eedi, eeprom->eedo);
675
676 if (!old_eecs && eecs)
677 {
678 /* Synchronize start */
679 eeprom->tick = 0;
680 eeprom->input = 0;
681 eeprom->output = 0;
682 eeprom->mode = Chip9346_enter_command_mode;
683
684 DPRINTF("=== eeprom: begin access, enter command mode\n");
685 }
686
687 if (!eecs)
688 {
689 DPRINTF("=== eeprom: end access\n");
690 return;
691 }
692
693 if (!old_eesk && eesk)
694 {
695 /* SK front rules */
696 prom9346_shift_clock(eeprom);
697 }
698 }
699
700 static void rtl8139_update_irq(RTL8139State *s)
701 {
702 int isr;
703 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
704
705 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
706 s->IntrMask);
707
708 qemu_set_irq(s->dev.irq[0], (isr != 0));
709 }
710
711 static int rtl8139_RxWrap(RTL8139State *s)
712 {
713 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
714 return (s->RxConfig & (1 << 7));
715 }
716
717 static int rtl8139_receiver_enabled(RTL8139State *s)
718 {
719 return s->bChipCmdState & CmdRxEnb;
720 }
721
722 static int rtl8139_transmitter_enabled(RTL8139State *s)
723 {
724 return s->bChipCmdState & CmdTxEnb;
725 }
726
727 static int rtl8139_cp_receiver_enabled(RTL8139State *s)
728 {
729 return s->CpCmd & CPlusRxEnb;
730 }
731
732 static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
733 {
734 return s->CpCmd & CPlusTxEnb;
735 }
736
737 static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
738 {
739 if (s->RxBufAddr + size > s->RxBufferSize)
740 {
741 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
742
743 /* write packet data */
744 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
745 {
746 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
747
748 if (size > wrapped)
749 {
750 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
751 buf, size-wrapped);
752 }
753
754 /* reset buffer pointer */
755 s->RxBufAddr = 0;
756
757 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
758 buf + (size-wrapped), wrapped);
759
760 s->RxBufAddr = wrapped;
761
762 return;
763 }
764 }
765
766 /* non-wrapping path or overwrapping enabled */
767 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
768
769 s->RxBufAddr += size;
770 }
771
772 #define MIN_BUF_SIZE 60
773 static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
774 {
775 #if TARGET_PHYS_ADDR_BITS > 32
776 return low | ((target_phys_addr_t)high << 32);
777 #else
778 return low;
779 #endif
780 }
781
782 static int rtl8139_can_receive(VLANClientState *nc)
783 {
784 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
785 int avail;
786
787 /* Receive (drop) packets if card is disabled. */
788 if (!s->clock_enabled)
789 return 1;
790 if (!rtl8139_receiver_enabled(s))
791 return 1;
792
793 if (rtl8139_cp_receiver_enabled(s)) {
794 /* ??? Flow control not implemented in c+ mode.
795 This is a hack to work around slirp deficiencies anyway. */
796 return 1;
797 } else {
798 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
799 s->RxBufferSize);
800 return (avail == 0 || avail >= 1514);
801 }
802 }
803
804 static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
805 {
806 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
807 /* size is the length of the buffer passed to the driver */
808 int size = size_;
809 const uint8_t *dot1q_buf = NULL;
810
811 uint32_t packet_header = 0;
812
813 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
814 static const uint8_t broadcast_macaddr[6] =
815 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
816
817 DPRINTF(">>> received len=%d\n", size);
818
819 /* test if board clock is stopped */
820 if (!s->clock_enabled)
821 {
822 DPRINTF("stopped ==========================\n");
823 return -1;
824 }
825
826 /* first check if receiver is enabled */
827
828 if (!rtl8139_receiver_enabled(s))
829 {
830 DPRINTF("receiver disabled ================\n");
831 return -1;
832 }
833
834 /* XXX: check this */
835 if (s->RxConfig & AcceptAllPhys) {
836 /* promiscuous: receive all */
837 DPRINTF(">>> packet received in promiscuous mode\n");
838
839 } else {
840 if (!memcmp(buf, broadcast_macaddr, 6)) {
841 /* broadcast address */
842 if (!(s->RxConfig & AcceptBroadcast))
843 {
844 DPRINTF(">>> broadcast packet rejected\n");
845
846 /* update tally counter */
847 ++s->tally_counters.RxERR;
848
849 return size;
850 }
851
852 packet_header |= RxBroadcast;
853
854 DPRINTF(">>> broadcast packet received\n");
855
856 /* update tally counter */
857 ++s->tally_counters.RxOkBrd;
858
859 } else if (buf[0] & 0x01) {
860 /* multicast */
861 if (!(s->RxConfig & AcceptMulticast))
862 {
863 DPRINTF(">>> multicast packet rejected\n");
864
865 /* update tally counter */
866 ++s->tally_counters.RxERR;
867
868 return size;
869 }
870
871 int mcast_idx = compute_mcast_idx(buf);
872
873 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
874 {
875 DPRINTF(">>> multicast address mismatch\n");
876
877 /* update tally counter */
878 ++s->tally_counters.RxERR;
879
880 return size;
881 }
882
883 packet_header |= RxMulticast;
884
885 DPRINTF(">>> multicast packet received\n");
886
887 /* update tally counter */
888 ++s->tally_counters.RxOkMul;
889
890 } else if (s->phys[0] == buf[0] &&
891 s->phys[1] == buf[1] &&
892 s->phys[2] == buf[2] &&
893 s->phys[3] == buf[3] &&
894 s->phys[4] == buf[4] &&
895 s->phys[5] == buf[5]) {
896 /* match */
897 if (!(s->RxConfig & AcceptMyPhys))
898 {
899 DPRINTF(">>> rejecting physical address matching packet\n");
900
901 /* update tally counter */
902 ++s->tally_counters.RxERR;
903
904 return size;
905 }
906
907 packet_header |= RxPhysical;
908
909 DPRINTF(">>> physical address matching packet received\n");
910
911 /* update tally counter */
912 ++s->tally_counters.RxOkPhy;
913
914 } else {
915
916 DPRINTF(">>> unknown packet\n");
917
918 /* update tally counter */
919 ++s->tally_counters.RxERR;
920
921 return size;
922 }
923 }
924
925 /* if too small buffer, then expand it
926 * Include some tailroom in case a vlan tag is later removed. */
927 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
928 memcpy(buf1, buf, size);
929 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
930 buf = buf1;
931 if (size < MIN_BUF_SIZE) {
932 size = MIN_BUF_SIZE;
933 }
934 }
935
936 if (rtl8139_cp_receiver_enabled(s))
937 {
938 DPRINTF("in C+ Rx mode ================\n");
939
940 /* begin C+ receiver mode */
941
942 /* w0 ownership flag */
943 #define CP_RX_OWN (1<<31)
944 /* w0 end of ring flag */
945 #define CP_RX_EOR (1<<30)
946 /* w0 bits 0...12 : buffer size */
947 #define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
948 /* w1 tag available flag */
949 #define CP_RX_TAVA (1<<16)
950 /* w1 bits 0...15 : VLAN tag */
951 #define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
952 /* w2 low 32bit of Rx buffer ptr */
953 /* w3 high 32bit of Rx buffer ptr */
954
955 int descriptor = s->currCPlusRxDesc;
956 dma_addr_t cplus_rx_ring_desc;
957
958 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
959 cplus_rx_ring_desc += 16 * descriptor;
960
961 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
962 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
963 s->RxRingAddrLO, cplus_rx_ring_desc);
964
965 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
966
967 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
968 rxdw0 = le32_to_cpu(val);
969 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
970 rxdw1 = le32_to_cpu(val);
971 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
972 rxbufLO = le32_to_cpu(val);
973 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
974 rxbufHI = le32_to_cpu(val);
975
976 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
977 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
978
979 if (!(rxdw0 & CP_RX_OWN))
980 {
981 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
982 descriptor);
983
984 s->IntrStatus |= RxOverflow;
985 ++s->RxMissed;
986
987 /* update tally counter */
988 ++s->tally_counters.RxERR;
989 ++s->tally_counters.MissPkt;
990
991 rtl8139_update_irq(s);
992 return size_;
993 }
994
995 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
996
997 /* write VLAN info to descriptor variables. */
998 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
999 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1000 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1001 size -= VLAN_HLEN;
1002 /* if too small buffer, use the tailroom added duing expansion */
1003 if (size < MIN_BUF_SIZE) {
1004 size = MIN_BUF_SIZE;
1005 }
1006
1007 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1008 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1009 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1010 &dot1q_buf[ETHER_TYPE_LEN]);
1011
1012 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1013 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
1014 } else {
1015 /* reset VLAN tag flag */
1016 rxdw1 &= ~CP_RX_TAVA;
1017 }
1018
1019 /* TODO: scatter the packet over available receive ring descriptors space */
1020
1021 if (size+4 > rx_space)
1022 {
1023 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1024 descriptor, rx_space, size);
1025
1026 s->IntrStatus |= RxOverflow;
1027 ++s->RxMissed;
1028
1029 /* update tally counter */
1030 ++s->tally_counters.RxERR;
1031 ++s->tally_counters.MissPkt;
1032
1033 rtl8139_update_irq(s);
1034 return size_;
1035 }
1036
1037 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
1038
1039 /* receive/copy to target memory */
1040 if (dot1q_buf) {
1041 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1042 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1043 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1044 size - 2 * ETHER_ADDR_LEN);
1045 } else {
1046 pci_dma_write(&s->dev, rx_addr, buf, size);
1047 }
1048
1049 if (s->CpCmd & CPlusRxChkSum)
1050 {
1051 /* do some packet checksumming */
1052 }
1053
1054 /* write checksum */
1055 val = cpu_to_le32(crc32(0, buf, size_));
1056 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
1057
1058 /* first segment of received packet flag */
1059 #define CP_RX_STATUS_FS (1<<29)
1060 /* last segment of received packet flag */
1061 #define CP_RX_STATUS_LS (1<<28)
1062 /* multicast packet flag */
1063 #define CP_RX_STATUS_MAR (1<<26)
1064 /* physical-matching packet flag */
1065 #define CP_RX_STATUS_PAM (1<<25)
1066 /* broadcast packet flag */
1067 #define CP_RX_STATUS_BAR (1<<24)
1068 /* runt packet flag */
1069 #define CP_RX_STATUS_RUNT (1<<19)
1070 /* crc error flag */
1071 #define CP_RX_STATUS_CRC (1<<18)
1072 /* IP checksum error flag */
1073 #define CP_RX_STATUS_IPF (1<<15)
1074 /* UDP checksum error flag */
1075 #define CP_RX_STATUS_UDPF (1<<14)
1076 /* TCP checksum error flag */
1077 #define CP_RX_STATUS_TCPF (1<<13)
1078
1079 /* transfer ownership to target */
1080 rxdw0 &= ~CP_RX_OWN;
1081
1082 /* set first segment bit */
1083 rxdw0 |= CP_RX_STATUS_FS;
1084
1085 /* set last segment bit */
1086 rxdw0 |= CP_RX_STATUS_LS;
1087
1088 /* set received packet type flags */
1089 if (packet_header & RxBroadcast)
1090 rxdw0 |= CP_RX_STATUS_BAR;
1091 if (packet_header & RxMulticast)
1092 rxdw0 |= CP_RX_STATUS_MAR;
1093 if (packet_header & RxPhysical)
1094 rxdw0 |= CP_RX_STATUS_PAM;
1095
1096 /* set received size */
1097 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1098 rxdw0 |= (size+4);
1099
1100 /* update ring data */
1101 val = cpu_to_le32(rxdw0);
1102 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
1103 val = cpu_to_le32(rxdw1);
1104 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
1105
1106 /* update tally counter */
1107 ++s->tally_counters.RxOk;
1108
1109 /* seek to next Rx descriptor */
1110 if (rxdw0 & CP_RX_EOR)
1111 {
1112 s->currCPlusRxDesc = 0;
1113 }
1114 else
1115 {
1116 ++s->currCPlusRxDesc;
1117 }
1118
1119 DPRINTF("done C+ Rx mode ----------------\n");
1120
1121 }
1122 else
1123 {
1124 DPRINTF("in ring Rx mode ================\n");
1125
1126 /* begin ring receiver mode */
1127 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1128
1129 /* if receiver buffer is empty then avail == 0 */
1130
1131 if (avail != 0 && size + 8 >= avail)
1132 {
1133 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1134 "read 0x%04x === available 0x%04x need 0x%04x\n",
1135 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
1136
1137 s->IntrStatus |= RxOverflow;
1138 ++s->RxMissed;
1139 rtl8139_update_irq(s);
1140 return size_;
1141 }
1142
1143 packet_header |= RxStatusOK;
1144
1145 packet_header |= (((size+4) << 16) & 0xffff0000);
1146
1147 /* write header */
1148 uint32_t val = cpu_to_le32(packet_header);
1149
1150 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1151
1152 rtl8139_write_buffer(s, buf, size);
1153
1154 /* write checksum */
1155 val = cpu_to_le32(crc32(0, buf, size));
1156 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1157
1158 /* correct buffer write pointer */
1159 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1160
1161 /* now we can signal we have received something */
1162
1163 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1164 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
1165 }
1166
1167 s->IntrStatus |= RxOK;
1168
1169 if (do_interrupt)
1170 {
1171 rtl8139_update_irq(s);
1172 }
1173
1174 return size_;
1175 }
1176
1177 static ssize_t rtl8139_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
1178 {
1179 return rtl8139_do_receive(nc, buf, size, 1);
1180 }
1181
1182 static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1183 {
1184 s->RxBufferSize = bufferSize;
1185 s->RxBufPtr = 0;
1186 s->RxBufAddr = 0;
1187 }
1188
1189 static void rtl8139_reset(DeviceState *d)
1190 {
1191 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
1192 int i;
1193
1194 /* restore MAC address */
1195 memcpy(s->phys, s->conf.macaddr.a, 6);
1196
1197 /* reset interrupt mask */
1198 s->IntrStatus = 0;
1199 s->IntrMask = 0;
1200
1201 rtl8139_update_irq(s);
1202
1203 /* mark all status registers as owned by host */
1204 for (i = 0; i < 4; ++i)
1205 {
1206 s->TxStatus[i] = TxHostOwns;
1207 }
1208
1209 s->currTxDesc = 0;
1210 s->currCPlusRxDesc = 0;
1211 s->currCPlusTxDesc = 0;
1212
1213 s->RxRingAddrLO = 0;
1214 s->RxRingAddrHI = 0;
1215
1216 s->RxBuf = 0;
1217
1218 rtl8139_reset_rxring(s, 8192);
1219
1220 /* ACK the reset */
1221 s->TxConfig = 0;
1222
1223 #if 0
1224 // s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1225 s->clock_enabled = 0;
1226 #else
1227 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
1228 s->clock_enabled = 1;
1229 #endif
1230
1231 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1232
1233 /* set initial state data */
1234 s->Config0 = 0x0; /* No boot ROM */
1235 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1236 s->Config3 = 0x1; /* fast back-to-back compatible */
1237 s->Config5 = 0x0;
1238
1239 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
1240
1241 s->CpCmd = 0x0; /* reset C+ mode */
1242 s->cplus_enabled = 0;
1243
1244
1245 // s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1246 // s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1247 s->BasicModeCtrl = 0x1000; // autonegotiation
1248
1249 s->BasicModeStatus = 0x7809;
1250 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1251 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1252 s->BasicModeStatus |= 0x0004; /* link is up */
1253
1254 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1255 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1256 s->NWayExpansion = 0x0001; /* autonegotiation supported */
1257
1258 /* also reset timer and disable timer interrupt */
1259 s->TCTR = 0;
1260 s->TimerInt = 0;
1261 s->TCTR_base = 0;
1262
1263 /* reset tally counters */
1264 RTL8139TallyCounters_clear(&s->tally_counters);
1265 }
1266
1267 static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
1268 {
1269 counters->TxOk = 0;
1270 counters->RxOk = 0;
1271 counters->TxERR = 0;
1272 counters->RxERR = 0;
1273 counters->MissPkt = 0;
1274 counters->FAE = 0;
1275 counters->Tx1Col = 0;
1276 counters->TxMCol = 0;
1277 counters->RxOkPhy = 0;
1278 counters->RxOkBrd = 0;
1279 counters->RxOkMul = 0;
1280 counters->TxAbt = 0;
1281 counters->TxUndrn = 0;
1282 }
1283
1284 static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
1285 {
1286 RTL8139TallyCounters *tally_counters = &s->tally_counters;
1287 uint16_t val16;
1288 uint32_t val32;
1289 uint64_t val64;
1290
1291 val64 = cpu_to_le64(tally_counters->TxOk);
1292 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
1293
1294 val64 = cpu_to_le64(tally_counters->RxOk);
1295 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
1296
1297 val64 = cpu_to_le64(tally_counters->TxERR);
1298 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
1299
1300 val32 = cpu_to_le32(tally_counters->RxERR);
1301 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
1302
1303 val16 = cpu_to_le16(tally_counters->MissPkt);
1304 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
1305
1306 val16 = cpu_to_le16(tally_counters->FAE);
1307 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
1308
1309 val32 = cpu_to_le32(tally_counters->Tx1Col);
1310 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
1311
1312 val32 = cpu_to_le32(tally_counters->TxMCol);
1313 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
1314
1315 val64 = cpu_to_le64(tally_counters->RxOkPhy);
1316 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
1317
1318 val64 = cpu_to_le64(tally_counters->RxOkBrd);
1319 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
1320
1321 val32 = cpu_to_le32(tally_counters->RxOkMul);
1322 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
1323
1324 val16 = cpu_to_le16(tally_counters->TxAbt);
1325 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
1326
1327 val16 = cpu_to_le16(tally_counters->TxUndrn);
1328 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
1329 }
1330
1331 /* Loads values of tally counters from VM state file */
1332
1333 static const VMStateDescription vmstate_tally_counters = {
1334 .name = "tally_counters",
1335 .version_id = 1,
1336 .minimum_version_id = 1,
1337 .minimum_version_id_old = 1,
1338 .fields = (VMStateField []) {
1339 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1340 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1341 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1342 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1343 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1344 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1345 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1346 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1347 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1348 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1349 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1350 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1351 VMSTATE_END_OF_LIST()
1352 }
1353 };
1354
1355 static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1356 {
1357 val &= 0xff;
1358
1359 DPRINTF("ChipCmd write val=0x%08x\n", val);
1360
1361 if (val & CmdReset)
1362 {
1363 DPRINTF("ChipCmd reset\n");
1364 rtl8139_reset(&s->dev.qdev);
1365 }
1366 if (val & CmdRxEnb)
1367 {
1368 DPRINTF("ChipCmd enable receiver\n");
1369
1370 s->currCPlusRxDesc = 0;
1371 }
1372 if (val & CmdTxEnb)
1373 {
1374 DPRINTF("ChipCmd enable transmitter\n");
1375
1376 s->currCPlusTxDesc = 0;
1377 }
1378
1379 /* mask unwritable bits */
1380 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1381
1382 /* Deassert reset pin before next read */
1383 val &= ~CmdReset;
1384
1385 s->bChipCmdState = val;
1386 }
1387
1388 static int rtl8139_RxBufferEmpty(RTL8139State *s)
1389 {
1390 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1391
1392 if (unread != 0)
1393 {
1394 DPRINTF("receiver buffer data available 0x%04x\n", unread);
1395 return 0;
1396 }
1397
1398 DPRINTF("receiver buffer is empty\n");
1399
1400 return 1;
1401 }
1402
1403 static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1404 {
1405 uint32_t ret = s->bChipCmdState;
1406
1407 if (rtl8139_RxBufferEmpty(s))
1408 ret |= RxBufEmpty;
1409
1410 DPRINTF("ChipCmd read val=0x%04x\n", ret);
1411
1412 return ret;
1413 }
1414
1415 static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1416 {
1417 val &= 0xffff;
1418
1419 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
1420
1421 s->cplus_enabled = 1;
1422
1423 /* mask unwritable bits */
1424 val = SET_MASKED(val, 0xff84, s->CpCmd);
1425
1426 s->CpCmd = val;
1427 }
1428
1429 static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1430 {
1431 uint32_t ret = s->CpCmd;
1432
1433 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
1434
1435 return ret;
1436 }
1437
1438 static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1439 {
1440 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
1441 }
1442
1443 static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1444 {
1445 uint32_t ret = 0;
1446
1447 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
1448
1449 return ret;
1450 }
1451
1452 static int rtl8139_config_writable(RTL8139State *s)
1453 {
1454 if (s->Cfg9346 & Cfg9346_Unlock)
1455 {
1456 return 1;
1457 }
1458
1459 DPRINTF("Configuration registers are write-protected\n");
1460
1461 return 0;
1462 }
1463
1464 static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1465 {
1466 val &= 0xffff;
1467
1468 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
1469
1470 /* mask unwritable bits */
1471 uint32_t mask = 0x4cff;
1472
1473 if (1 || !rtl8139_config_writable(s))
1474 {
1475 /* Speed setting and autonegotiation enable bits are read-only */
1476 mask |= 0x3000;
1477 /* Duplex mode setting is read-only */
1478 mask |= 0x0100;
1479 }
1480
1481 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1482
1483 s->BasicModeCtrl = val;
1484 }
1485
1486 static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1487 {
1488 uint32_t ret = s->BasicModeCtrl;
1489
1490 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
1491
1492 return ret;
1493 }
1494
1495 static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1496 {
1497 val &= 0xffff;
1498
1499 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
1500
1501 /* mask unwritable bits */
1502 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1503
1504 s->BasicModeStatus = val;
1505 }
1506
1507 static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1508 {
1509 uint32_t ret = s->BasicModeStatus;
1510
1511 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
1512
1513 return ret;
1514 }
1515
1516 static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1517 {
1518 val &= 0xff;
1519
1520 DPRINTF("Cfg9346 write val=0x%02x\n", val);
1521
1522 /* mask unwritable bits */
1523 val = SET_MASKED(val, 0x31, s->Cfg9346);
1524
1525 uint32_t opmode = val & 0xc0;
1526 uint32_t eeprom_val = val & 0xf;
1527
1528 if (opmode == 0x80) {
1529 /* eeprom access */
1530 int eecs = (eeprom_val & 0x08)?1:0;
1531 int eesk = (eeprom_val & 0x04)?1:0;
1532 int eedi = (eeprom_val & 0x02)?1:0;
1533 prom9346_set_wire(s, eecs, eesk, eedi);
1534 } else if (opmode == 0x40) {
1535 /* Reset. */
1536 val = 0;
1537 rtl8139_reset(&s->dev.qdev);
1538 }
1539
1540 s->Cfg9346 = val;
1541 }
1542
1543 static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1544 {
1545 uint32_t ret = s->Cfg9346;
1546
1547 uint32_t opmode = ret & 0xc0;
1548
1549 if (opmode == 0x80)
1550 {
1551 /* eeprom access */
1552 int eedo = prom9346_get_wire(s);
1553 if (eedo)
1554 {
1555 ret |= 0x01;
1556 }
1557 else
1558 {
1559 ret &= ~0x01;
1560 }
1561 }
1562
1563 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
1564
1565 return ret;
1566 }
1567
1568 static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1569 {
1570 val &= 0xff;
1571
1572 DPRINTF("Config0 write val=0x%02x\n", val);
1573
1574 if (!rtl8139_config_writable(s)) {
1575 return;
1576 }
1577
1578 /* mask unwritable bits */
1579 val = SET_MASKED(val, 0xf8, s->Config0);
1580
1581 s->Config0 = val;
1582 }
1583
1584 static uint32_t rtl8139_Config0_read(RTL8139State *s)
1585 {
1586 uint32_t ret = s->Config0;
1587
1588 DPRINTF("Config0 read val=0x%02x\n", ret);
1589
1590 return ret;
1591 }
1592
1593 static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1594 {
1595 val &= 0xff;
1596
1597 DPRINTF("Config1 write val=0x%02x\n", val);
1598
1599 if (!rtl8139_config_writable(s)) {
1600 return;
1601 }
1602
1603 /* mask unwritable bits */
1604 val = SET_MASKED(val, 0xC, s->Config1);
1605
1606 s->Config1 = val;
1607 }
1608
1609 static uint32_t rtl8139_Config1_read(RTL8139State *s)
1610 {
1611 uint32_t ret = s->Config1;
1612
1613 DPRINTF("Config1 read val=0x%02x\n", ret);
1614
1615 return ret;
1616 }
1617
1618 static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1619 {
1620 val &= 0xff;
1621
1622 DPRINTF("Config3 write val=0x%02x\n", val);
1623
1624 if (!rtl8139_config_writable(s)) {
1625 return;
1626 }
1627
1628 /* mask unwritable bits */
1629 val = SET_MASKED(val, 0x8F, s->Config3);
1630
1631 s->Config3 = val;
1632 }
1633
1634 static uint32_t rtl8139_Config3_read(RTL8139State *s)
1635 {
1636 uint32_t ret = s->Config3;
1637
1638 DPRINTF("Config3 read val=0x%02x\n", ret);
1639
1640 return ret;
1641 }
1642
1643 static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1644 {
1645 val &= 0xff;
1646
1647 DPRINTF("Config4 write val=0x%02x\n", val);
1648
1649 if (!rtl8139_config_writable(s)) {
1650 return;
1651 }
1652
1653 /* mask unwritable bits */
1654 val = SET_MASKED(val, 0x0a, s->Config4);
1655
1656 s->Config4 = val;
1657 }
1658
1659 static uint32_t rtl8139_Config4_read(RTL8139State *s)
1660 {
1661 uint32_t ret = s->Config4;
1662
1663 DPRINTF("Config4 read val=0x%02x\n", ret);
1664
1665 return ret;
1666 }
1667
1668 static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1669 {
1670 val &= 0xff;
1671
1672 DPRINTF("Config5 write val=0x%02x\n", val);
1673
1674 /* mask unwritable bits */
1675 val = SET_MASKED(val, 0x80, s->Config5);
1676
1677 s->Config5 = val;
1678 }
1679
1680 static uint32_t rtl8139_Config5_read(RTL8139State *s)
1681 {
1682 uint32_t ret = s->Config5;
1683
1684 DPRINTF("Config5 read val=0x%02x\n", ret);
1685
1686 return ret;
1687 }
1688
1689 static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1690 {
1691 if (!rtl8139_transmitter_enabled(s))
1692 {
1693 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
1694 return;
1695 }
1696
1697 DPRINTF("TxConfig write val=0x%08x\n", val);
1698
1699 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1700
1701 s->TxConfig = val;
1702 }
1703
1704 static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1705 {
1706 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
1707
1708 uint32_t tc = s->TxConfig;
1709 tc &= 0xFFFFFF00;
1710 tc |= (val & 0x000000FF);
1711 rtl8139_TxConfig_write(s, tc);
1712 }
1713
1714 static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1715 {
1716 uint32_t ret = s->TxConfig;
1717
1718 DPRINTF("TxConfig read val=0x%04x\n", ret);
1719
1720 return ret;
1721 }
1722
1723 static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1724 {
1725 DPRINTF("RxConfig write val=0x%08x\n", val);
1726
1727 /* mask unwritable bits */
1728 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1729
1730 s->RxConfig = val;
1731
1732 /* reset buffer size and read/write pointers */
1733 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1734
1735 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
1736 }
1737
1738 static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1739 {
1740 uint32_t ret = s->RxConfig;
1741
1742 DPRINTF("RxConfig read val=0x%08x\n", ret);
1743
1744 return ret;
1745 }
1746
1747 static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1748 int do_interrupt, const uint8_t *dot1q_buf)
1749 {
1750 struct iovec *iov = NULL;
1751
1752 if (!size)
1753 {
1754 DPRINTF("+++ empty ethernet frame\n");
1755 return;
1756 }
1757
1758 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1759 iov = (struct iovec[3]) {
1760 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1761 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1762 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1763 .iov_len = size - ETHER_ADDR_LEN * 2 },
1764 };
1765 }
1766
1767 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1768 {
1769 size_t buf2_size;
1770 uint8_t *buf2;
1771
1772 if (iov) {
1773 buf2_size = iov_size(iov, 3);
1774 buf2 = g_malloc(buf2_size);
1775 iov_to_buf(iov, 3, buf2, 0, buf2_size);
1776 buf = buf2;
1777 }
1778
1779 DPRINTF("+++ transmit loopback mode\n");
1780 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
1781
1782 if (iov) {
1783 g_free(buf2);
1784 }
1785 }
1786 else
1787 {
1788 if (iov) {
1789 qemu_sendv_packet(&s->nic->nc, iov, 3);
1790 } else {
1791 qemu_send_packet(&s->nic->nc, buf, size);
1792 }
1793 }
1794 }
1795
1796 static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1797 {
1798 if (!rtl8139_transmitter_enabled(s))
1799 {
1800 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1801 "disabled\n", descriptor);
1802 return 0;
1803 }
1804
1805 if (s->TxStatus[descriptor] & TxHostOwns)
1806 {
1807 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1808 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
1809 return 0;
1810 }
1811
1812 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
1813
1814 int txsize = s->TxStatus[descriptor] & 0x1fff;
1815 uint8_t txbuffer[0x2000];
1816
1817 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1818 txsize, s->TxAddr[descriptor]);
1819
1820 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
1821
1822 /* Mark descriptor as transferred */
1823 s->TxStatus[descriptor] |= TxHostOwns;
1824 s->TxStatus[descriptor] |= TxStatOK;
1825
1826 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
1827
1828 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1829 descriptor);
1830
1831 /* update interrupt */
1832 s->IntrStatus |= TxOK;
1833 rtl8139_update_irq(s);
1834
1835 return 1;
1836 }
1837
1838 /* structures and macros for task offloading */
1839 typedef struct ip_header
1840 {
1841 uint8_t ip_ver_len; /* version and header length */
1842 uint8_t ip_tos; /* type of service */
1843 uint16_t ip_len; /* total length */
1844 uint16_t ip_id; /* identification */
1845 uint16_t ip_off; /* fragment offset field */
1846 uint8_t ip_ttl; /* time to live */
1847 uint8_t ip_p; /* protocol */
1848 uint16_t ip_sum; /* checksum */
1849 uint32_t ip_src,ip_dst; /* source and dest address */
1850 } ip_header;
1851
1852 #define IP_HEADER_VERSION_4 4
1853 #define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1854 #define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1855
1856 typedef struct tcp_header
1857 {
1858 uint16_t th_sport; /* source port */
1859 uint16_t th_dport; /* destination port */
1860 uint32_t th_seq; /* sequence number */
1861 uint32_t th_ack; /* acknowledgement number */
1862 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1863 uint16_t th_win; /* window */
1864 uint16_t th_sum; /* checksum */
1865 uint16_t th_urp; /* urgent pointer */
1866 } tcp_header;
1867
1868 typedef struct udp_header
1869 {
1870 uint16_t uh_sport; /* source port */
1871 uint16_t uh_dport; /* destination port */
1872 uint16_t uh_ulen; /* udp length */
1873 uint16_t uh_sum; /* udp checksum */
1874 } udp_header;
1875
1876 typedef struct ip_pseudo_header
1877 {
1878 uint32_t ip_src;
1879 uint32_t ip_dst;
1880 uint8_t zeros;
1881 uint8_t ip_proto;
1882 uint16_t ip_payload;
1883 } ip_pseudo_header;
1884
1885 #define IP_PROTO_TCP 6
1886 #define IP_PROTO_UDP 17
1887
1888 #define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1889 #define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1890 #define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1891
1892 #define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1893
1894 #define TCP_FLAG_FIN 0x01
1895 #define TCP_FLAG_PUSH 0x08
1896
1897 /* produces ones' complement sum of data */
1898 static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1899 {
1900 uint32_t result = 0;
1901
1902 for (; len > 1; data+=2, len-=2)
1903 {
1904 result += *(uint16_t*)data;
1905 }
1906
1907 /* add the remainder byte */
1908 if (len)
1909 {
1910 uint8_t odd[2] = {*data, 0};
1911 result += *(uint16_t*)odd;
1912 }
1913
1914 while (result>>16)
1915 result = (result & 0xffff) + (result >> 16);
1916
1917 return result;
1918 }
1919
1920 static uint16_t ip_checksum(void *data, size_t len)
1921 {
1922 return ~ones_complement_sum((uint8_t*)data, len);
1923 }
1924
1925 static int rtl8139_cplus_transmit_one(RTL8139State *s)
1926 {
1927 if (!rtl8139_transmitter_enabled(s))
1928 {
1929 DPRINTF("+++ C+ mode: transmitter disabled\n");
1930 return 0;
1931 }
1932
1933 if (!rtl8139_cp_transmitter_enabled(s))
1934 {
1935 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
1936 return 0 ;
1937 }
1938
1939 int descriptor = s->currCPlusTxDesc;
1940
1941 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
1942
1943 /* Normal priority ring */
1944 cplus_tx_ring_desc += 16 * descriptor;
1945
1946 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
1947 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
1948 s->TxAddr[0], cplus_tx_ring_desc);
1949
1950 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1951
1952 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
1953 txdw0 = le32_to_cpu(val);
1954 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
1955 txdw1 = le32_to_cpu(val);
1956 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
1957 txbufLO = le32_to_cpu(val);
1958 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
1959 txbufHI = le32_to_cpu(val);
1960
1961 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1962 txdw0, txdw1, txbufLO, txbufHI);
1963
1964 /* w0 ownership flag */
1965 #define CP_TX_OWN (1<<31)
1966 /* w0 end of ring flag */
1967 #define CP_TX_EOR (1<<30)
1968 /* first segment of received packet flag */
1969 #define CP_TX_FS (1<<29)
1970 /* last segment of received packet flag */
1971 #define CP_TX_LS (1<<28)
1972 /* large send packet flag */
1973 #define CP_TX_LGSEN (1<<27)
1974 /* large send MSS mask, bits 16...25 */
1975 #define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1976
1977 /* IP checksum offload flag */
1978 #define CP_TX_IPCS (1<<18)
1979 /* UDP checksum offload flag */
1980 #define CP_TX_UDPCS (1<<17)
1981 /* TCP checksum offload flag */
1982 #define CP_TX_TCPCS (1<<16)
1983
1984 /* w0 bits 0...15 : buffer size */
1985 #define CP_TX_BUFFER_SIZE (1<<16)
1986 #define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
1987 /* w1 add tag flag */
1988 #define CP_TX_TAGC (1<<17)
1989 /* w1 bits 0...15 : VLAN tag (big endian) */
1990 #define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
1991 /* w2 low 32bit of Rx buffer ptr */
1992 /* w3 high 32bit of Rx buffer ptr */
1993
1994 /* set after transmission */
1995 /* FIFO underrun flag */
1996 #define CP_TX_STATUS_UNF (1<<25)
1997 /* transmit error summary flag, valid if set any of three below */
1998 #define CP_TX_STATUS_TES (1<<23)
1999 /* out-of-window collision flag */
2000 #define CP_TX_STATUS_OWC (1<<22)
2001 /* link failure flag */
2002 #define CP_TX_STATUS_LNKF (1<<21)
2003 /* excessive collisions flag */
2004 #define CP_TX_STATUS_EXC (1<<20)
2005
2006 if (!(txdw0 & CP_TX_OWN))
2007 {
2008 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
2009 return 0 ;
2010 }
2011
2012 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
2013
2014 if (txdw0 & CP_TX_FS)
2015 {
2016 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2017 "descriptor\n", descriptor);
2018
2019 /* reset internal buffer offset */
2020 s->cplus_txbuffer_offset = 0;
2021 }
2022
2023 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
2024 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
2025
2026 /* make sure we have enough space to assemble the packet */
2027 if (!s->cplus_txbuffer)
2028 {
2029 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
2030 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
2031 s->cplus_txbuffer_offset = 0;
2032
2033 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2034 s->cplus_txbuffer_len);
2035 }
2036
2037 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
2038 {
2039 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2040 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2041 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2042 "length to %d\n", txsize);
2043 }
2044
2045 if (!s->cplus_txbuffer)
2046 {
2047 /* out of memory */
2048
2049 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2050 s->cplus_txbuffer_len);
2051
2052 /* update tally counter */
2053 ++s->tally_counters.TxERR;
2054 ++s->tally_counters.TxAbt;
2055
2056 return 0;
2057 }
2058
2059 /* append more data to the packet */
2060
2061 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
2062 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2063 s->cplus_txbuffer_offset);
2064
2065 pci_dma_read(&s->dev, tx_addr,
2066 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
2067 s->cplus_txbuffer_offset += txsize;
2068
2069 /* seek to next Rx descriptor */
2070 if (txdw0 & CP_TX_EOR)
2071 {
2072 s->currCPlusTxDesc = 0;
2073 }
2074 else
2075 {
2076 ++s->currCPlusTxDesc;
2077 if (s->currCPlusTxDesc >= 64)
2078 s->currCPlusTxDesc = 0;
2079 }
2080
2081 /* transfer ownership to target */
2082 txdw0 &= ~CP_RX_OWN;
2083
2084 /* reset error indicator bits */
2085 txdw0 &= ~CP_TX_STATUS_UNF;
2086 txdw0 &= ~CP_TX_STATUS_TES;
2087 txdw0 &= ~CP_TX_STATUS_OWC;
2088 txdw0 &= ~CP_TX_STATUS_LNKF;
2089 txdw0 &= ~CP_TX_STATUS_EXC;
2090
2091 /* update ring data */
2092 val = cpu_to_le32(txdw0);
2093 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
2094
2095 /* Now decide if descriptor being processed is holding the last segment of packet */
2096 if (txdw0 & CP_TX_LS)
2097 {
2098 uint8_t dot1q_buffer_space[VLAN_HLEN];
2099 uint16_t *dot1q_buffer;
2100
2101 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2102 descriptor);
2103
2104 /* can transfer fully assembled packet */
2105
2106 uint8_t *saved_buffer = s->cplus_txbuffer;
2107 int saved_size = s->cplus_txbuffer_offset;
2108 int saved_buffer_len = s->cplus_txbuffer_len;
2109
2110 /* create vlan tag */
2111 if (txdw1 & CP_TX_TAGC) {
2112 /* the vlan tag is in BE byte order in the descriptor
2113 * BE + le_to_cpu() + ~swap()~ = cpu */
2114 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2115 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
2116
2117 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2118 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2119 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2120 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2121 } else {
2122 dot1q_buffer = NULL;
2123 }
2124
2125 /* reset the card space to protect from recursive call */
2126 s->cplus_txbuffer = NULL;
2127 s->cplus_txbuffer_offset = 0;
2128 s->cplus_txbuffer_len = 0;
2129
2130 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
2131 {
2132 DPRINTF("+++ C+ mode offloaded task checksum\n");
2133
2134 /* ip packet header */
2135 ip_header *ip = NULL;
2136 int hlen = 0;
2137 uint8_t ip_protocol = 0;
2138 uint16_t ip_data_len = 0;
2139
2140 uint8_t *eth_payload_data = NULL;
2141 size_t eth_payload_len = 0;
2142
2143 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
2144 if (proto == ETH_P_IP)
2145 {
2146 DPRINTF("+++ C+ mode has IP packet\n");
2147
2148 /* not aligned */
2149 eth_payload_data = saved_buffer + ETH_HLEN;
2150 eth_payload_len = saved_size - ETH_HLEN;
2151
2152 ip = (ip_header*)eth_payload_data;
2153
2154 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
2155 DPRINTF("+++ C+ mode packet has bad IP version %d "
2156 "expected %d\n", IP_HEADER_VERSION(ip),
2157 IP_HEADER_VERSION_4);
2158 ip = NULL;
2159 } else {
2160 hlen = IP_HEADER_LENGTH(ip);
2161 ip_protocol = ip->ip_p;
2162 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
2163 }
2164 }
2165
2166 if (ip)
2167 {
2168 if (txdw0 & CP_TX_IPCS)
2169 {
2170 DPRINTF("+++ C+ mode need IP checksum\n");
2171
2172 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
2173 /* bad packet header len */
2174 /* or packet too short */
2175 }
2176 else
2177 {
2178 ip->ip_sum = 0;
2179 ip->ip_sum = ip_checksum(ip, hlen);
2180 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2181 hlen, ip->ip_sum);
2182 }
2183 }
2184
2185 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
2186 {
2187 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
2188
2189 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2190 "frame data %d specified MSS=%d\n", ETH_MTU,
2191 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
2192
2193 int tcp_send_offset = 0;
2194 int send_count = 0;
2195
2196 /* maximum IP header length is 60 bytes */
2197 uint8_t saved_ip_header[60];
2198
2199 /* save IP header template; data area is used in tcp checksum calculation */
2200 memcpy(saved_ip_header, eth_payload_data, hlen);
2201
2202 /* a placeholder for checksum calculation routine in tcp case */
2203 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2204 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2205
2206 /* pointer to TCP header */
2207 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2208
2209 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2210
2211 /* ETH_MTU = ip header len + tcp header len + payload */
2212 int tcp_data_len = ip_data_len - tcp_hlen;
2213 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2214
2215 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2216 "data len %d TCP chunk size %d\n", ip_data_len,
2217 tcp_hlen, tcp_data_len, tcp_chunk_size);
2218
2219 /* note the cycle below overwrites IP header data,
2220 but restores it from saved_ip_header before sending packet */
2221
2222 int is_last_frame = 0;
2223
2224 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2225 {
2226 uint16_t chunk_size = tcp_chunk_size;
2227
2228 /* check if this is the last frame */
2229 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2230 {
2231 is_last_frame = 1;
2232 chunk_size = tcp_data_len - tcp_send_offset;
2233 }
2234
2235 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2236 be32_to_cpu(p_tcp_hdr->th_seq));
2237
2238 /* add 4 TCP pseudoheader fields */
2239 /* copy IP source and destination fields */
2240 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2241
2242 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2243 "packet with %d bytes data\n", tcp_hlen +
2244 chunk_size);
2245
2246 if (tcp_send_offset)
2247 {
2248 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2249 }
2250
2251 /* keep PUSH and FIN flags only for the last frame */
2252 if (!is_last_frame)
2253 {
2254 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2255 }
2256
2257 /* recalculate TCP checksum */
2258 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2259 p_tcpip_hdr->zeros = 0;
2260 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2261 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2262
2263 p_tcp_hdr->th_sum = 0;
2264
2265 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
2266 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2267 tcp_checksum);
2268
2269 p_tcp_hdr->th_sum = tcp_checksum;
2270
2271 /* restore IP header */
2272 memcpy(eth_payload_data, saved_ip_header, hlen);
2273
2274 /* set IP data length and recalculate IP checksum */
2275 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2276
2277 /* increment IP id for subsequent frames */
2278 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2279
2280 ip->ip_sum = 0;
2281 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
2282 DPRINTF("+++ C+ mode TSO IP header len=%d "
2283 "checksum=%04x\n", hlen, ip->ip_sum);
2284
2285 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
2286 DPRINTF("+++ C+ mode TSO transferring packet size "
2287 "%d\n", tso_send_size);
2288 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2289 0, (uint8_t *) dot1q_buffer);
2290
2291 /* add transferred count to TCP sequence number */
2292 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2293 ++send_count;
2294 }
2295
2296 /* Stop sending this frame */
2297 saved_size = 0;
2298 }
2299 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2300 {
2301 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
2302
2303 /* maximum IP header length is 60 bytes */
2304 uint8_t saved_ip_header[60];
2305 memcpy(saved_ip_header, eth_payload_data, hlen);
2306
2307 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2308 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2309
2310 /* add 4 TCP pseudoheader fields */
2311 /* copy IP source and destination fields */
2312 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2313
2314 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
2315 {
2316 DPRINTF("+++ C+ mode calculating TCP checksum for "
2317 "packet with %d bytes data\n", ip_data_len);
2318
2319 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2320 p_tcpip_hdr->zeros = 0;
2321 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2322 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2323
2324 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
2325
2326 p_tcp_hdr->th_sum = 0;
2327
2328 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2329 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2330 tcp_checksum);
2331
2332 p_tcp_hdr->th_sum = tcp_checksum;
2333 }
2334 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
2335 {
2336 DPRINTF("+++ C+ mode calculating UDP checksum for "
2337 "packet with %d bytes data\n", ip_data_len);
2338
2339 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2340 p_udpip_hdr->zeros = 0;
2341 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2342 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
2343
2344 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
2345
2346 p_udp_hdr->uh_sum = 0;
2347
2348 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
2349 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2350 udp_checksum);
2351
2352 p_udp_hdr->uh_sum = udp_checksum;
2353 }
2354
2355 /* restore IP header */
2356 memcpy(eth_payload_data, saved_ip_header, hlen);
2357 }
2358 }
2359 }
2360
2361 /* update tally counter */
2362 ++s->tally_counters.TxOk;
2363
2364 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
2365
2366 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2367 (uint8_t *) dot1q_buffer);
2368
2369 /* restore card space if there was no recursion and reset offset */
2370 if (!s->cplus_txbuffer)
2371 {
2372 s->cplus_txbuffer = saved_buffer;
2373 s->cplus_txbuffer_len = saved_buffer_len;
2374 s->cplus_txbuffer_offset = 0;
2375 }
2376 else
2377 {
2378 g_free(saved_buffer);
2379 }
2380 }
2381 else
2382 {
2383 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
2384 }
2385
2386 return 1;
2387 }
2388
2389 static void rtl8139_cplus_transmit(RTL8139State *s)
2390 {
2391 int txcount = 0;
2392
2393 while (rtl8139_cplus_transmit_one(s))
2394 {
2395 ++txcount;
2396 }
2397
2398 /* Mark transfer completed */
2399 if (!txcount)
2400 {
2401 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2402 s->currCPlusTxDesc);
2403 }
2404 else
2405 {
2406 /* update interrupt status */
2407 s->IntrStatus |= TxOK;
2408 rtl8139_update_irq(s);
2409 }
2410 }
2411
2412 static void rtl8139_transmit(RTL8139State *s)
2413 {
2414 int descriptor = s->currTxDesc, txcount = 0;
2415
2416 /*while*/
2417 if (rtl8139_transmit_one(s, descriptor))
2418 {
2419 ++s->currTxDesc;
2420 s->currTxDesc %= 4;
2421 ++txcount;
2422 }
2423
2424 /* Mark transfer completed */
2425 if (!txcount)
2426 {
2427 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2428 s->currTxDesc);
2429 }
2430 }
2431
2432 static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2433 {
2434
2435 int descriptor = txRegOffset/4;
2436
2437 /* handle C+ transmit mode register configuration */
2438
2439 if (s->cplus_enabled)
2440 {
2441 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2442 "descriptor=%d\n", txRegOffset, val, descriptor);
2443
2444 /* handle Dump Tally Counters command */
2445 s->TxStatus[descriptor] = val;
2446
2447 if (descriptor == 0 && (val & 0x8))
2448 {
2449 target_phys_addr_t tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
2450
2451 /* dump tally counters to specified memory location */
2452 RTL8139TallyCounters_dma_write(s, tc_addr);
2453
2454 /* mark dump completed */
2455 s->TxStatus[0] &= ~0x8;
2456 }
2457
2458 return;
2459 }
2460
2461 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2462 txRegOffset, val, descriptor);
2463
2464 /* mask only reserved bits */
2465 val &= ~0xff00c000; /* these bits are reset on write */
2466 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2467
2468 s->TxStatus[descriptor] = val;
2469
2470 /* attempt to start transmission */
2471 rtl8139_transmit(s);
2472 }
2473
2474 static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint8_t addr, int size)
2475 {
2476 uint32_t reg = (addr - TxStatus0) / 4;
2477 uint32_t offset = addr & 0x3;
2478 uint32_t ret = 0;
2479
2480 if (addr & (size - 1)) {
2481 DPRINTF("not implemented read for TxStatus addr=0x%x size=0x%x\n", addr,
2482 size);
2483 return ret;
2484 }
2485
2486 switch (size) {
2487 case 1: /* fall through */
2488 case 2: /* fall through */
2489 case 4:
2490 ret = (s->TxStatus[reg] >> offset * 8) & ((1 << (size * 8)) - 1);
2491 DPRINTF("TxStatus[%d] read addr=0x%x size=0x%x val=0x%08x\n", reg, addr,
2492 size, ret);
2493 break;
2494 default:
2495 DPRINTF("unsupported size 0x%x of TxStatus reading\n", size);
2496 break;
2497 }
2498
2499 return ret;
2500 }
2501
2502 static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2503 {
2504 uint16_t ret = 0;
2505
2506 /* Simulate TSAD, it is read only anyway */
2507
2508 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2509 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2510 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2511 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2512
2513 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2514 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2515 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2516 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
2517
2518 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2519 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2520 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2521 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
2522
2523 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2524 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2525 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2526 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
2527
2528
2529 DPRINTF("TSAD read val=0x%04x\n", ret);
2530
2531 return ret;
2532 }
2533
2534 static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2535 {
2536 uint16_t ret = s->CSCR;
2537
2538 DPRINTF("CSCR read val=0x%04x\n", ret);
2539
2540 return ret;
2541 }
2542
2543 static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2544 {
2545 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
2546
2547 s->TxAddr[txAddrOffset/4] = val;
2548 }
2549
2550 static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2551 {
2552 uint32_t ret = s->TxAddr[txAddrOffset/4];
2553
2554 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
2555
2556 return ret;
2557 }
2558
2559 static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2560 {
2561 DPRINTF("RxBufPtr write val=0x%04x\n", val);
2562
2563 /* this value is off by 16 */
2564 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2565
2566 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2567 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
2568 }
2569
2570 static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2571 {
2572 /* this value is off by 16 */
2573 uint32_t ret = s->RxBufPtr - 0x10;
2574
2575 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
2576
2577 return ret;
2578 }
2579
2580 static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2581 {
2582 /* this value is NOT off by 16 */
2583 uint32_t ret = s->RxBufAddr;
2584
2585 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
2586
2587 return ret;
2588 }
2589
2590 static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2591 {
2592 DPRINTF("RxBuf write val=0x%08x\n", val);
2593
2594 s->RxBuf = val;
2595
2596 /* may need to reset rxring here */
2597 }
2598
2599 static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2600 {
2601 uint32_t ret = s->RxBuf;
2602
2603 DPRINTF("RxBuf read val=0x%08x\n", ret);
2604
2605 return ret;
2606 }
2607
2608 static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2609 {
2610 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
2611
2612 /* mask unwritable bits */
2613 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2614
2615 s->IntrMask = val;
2616
2617 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2618 rtl8139_update_irq(s);
2619
2620 }
2621
2622 static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2623 {
2624 uint32_t ret = s->IntrMask;
2625
2626 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
2627
2628 return ret;
2629 }
2630
2631 static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2632 {
2633 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
2634
2635 #if 0
2636
2637 /* writing to ISR has no effect */
2638
2639 return;
2640
2641 #else
2642 uint16_t newStatus = s->IntrStatus & ~val;
2643
2644 /* mask unwritable bits */
2645 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2646
2647 /* writing 1 to interrupt status register bit clears it */
2648 s->IntrStatus = 0;
2649 rtl8139_update_irq(s);
2650
2651 s->IntrStatus = newStatus;
2652 /*
2653 * Computing if we miss an interrupt here is not that correct but
2654 * considered that we should have had already an interrupt
2655 * and probably emulated is slower is better to assume this resetting was
2656 * done before testing on previous rtl8139_update_irq lead to IRQ losing
2657 */
2658 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2659 rtl8139_update_irq(s);
2660
2661 #endif
2662 }
2663
2664 static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2665 {
2666 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2667
2668 uint32_t ret = s->IntrStatus;
2669
2670 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
2671
2672 #if 0
2673
2674 /* reading ISR clears all interrupts */
2675 s->IntrStatus = 0;
2676
2677 rtl8139_update_irq(s);
2678
2679 #endif
2680
2681 return ret;
2682 }
2683
2684 static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2685 {
2686 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
2687
2688 /* mask unwritable bits */
2689 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2690
2691 s->MultiIntr = val;
2692 }
2693
2694 static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2695 {
2696 uint32_t ret = s->MultiIntr;
2697
2698 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
2699
2700 return ret;
2701 }
2702
2703 static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2704 {
2705 RTL8139State *s = opaque;
2706
2707 switch (addr)
2708 {
2709 case MAC0 ... MAC0+5:
2710 s->phys[addr - MAC0] = val;
2711 break;
2712 case MAC0+6 ... MAC0+7:
2713 /* reserved */
2714 break;
2715 case MAR0 ... MAR0+7:
2716 s->mult[addr - MAR0] = val;
2717 break;
2718 case ChipCmd:
2719 rtl8139_ChipCmd_write(s, val);
2720 break;
2721 case Cfg9346:
2722 rtl8139_Cfg9346_write(s, val);
2723 break;
2724 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2725 rtl8139_TxConfig_writeb(s, val);
2726 break;
2727 case Config0:
2728 rtl8139_Config0_write(s, val);
2729 break;
2730 case Config1:
2731 rtl8139_Config1_write(s, val);
2732 break;
2733 case Config3:
2734 rtl8139_Config3_write(s, val);
2735 break;
2736 case Config4:
2737 rtl8139_Config4_write(s, val);
2738 break;
2739 case Config5:
2740 rtl8139_Config5_write(s, val);
2741 break;
2742 case MediaStatus:
2743 /* ignore */
2744 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2745 val);
2746 break;
2747
2748 case HltClk:
2749 DPRINTF("HltClk write val=0x%08x\n", val);
2750 if (val == 'R')
2751 {
2752 s->clock_enabled = 1;
2753 }
2754 else if (val == 'H')
2755 {
2756 s->clock_enabled = 0;
2757 }
2758 break;
2759
2760 case TxThresh:
2761 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
2762 s->TxThresh = val;
2763 break;
2764
2765 case TxPoll:
2766 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
2767 if (val & (1 << 7))
2768 {
2769 DPRINTF("C+ TxPoll high priority transmission (not "
2770 "implemented)\n");
2771 //rtl8139_cplus_transmit(s);
2772 }
2773 if (val & (1 << 6))
2774 {
2775 DPRINTF("C+ TxPoll normal priority transmission\n");
2776 rtl8139_cplus_transmit(s);
2777 }
2778
2779 break;
2780
2781 default:
2782 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2783 val);
2784 break;
2785 }
2786 }
2787
2788 static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2789 {
2790 RTL8139State *s = opaque;
2791
2792 switch (addr)
2793 {
2794 case IntrMask:
2795 rtl8139_IntrMask_write(s, val);
2796 break;
2797
2798 case IntrStatus:
2799 rtl8139_IntrStatus_write(s, val);
2800 break;
2801
2802 case MultiIntr:
2803 rtl8139_MultiIntr_write(s, val);
2804 break;
2805
2806 case RxBufPtr:
2807 rtl8139_RxBufPtr_write(s, val);
2808 break;
2809
2810 case BasicModeCtrl:
2811 rtl8139_BasicModeCtrl_write(s, val);
2812 break;
2813 case BasicModeStatus:
2814 rtl8139_BasicModeStatus_write(s, val);
2815 break;
2816 case NWayAdvert:
2817 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
2818 s->NWayAdvert = val;
2819 break;
2820 case NWayLPAR:
2821 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
2822 break;
2823 case NWayExpansion:
2824 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
2825 s->NWayExpansion = val;
2826 break;
2827
2828 case CpCmd:
2829 rtl8139_CpCmd_write(s, val);
2830 break;
2831
2832 case IntrMitigate:
2833 rtl8139_IntrMitigate_write(s, val);
2834 break;
2835
2836 default:
2837 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2838 addr, val);
2839
2840 rtl8139_io_writeb(opaque, addr, val & 0xff);
2841 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2842 break;
2843 }
2844 }
2845
2846 static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2847 {
2848 int64_t pci_time, next_time;
2849 uint32_t low_pci;
2850
2851 DPRINTF("entered rtl8139_set_next_tctr_time\n");
2852
2853 if (s->TimerExpire && current_time >= s->TimerExpire) {
2854 s->IntrStatus |= PCSTimeout;
2855 rtl8139_update_irq(s);
2856 }
2857
2858 /* Set QEMU timer only if needed that is
2859 * - TimerInt <> 0 (we have a timer)
2860 * - mask = 1 (we want an interrupt timer)
2861 * - irq = 0 (irq is not already active)
2862 * If any of above change we need to compute timer again
2863 * Also we must check if timer is passed without QEMU timer
2864 */
2865 s->TimerExpire = 0;
2866 if (!s->TimerInt) {
2867 return;
2868 }
2869
2870 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2871 get_ticks_per_sec());
2872 low_pci = pci_time & 0xffffffff;
2873 pci_time = pci_time - low_pci + s->TimerInt;
2874 if (low_pci >= s->TimerInt) {
2875 pci_time += 0x100000000LL;
2876 }
2877 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2878 PCI_FREQUENCY);
2879 s->TimerExpire = next_time;
2880
2881 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2882 qemu_mod_timer(s->timer, next_time);
2883 }
2884 }
2885
2886 static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2887 {
2888 RTL8139State *s = opaque;
2889
2890 switch (addr)
2891 {
2892 case RxMissed:
2893 DPRINTF("RxMissed clearing on write\n");
2894 s->RxMissed = 0;
2895 break;
2896
2897 case TxConfig:
2898 rtl8139_TxConfig_write(s, val);
2899 break;
2900
2901 case RxConfig:
2902 rtl8139_RxConfig_write(s, val);
2903 break;
2904
2905 case TxStatus0 ... TxStatus0+4*4-1:
2906 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2907 break;
2908
2909 case TxAddr0 ... TxAddr0+4*4-1:
2910 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2911 break;
2912
2913 case RxBuf:
2914 rtl8139_RxBuf_write(s, val);
2915 break;
2916
2917 case RxRingAddrLO:
2918 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
2919 s->RxRingAddrLO = val;
2920 break;
2921
2922 case RxRingAddrHI:
2923 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
2924 s->RxRingAddrHI = val;
2925 break;
2926
2927 case Timer:
2928 DPRINTF("TCTR Timer reset on write\n");
2929 s->TCTR_base = qemu_get_clock_ns(vm_clock);
2930 rtl8139_set_next_tctr_time(s, s->TCTR_base);
2931 break;
2932
2933 case FlashReg:
2934 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
2935 if (s->TimerInt != val) {
2936 s->TimerInt = val;
2937 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
2938 }
2939 break;
2940
2941 default:
2942 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2943 addr, val);
2944 rtl8139_io_writeb(opaque, addr, val & 0xff);
2945 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2946 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2947 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
2948 break;
2949 }
2950 }
2951
2952 static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2953 {
2954 RTL8139State *s = opaque;
2955 int ret;
2956
2957 switch (addr)
2958 {
2959 case MAC0 ... MAC0+5:
2960 ret = s->phys[addr - MAC0];
2961 break;
2962 case MAC0+6 ... MAC0+7:
2963 ret = 0;
2964 break;
2965 case MAR0 ... MAR0+7:
2966 ret = s->mult[addr - MAR0];
2967 break;
2968 case TxStatus0 ... TxStatus0+4*4-1:
2969 ret = rtl8139_TxStatus_read(s, addr, 1);
2970 break;
2971 case ChipCmd:
2972 ret = rtl8139_ChipCmd_read(s);
2973 break;
2974 case Cfg9346:
2975 ret = rtl8139_Cfg9346_read(s);
2976 break;
2977 case Config0:
2978 ret = rtl8139_Config0_read(s);
2979 break;
2980 case Config1:
2981 ret = rtl8139_Config1_read(s);
2982 break;
2983 case Config3:
2984 ret = rtl8139_Config3_read(s);
2985 break;
2986 case Config4:
2987 ret = rtl8139_Config4_read(s);
2988 break;
2989 case Config5:
2990 ret = rtl8139_Config5_read(s);
2991 break;
2992
2993 case MediaStatus:
2994 ret = 0xd0;
2995 DPRINTF("MediaStatus read 0x%x\n", ret);
2996 break;
2997
2998 case HltClk:
2999 ret = s->clock_enabled;
3000 DPRINTF("HltClk read 0x%x\n", ret);
3001 break;
3002
3003 case PCIRevisionID:
3004 ret = RTL8139_PCI_REVID;
3005 DPRINTF("PCI Revision ID read 0x%x\n", ret);
3006 break;
3007
3008 case TxThresh:
3009 ret = s->TxThresh;
3010 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
3011 break;
3012
3013 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3014 ret = s->TxConfig >> 24;
3015 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
3016 break;
3017
3018 default:
3019 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
3020 ret = 0;
3021 break;
3022 }
3023
3024 return ret;
3025 }
3026
3027 static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3028 {
3029 RTL8139State *s = opaque;
3030 uint32_t ret;
3031
3032 switch (addr)
3033 {
3034 case TxAddr0 ... TxAddr0+4*4-1:
3035 ret = rtl8139_TxStatus_read(s, addr, 2);
3036 break;
3037 case IntrMask:
3038 ret = rtl8139_IntrMask_read(s);
3039 break;
3040
3041 case IntrStatus:
3042 ret = rtl8139_IntrStatus_read(s);
3043 break;
3044
3045 case MultiIntr:
3046 ret = rtl8139_MultiIntr_read(s);
3047 break;
3048
3049 case RxBufPtr:
3050 ret = rtl8139_RxBufPtr_read(s);
3051 break;
3052
3053 case RxBufAddr:
3054 ret = rtl8139_RxBufAddr_read(s);
3055 break;
3056
3057 case BasicModeCtrl:
3058 ret = rtl8139_BasicModeCtrl_read(s);
3059 break;
3060 case BasicModeStatus:
3061 ret = rtl8139_BasicModeStatus_read(s);
3062 break;
3063 case NWayAdvert:
3064 ret = s->NWayAdvert;
3065 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
3066 break;
3067 case NWayLPAR:
3068 ret = s->NWayLPAR;
3069 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
3070 break;
3071 case NWayExpansion:
3072 ret = s->NWayExpansion;
3073 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
3074 break;
3075
3076 case CpCmd:
3077 ret = rtl8139_CpCmd_read(s);
3078 break;
3079
3080 case IntrMitigate:
3081 ret = rtl8139_IntrMitigate_read(s);
3082 break;
3083
3084 case TxSummary:
3085 ret = rtl8139_TSAD_read(s);
3086 break;
3087
3088 case CSCR:
3089 ret = rtl8139_CSCR_read(s);
3090 break;
3091
3092 default:
3093 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
3094
3095 ret = rtl8139_io_readb(opaque, addr);
3096 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3097
3098 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
3099 break;
3100 }
3101
3102 return ret;
3103 }
3104
3105 static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3106 {
3107 RTL8139State *s = opaque;
3108 uint32_t ret;
3109
3110 switch (addr)
3111 {
3112 case RxMissed:
3113 ret = s->RxMissed;
3114
3115 DPRINTF("RxMissed read val=0x%08x\n", ret);
3116 break;
3117
3118 case TxConfig:
3119 ret = rtl8139_TxConfig_read(s);
3120 break;
3121
3122 case RxConfig:
3123 ret = rtl8139_RxConfig_read(s);
3124 break;
3125
3126 case TxStatus0 ... TxStatus0+4*4-1:
3127 ret = rtl8139_TxStatus_read(s, addr, 4);
3128 break;
3129
3130 case TxAddr0 ... TxAddr0+4*4-1:
3131 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3132 break;
3133
3134 case RxBuf:
3135 ret = rtl8139_RxBuf_read(s);
3136 break;
3137
3138 case RxRingAddrLO:
3139 ret = s->RxRingAddrLO;
3140 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
3141 break;
3142
3143 case RxRingAddrHI:
3144 ret = s->RxRingAddrHI;
3145 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
3146 break;
3147
3148 case Timer:
3149 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
3150 PCI_FREQUENCY, get_ticks_per_sec());
3151 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
3152 break;
3153
3154 case FlashReg:
3155 ret = s->TimerInt;
3156 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
3157 break;
3158
3159 default:
3160 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
3161
3162 ret = rtl8139_io_readb(opaque, addr);
3163 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3164 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3165 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
3166
3167 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
3168 break;
3169 }
3170
3171 return ret;
3172 }
3173
3174 /* */
3175
3176 static void rtl8139_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
3177 {
3178 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3179 }
3180
3181 static void rtl8139_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
3182 {
3183 rtl8139_io_writew(opaque, addr & 0xFF, val);
3184 }
3185
3186 static void rtl8139_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
3187 {
3188 rtl8139_io_writel(opaque, addr & 0xFF, val);
3189 }
3190
3191 static uint32_t rtl8139_ioport_readb(void *opaque, uint32_t addr)
3192 {
3193 return rtl8139_io_readb(opaque, addr & 0xFF);
3194 }
3195
3196 static uint32_t rtl8139_ioport_readw(void *opaque, uint32_t addr)
3197 {
3198 return rtl8139_io_readw(opaque, addr & 0xFF);
3199 }
3200
3201 static uint32_t rtl8139_ioport_readl(void *opaque, uint32_t addr)
3202 {
3203 return rtl8139_io_readl(opaque, addr & 0xFF);
3204 }
3205
3206 /* */
3207
3208 static void rtl8139_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
3209 {
3210 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3211 }
3212
3213 static void rtl8139_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
3214 {
3215 rtl8139_io_writew(opaque, addr & 0xFF, val);
3216 }
3217
3218 static void rtl8139_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
3219 {
3220 rtl8139_io_writel(opaque, addr & 0xFF, val);
3221 }
3222
3223 static uint32_t rtl8139_mmio_readb(void *opaque, target_phys_addr_t addr)
3224 {
3225 return rtl8139_io_readb(opaque, addr & 0xFF);
3226 }
3227
3228 static uint32_t rtl8139_mmio_readw(void *opaque, target_phys_addr_t addr)
3229 {
3230 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
3231 return val;
3232 }
3233
3234 static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
3235 {
3236 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
3237 return val;
3238 }
3239
3240 static int rtl8139_post_load(void *opaque, int version_id)
3241 {
3242 RTL8139State* s = opaque;
3243 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3244 if (version_id < 4) {
3245 s->cplus_enabled = s->CpCmd != 0;
3246 }
3247
3248 return 0;
3249 }
3250
3251 static bool rtl8139_hotplug_ready_needed(void *opaque)
3252 {
3253 return qdev_machine_modified();
3254 }
3255
3256 static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3257 .name = "rtl8139/hotplug_ready",
3258 .version_id = 1,
3259 .minimum_version_id = 1,
3260 .minimum_version_id_old = 1,
3261 .fields = (VMStateField []) {
3262 VMSTATE_END_OF_LIST()
3263 }
3264 };
3265
3266 static void rtl8139_pre_save(void *opaque)
3267 {
3268 RTL8139State* s = opaque;
3269 int64_t current_time = qemu_get_clock_ns(vm_clock);
3270
3271 /* set IntrStatus correctly */
3272 rtl8139_set_next_tctr_time(s, current_time);
3273 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3274 get_ticks_per_sec());
3275 s->rtl8139_mmio_io_addr_dummy = 0;
3276 }
3277
3278 static const VMStateDescription vmstate_rtl8139 = {
3279 .name = "rtl8139",
3280 .version_id = 4,
3281 .minimum_version_id = 3,
3282 .minimum_version_id_old = 3,
3283 .post_load = rtl8139_post_load,
3284 .pre_save = rtl8139_pre_save,
3285 .fields = (VMStateField []) {
3286 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3287 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3288 VMSTATE_BUFFER(mult, RTL8139State),
3289 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3290 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3291
3292 VMSTATE_UINT32(RxBuf, RTL8139State),
3293 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3294 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3295 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3296
3297 VMSTATE_UINT16(IntrStatus, RTL8139State),
3298 VMSTATE_UINT16(IntrMask, RTL8139State),
3299
3300 VMSTATE_UINT32(TxConfig, RTL8139State),
3301 VMSTATE_UINT32(RxConfig, RTL8139State),
3302 VMSTATE_UINT32(RxMissed, RTL8139State),
3303 VMSTATE_UINT16(CSCR, RTL8139State),
3304
3305 VMSTATE_UINT8(Cfg9346, RTL8139State),
3306 VMSTATE_UINT8(Config0, RTL8139State),
3307 VMSTATE_UINT8(Config1, RTL8139State),
3308 VMSTATE_UINT8(Config3, RTL8139State),
3309 VMSTATE_UINT8(Config4, RTL8139State),
3310 VMSTATE_UINT8(Config5, RTL8139State),
3311
3312 VMSTATE_UINT8(clock_enabled, RTL8139State),
3313 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3314
3315 VMSTATE_UINT16(MultiIntr, RTL8139State),
3316
3317 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3318 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3319 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3320 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3321 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3322
3323 VMSTATE_UINT16(CpCmd, RTL8139State),
3324 VMSTATE_UINT8(TxThresh, RTL8139State),
3325
3326 VMSTATE_UNUSED(4),
3327 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
3328 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
3329
3330 VMSTATE_UINT32(currTxDesc, RTL8139State),
3331 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3332 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3333 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3334 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3335
3336 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3337 VMSTATE_INT32(eeprom.mode, RTL8139State),
3338 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3339 VMSTATE_UINT8(eeprom.address, RTL8139State),
3340 VMSTATE_UINT16(eeprom.input, RTL8139State),
3341 VMSTATE_UINT16(eeprom.output, RTL8139State),
3342
3343 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3344 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3345 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3346 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3347
3348 VMSTATE_UINT32(TCTR, RTL8139State),
3349 VMSTATE_UINT32(TimerInt, RTL8139State),
3350 VMSTATE_INT64(TCTR_base, RTL8139State),
3351
3352 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3353 vmstate_tally_counters, RTL8139TallyCounters),
3354
3355 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3356 VMSTATE_END_OF_LIST()
3357 },
3358 .subsections = (VMStateSubsection []) {
3359 {
3360 .vmsd = &vmstate_rtl8139_hotplug_ready,
3361 .needed = rtl8139_hotplug_ready_needed,
3362 }, {
3363 /* empty */
3364 }
3365 }
3366 };
3367
3368 /***********************************************************/
3369 /* PCI RTL8139 definitions */
3370
3371 static const MemoryRegionPortio rtl8139_portio[] = {
3372 { 0, 0x100, 1, .read = rtl8139_ioport_readb, },
3373 { 0, 0x100, 1, .write = rtl8139_ioport_writeb, },
3374 { 0, 0x100, 2, .read = rtl8139_ioport_readw, },
3375 { 0, 0x100, 2, .write = rtl8139_ioport_writew, },
3376 { 0, 0x100, 4, .read = rtl8139_ioport_readl, },
3377 { 0, 0x100, 4, .write = rtl8139_ioport_writel, },
3378 PORTIO_END_OF_LIST()
3379 };
3380
3381 static const MemoryRegionOps rtl8139_io_ops = {
3382 .old_portio = rtl8139_portio,
3383 .endianness = DEVICE_LITTLE_ENDIAN,
3384 };
3385
3386 static const MemoryRegionOps rtl8139_mmio_ops = {
3387 .old_mmio = {
3388 .read = {
3389 rtl8139_mmio_readb,
3390 rtl8139_mmio_readw,
3391 rtl8139_mmio_readl,
3392 },
3393 .write = {
3394 rtl8139_mmio_writeb,
3395 rtl8139_mmio_writew,
3396 rtl8139_mmio_writel,
3397 },
3398 },
3399 .endianness = DEVICE_LITTLE_ENDIAN,
3400 };
3401
3402 static void rtl8139_timer(void *opaque)
3403 {
3404 RTL8139State *s = opaque;
3405
3406 if (!s->clock_enabled)
3407 {
3408 DPRINTF(">>> timer: clock is not running\n");
3409 return;
3410 }
3411
3412 s->IntrStatus |= PCSTimeout;
3413 rtl8139_update_irq(s);
3414 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3415 }
3416
3417 static void rtl8139_cleanup(VLANClientState *nc)
3418 {
3419 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3420
3421 s->nic = NULL;
3422 }
3423
3424 static int pci_rtl8139_uninit(PCIDevice *dev)
3425 {
3426 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3427
3428 memory_region_destroy(&s->bar_io);
3429 memory_region_destroy(&s->bar_mem);
3430 if (s->cplus_txbuffer) {
3431 g_free(s->cplus_txbuffer);
3432 s->cplus_txbuffer = NULL;
3433 }
3434 qemu_del_timer(s->timer);
3435 qemu_free_timer(s->timer);
3436 qemu_del_vlan_client(&s->nic->nc);
3437 return 0;
3438 }
3439
3440 static NetClientInfo net_rtl8139_info = {
3441 .type = NET_CLIENT_TYPE_NIC,
3442 .size = sizeof(NICState),
3443 .can_receive = rtl8139_can_receive,
3444 .receive = rtl8139_receive,
3445 .cleanup = rtl8139_cleanup,
3446 };
3447
3448 static int pci_rtl8139_init(PCIDevice *dev)
3449 {
3450 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
3451 uint8_t *pci_conf;
3452
3453 pci_conf = s->dev.config;
3454 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
3455 /* TODO: start of capability list, but no capability
3456 * list bit in status register, and offset 0xdc seems unused. */
3457 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
3458
3459 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3460 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
3461 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3462 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
3463
3464 qemu_macaddr_default_if_unset(&s->conf.macaddr);
3465
3466 /* prepare eeprom */
3467 s->eeprom.contents[0] = 0x8129;
3468 #if 1
3469 /* PCI vendor and device ID should be mirrored here */
3470 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3471 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3472 #endif
3473 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3474 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3475 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3476
3477 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
3478 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
3479 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
3480
3481 s->cplus_txbuffer = NULL;
3482 s->cplus_txbuffer_len = 0;
3483 s->cplus_txbuffer_offset = 0;
3484
3485 s->TimerExpire = 0;
3486 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3487 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
3488
3489 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3490
3491 return 0;
3492 }
3493
3494 static Property rtl8139_properties[] = {
3495 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3496 DEFINE_PROP_END_OF_LIST(),
3497 };
3498
3499 static void rtl8139_class_init(ObjectClass *klass, void *data)
3500 {
3501 DeviceClass *dc = DEVICE_CLASS(klass);
3502 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3503
3504 k->init = pci_rtl8139_init;
3505 k->exit = pci_rtl8139_uninit;
3506 k->romfile = "pxe-rtl8139.rom";
3507 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3508 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3509 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3510 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
3511 dc->reset = rtl8139_reset;
3512 dc->vmsd = &vmstate_rtl8139;
3513 dc->props = rtl8139_properties;
3514 }
3515
3516 static TypeInfo rtl8139_info = {
3517 .name = "rtl8139",
3518 .parent = TYPE_PCI_DEVICE,
3519 .instance_size = sizeof(RTL8139State),
3520 .class_init = rtl8139_class_init,
3521 };
3522
3523 static void rtl8139_register_types(void)
3524 {
3525 type_register_static(&rtl8139_info);
3526 }
3527
3528 type_init(rtl8139_register_types)
Qemu copy for testing