hw/sched.c

   1 /*
   2  * QEMU interrupt controller & timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 #define PHYS_JJ_CLOCK   0x71D00000
  27 #define PHYS_JJ_CLOCK1  0x71D10000
  28 #define PHYS_JJ_INTR0   0x71E00000      /* CPU0 interrupt control registers */
  29 #define PHYS_JJ_INTR_G  0x71E10000      /* Master interrupt control registers */
  30
  31 /* These registers are used for sending/receiving irqs from/to
  32  * different cpu's.
  33  */
  34 struct sun4m_intreg_percpu {
  35         unsigned int tbt;        /* Intrs pending for this cpu, by PIL. */
  36         /* These next two registers are WRITE-ONLY and are only
  37          * "on bit" sensitive, "off bits" written have NO affect.
  38          */
  39         unsigned int clear;  /* Clear this cpus irqs here. */
  40         unsigned int set;    /* Set this cpus irqs here. */
  41 };
  42 /*
  43  * djhr
  44  * Actually the clear and set fields in this struct are misleading..
  45  * according to the SLAVIO manual (and the same applies for the SEC)
  46  * the clear field clears bits in the mask which will ENABLE that IRQ
  47  * the set field sets bits in the mask to DISABLE the IRQ.
  48  *
  49  * Also the undirected_xx address in the SLAVIO is defined as
  50  * RESERVED and write only..
  51  *
  52  * DAVEM_NOTE: The SLAVIO only specifies behavior on uniprocessor
  53  *             sun4m machines, for MP the layout makes more sense.
  54  */
  55 struct sun4m_intreg_master {
  56         unsigned int tbt;        /* IRQ's that are pending, see sun4m masks. */
  57         unsigned int irqs;       /* Master IRQ bits. */
  58
  59         /* Again, like the above, two these registers are WRITE-ONLY. */
  60         unsigned int clear;      /* Clear master IRQ's by setting bits here. */
  61         unsigned int set;        /* Set master IRQ's by setting bits here. */
  62
  63         /* This register is both READ and WRITE. */
  64         unsigned int undirected_target;  /* Which cpu gets undirected irqs. */
  65 };
  66 /*
  67  * Registers of hardware timer in sun4m.
  68  */
  69 struct sun4m_timer_percpu {
  70         volatile unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
  71         volatile unsigned int l14_cur_count;
  72 };
  73
  74 struct sun4m_timer_global {
  75         volatile unsigned int l10_timer_limit;
  76         volatile unsigned int l10_cur_count;
  77 };
  78
  79 #define SUN4M_INT_ENABLE        0x80000000
  80 #define SUN4M_INT_E14           0x00000080
  81 #define SUN4M_INT_E10           0x00080000
  82
  83 #define SUN4M_HARD_INT(x)       (0x000000001 << (x))
  84 #define SUN4M_SOFT_INT(x)       (0x000010000 << (x))
  85
  86 #define SUN4M_INT_MASKALL       0x80000000        /* mask all interrupts */
  87 #define SUN4M_INT_MODULE_ERR    0x40000000        /* module error */
  88 #define SUN4M_INT_M2S_WRITE     0x20000000        /* write buffer error */
  89 #define SUN4M_INT_ECC           0x10000000        /* ecc memory error */
  90 #define SUN4M_INT_FLOPPY        0x00400000        /* floppy disk */
  91 #define SUN4M_INT_MODULE        0x00200000        /* module interrupt */
  92 #define SUN4M_INT_VIDEO         0x00100000        /* onboard video */
  93 #define SUN4M_INT_REALTIME      0x00080000        /* system timer */
  94 #define SUN4M_INT_SCSI          0x00040000        /* onboard scsi */
  95 #define SUN4M_INT_AUDIO         0x00020000        /* audio/isdn */
  96 #define SUN4M_INT_ETHERNET      0x00010000        /* onboard ethernet */
  97 #define SUN4M_INT_SERIAL        0x00008000        /* serial ports */
  98 #define SUN4M_INT_SBUSBITS      0x00003F80        /* sbus int bits */
  99
 100 #define SUN4M_INT_SBUS(x)       (1 << (x+7))
 101 #define SUN4M_INT_VME(x)        (1 << (x))
 102
 103 typedef struct SCHEDState {
 104     uint32_t intreg_pending;
 105     uint32_t intreg_enabled;
 106     uint32_t intregm_pending;
 107     uint32_t intregm_enabled;
 108     uint32_t timer_regs[2];
 109     uint32_t timerm_regs[2];
 110 } SCHEDState;
 111
 112 static SCHEDState *ps;
 113
 114 static int intreg_io_memory, intregm_io_memory,
 115     timer_io_memory, timerm_io_memory;
 116
 117 static void sched_reset(SCHEDState *s)
 118 {
 119 }
 120
 121 static uint32_t intreg_mem_readl(void *opaque, target_phys_addr_t addr)
 122 {
 123     SCHEDState *s = opaque;
 124     uint32_t saddr;
 125
 126     saddr = (addr - PHYS_JJ_INTR0) >> 2;
 127     switch (saddr) {
 128     case 0:
 129         return s->intreg_pending;
 130         break;
 131     default:
 132         break;
 133     }
 134     return 0;
 135 }
 136
 137 static void intreg_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 138 {
 139     SCHEDState *s = opaque;
 140     uint32_t saddr;
 141
 142     saddr = (addr - PHYS_JJ_INTR0) >> 2;
 143     switch (saddr) {
 144     case 0:
 145         s->intreg_pending = val;
 146         break;
 147     case 1: // clear
 148         s->intreg_enabled &= ~val;
 149         break;
 150     case 2: // set
 151         s->intreg_enabled |= val;
 152         break;
 153     default:
 154         break;
 155     }
 156 }
 157
 158 static CPUReadMemoryFunc *intreg_mem_read[3] = {
 159     intreg_mem_readl,
 160     intreg_mem_readl,
 161     intreg_mem_readl,
 162 };
 163
 164 static CPUWriteMemoryFunc *intreg_mem_write[3] = {
 165     intreg_mem_writel,
 166     intreg_mem_writel,
 167     intreg_mem_writel,
 168 };
 169
 170 static uint32_t intregm_mem_readl(void *opaque, target_phys_addr_t addr)
 171 {
 172     SCHEDState *s = opaque;
 173     uint32_t saddr;
 174
 175     saddr = (addr - PHYS_JJ_INTR_G) >> 2;
 176     switch (saddr) {
 177     case 0:
 178         return s->intregm_pending;
 179         break;
 180     case 1:
 181         return s->intregm_enabled;
 182         break;
 183     default:
 184         break;
 185     }
 186     return 0;
 187 }
 188
 189 static void intregm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 190 {
 191     SCHEDState *s = opaque;
 192     uint32_t saddr;
 193
 194     saddr = (addr - PHYS_JJ_INTR_G) >> 2;
 195     switch (saddr) {
 196     case 0:
 197         s->intregm_pending = val;
 198         break;
 199     case 1:
 200         s->intregm_enabled = val;
 201         break;
 202     case 2: // clear
 203         s->intregm_enabled &= ~val;
 204         break;
 205     case 3: // set
 206         s->intregm_enabled |= val;
 207         break;
 208     default:
 209         break;
 210     }
 211 }
 212
 213 static CPUReadMemoryFunc *intregm_mem_read[3] = {
 214     intregm_mem_readl,
 215     intregm_mem_readl,
 216     intregm_mem_readl,
 217 };
 218
 219 static CPUWriteMemoryFunc *intregm_mem_write[3] = {
 220     intregm_mem_writel,
 221     intregm_mem_writel,
 222     intregm_mem_writel,
 223 };
 224
 225 static uint32_t timer_mem_readl(void *opaque, target_phys_addr_t addr)
 226 {
 227     SCHEDState *s = opaque;
 228     uint32_t saddr;
 229
 230     saddr = (addr - PHYS_JJ_CLOCK) >> 2;
 231     switch (saddr) {
 232     default:
 233         return s->timer_regs[saddr];
 234         break;
 235     }
 236     return 0;
 237 }
 238
 239 static void timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 240 {
 241     SCHEDState *s = opaque;
 242     uint32_t saddr;
 243
 244     saddr = (addr - PHYS_JJ_CLOCK) >> 2;
 245     switch (saddr) {
 246     default:
 247         s->timer_regs[saddr] = val;
 248         break;
 249     }
 250 }
 251
 252 static CPUReadMemoryFunc *timer_mem_read[3] = {
 253     timer_mem_readl,
 254     timer_mem_readl,
 255     timer_mem_readl,
 256 };
 257
 258 static CPUWriteMemoryFunc *timer_mem_write[3] = {
 259     timer_mem_writel,
 260     timer_mem_writel,
 261     timer_mem_writel,
 262 };
 263
 264 static uint32_t timerm_mem_readl(void *opaque, target_phys_addr_t addr)
 265 {
 266     SCHEDState *s = opaque;
 267     uint32_t saddr;
 268
 269     saddr = (addr - PHYS_JJ_CLOCK1) >> 2;
 270     switch (saddr) {
 271     default:
 272         return s->timerm_regs[saddr];
 273         break;
 274     }
 275     return 0;
 276 }
 277
 278 static void timerm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 279 {
 280     SCHEDState *s = opaque;
 281     uint32_t saddr;
 282
 283     saddr = (addr - PHYS_JJ_CLOCK1) >> 2;
 284     switch (saddr) {
 285     default:
 286         s->timerm_regs[saddr] = val;
 287         break;
 288     }
 289 }
 290
 291 static CPUReadMemoryFunc *timerm_mem_read[3] = {
 292     timerm_mem_readl,
 293     timerm_mem_readl,
 294     timerm_mem_readl,
 295 };
 296
 297 static CPUWriteMemoryFunc *timerm_mem_write[3] = {
 298     timerm_mem_writel,
 299     timerm_mem_writel,
 300     timerm_mem_writel,
 301 };
 302
 303 void pic_info() {}
 304 void irq_info() {}
 305
 306 static const unsigned int intr_to_mask[16] = {
 307         0,      0,      0,      0,      0,      0, SUN4M_INT_ETHERNET,  0,
 308         0,      0,      0,      0,      0,      0,      0,      0,
 309 };
 310
 311 void pic_set_irq(int irq, int level)
 312 {
 313     if (irq < 16) {
 314         unsigned int mask = intr_to_mask[irq];
 315         ps->intreg_pending |= 1 << irq;
 316         if (ps->intregm_enabled & mask) {
 317             cpu_single_env->interrupt_index = irq;
 318             cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD);
 319         }
 320     }
 321 }
 322
 323 void sched_init()
 324 {
 325     SCHEDState *s;
 326
 327     s = qemu_mallocz(sizeof(SCHEDState));
 328     if (!s)
 329         return;
 330
 331     intreg_io_memory = cpu_register_io_memory(0, intreg_mem_read, intreg_mem_write, s);
 332     cpu_register_physical_memory(PHYS_JJ_INTR0, 3, intreg_io_memory);
 333
 334     intregm_io_memory = cpu_register_io_memory(0, intregm_mem_read, intregm_mem_write, s);
 335     cpu_register_physical_memory(PHYS_JJ_INTR_G, 5, intregm_io_memory);
 336
 337     timer_io_memory = cpu_register_io_memory(0, timer_mem_read, timer_mem_write, s);
 338     cpu_register_physical_memory(PHYS_JJ_CLOCK, 2, timer_io_memory);
 339
 340     timerm_io_memory = cpu_register_io_memory(0, timerm_mem_read, timerm_mem_write, s);
 341     cpu_register_physical_memory(PHYS_JJ_CLOCK1, 2, timerm_io_memory);
 342
 343     sched_reset(s);
 344     ps = s;
 345 }
 346