hw/sd/milkymist-memcard.c

   1 /*
   2  *  QEMU model of the Milkymist SD Card Controller.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.milkymist.org/socdoc/memcard.pdf
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "trace.h"
  28 #include "qemu/error-report.h"
  29 #include "sysemu/blockdev.h"
  30 #include "hw/sd.h"
  31
  32 enum {
  33     ENABLE_CMD_TX   = (1<<0),
  34     ENABLE_CMD_RX   = (1<<1),
  35     ENABLE_DAT_TX   = (1<<2),
  36     ENABLE_DAT_RX   = (1<<3),
  37 };
  38
  39 enum {
  40     PENDING_CMD_TX   = (1<<0),
  41     PENDING_CMD_RX   = (1<<1),
  42     PENDING_DAT_TX   = (1<<2),
  43     PENDING_DAT_RX   = (1<<3),
  44 };
  45
  46 enum {
  47     START_CMD_TX    = (1<<0),
  48     START_DAT_RX    = (1<<1),
  49 };
  50
  51 enum {
  52     R_CLK2XDIV = 0,
  53     R_ENABLE,
  54     R_PENDING,
  55     R_START,
  56     R_CMD,
  57     R_DAT,
  58     R_MAX
  59 };
  60
  61 #define TYPE_MILKYMIST_MEMCARD "milkymist-memcard"
  62 #define MILKYMIST_MEMCARD(obj) \
  63     OBJECT_CHECK(MilkymistMemcardState, (obj), TYPE_MILKYMIST_MEMCARD)
  64
  65 struct MilkymistMemcardState {
  66     SysBusDevice parent_obj;
  67
  68     MemoryRegion regs_region;
  69     SDState *card;
  70
  71     int command_write_ptr;
  72     int response_read_ptr;
  73     int response_len;
  74     int ignore_next_cmd;
  75     int enabled;
  76     uint8_t command[6];
  77     uint8_t response[17];
  78     uint32_t regs[R_MAX];
  79 };
  80 typedef struct MilkymistMemcardState MilkymistMemcardState;
  81
  82 static void update_pending_bits(MilkymistMemcardState *s)
  83 {
  84     /* transmits are instantaneous, thus tx pending bits are never set */
  85     s->regs[R_PENDING] = 0;
  86     /* if rx is enabled the corresponding pending bits are always set */
  87     if (s->regs[R_ENABLE] & ENABLE_CMD_RX) {
  88         s->regs[R_PENDING] |= PENDING_CMD_RX;
  89     }
  90     if (s->regs[R_ENABLE] & ENABLE_DAT_RX) {
  91         s->regs[R_PENDING] |= PENDING_DAT_RX;
  92     }
  93 }
  94
  95 static void memcard_sd_command(MilkymistMemcardState *s)
  96 {
  97     SDRequest req;
  98
  99     req.cmd = s->command[0] & 0x3f;
 100     req.arg = (s->command[1] << 24) | (s->command[2] << 16)
 101               | (s->command[3] << 8) | s->command[4];
 102     req.crc = s->command[5];
 103
 104     s->response[0] = req.cmd;
 105     s->response_len = sd_do_command(s->card, &req, s->response+1);
 106     s->response_read_ptr = 0;
 107
 108     if (s->response_len == 16) {
 109         /* R2 response */
 110         s->response[0] = 0x3f;
 111         s->response_len += 1;
 112     } else if (s->response_len == 4) {
 113         /* no crc calculation, insert dummy byte */
 114         s->response[5] = 0;
 115         s->response_len += 2;
 116     }
 117
 118     if (req.cmd == 0) {
 119         /* next write is a dummy byte to clock the initialization of the sd
 120          * card */
 121         s->ignore_next_cmd = 1;
 122     }
 123 }
 124
 125 static uint64_t memcard_read(void *opaque, hwaddr addr,
 126                              unsigned size)
 127 {
 128     MilkymistMemcardState *s = opaque;
 129     uint32_t r = 0;
 130
 131     addr >>= 2;
 132     switch (addr) {
 133     case R_CMD:
 134         if (!s->enabled) {
 135             r = 0xff;
 136         } else {
 137             r = s->response[s->response_read_ptr++];
 138             if (s->response_read_ptr > s->response_len) {
 139                 error_report("milkymist_memcard: "
 140                         "read more cmd bytes than available. Clipping.");
 141                 s->response_read_ptr = 0;
 142             }
 143         }
 144         break;
 145     case R_DAT:
 146         if (!s->enabled) {
 147             r = 0xffffffff;
 148         } else {
 149             r = 0;
 150             r |= sd_read_data(s->card) << 24;
 151             r |= sd_read_data(s->card) << 16;
 152             r |= sd_read_data(s->card) << 8;
 153             r |= sd_read_data(s->card);
 154         }
 155         break;
 156     case R_CLK2XDIV:
 157     case R_ENABLE:
 158     case R_PENDING:
 159     case R_START:
 160         r = s->regs[addr];
 161         break;
 162
 163     default:
 164         error_report("milkymist_memcard: read access to unknown register 0x"
 165                 TARGET_FMT_plx, addr << 2);
 166         break;
 167     }
 168
 169     trace_milkymist_memcard_memory_read(addr << 2, r);
 170
 171     return r;
 172 }
 173
 174 static void memcard_write(void *opaque, hwaddr addr, uint64_t value,
 175                           unsigned size)
 176 {
 177     MilkymistMemcardState *s = opaque;
 178
 179     trace_milkymist_memcard_memory_write(addr, value);
 180
 181     addr >>= 2;
 182     switch (addr) {
 183     case R_PENDING:
 184         /* clear rx pending bits */
 185         s->regs[R_PENDING] &= ~(value & (PENDING_CMD_RX | PENDING_DAT_RX));
 186         update_pending_bits(s);
 187         break;
 188     case R_CMD:
 189         if (!s->enabled) {
 190             break;
 191         }
 192         if (s->ignore_next_cmd) {
 193             s->ignore_next_cmd = 0;
 194             break;
 195         }
 196         s->command[s->command_write_ptr] = value & 0xff;
 197         s->command_write_ptr = (s->command_write_ptr + 1) % 6;
 198         if (s->command_write_ptr == 0) {
 199             memcard_sd_command(s);
 200         }
 201         break;
 202     case R_DAT:
 203         if (!s->enabled) {
 204             break;
 205         }
 206         sd_write_data(s->card, (value >> 24) & 0xff);
 207         sd_write_data(s->card, (value >> 16) & 0xff);
 208         sd_write_data(s->card, (value >> 8) & 0xff);
 209         sd_write_data(s->card, value & 0xff);
 210         break;
 211     case R_ENABLE:
 212         s->regs[addr] = value;
 213         update_pending_bits(s);
 214         break;
 215     case R_CLK2XDIV:
 216     case R_START:
 217         s->regs[addr] = value;
 218         break;
 219
 220     default:
 221         error_report("milkymist_memcard: write access to unknown register 0x"
 222                 TARGET_FMT_plx, addr << 2);
 223         break;
 224     }
 225 }
 226
 227 static const MemoryRegionOps memcard_mmio_ops = {
 228     .read = memcard_read,
 229     .write = memcard_write,
 230     .valid = {
 231         .min_access_size = 4,
 232         .max_access_size = 4,
 233     },
 234     .endianness = DEVICE_NATIVE_ENDIAN,
 235 };
 236
 237 static void milkymist_memcard_reset(DeviceState *d)
 238 {
 239     MilkymistMemcardState *s = MILKYMIST_MEMCARD(d);
 240     int i;
 241
 242     s->command_write_ptr = 0;
 243     s->response_read_ptr = 0;
 244     s->response_len = 0;
 245
 246     for (i = 0; i < R_MAX; i++) {
 247         s->regs[i] = 0;
 248     }
 249 }
 250
 251 static int milkymist_memcard_init(SysBusDevice *dev)
 252 {
 253     MilkymistMemcardState *s = MILKYMIST_MEMCARD(dev);
 254     DriveInfo *dinfo;
 255
 256     dinfo = drive_get_next(IF_SD);
 257     s->card = sd_init(dinfo ? dinfo->bdrv : NULL, false);
 258     if (s->card == NULL) {
 259         return -1;
 260     }
 261
 262     s->enabled = dinfo ? bdrv_is_inserted(dinfo->bdrv) : 0;
 263
 264     memory_region_init_io(&s->regs_region, OBJECT(s), &memcard_mmio_ops, s,
 265             "milkymist-memcard", R_MAX * 4);
 266     sysbus_init_mmio(dev, &s->regs_region);
 267
 268     return 0;
 269 }
 270
 271 static const VMStateDescription vmstate_milkymist_memcard = {
 272     .name = "milkymist-memcard",
 273     .version_id = 1,
 274     .minimum_version_id = 1,
 275     .minimum_version_id_old = 1,
 276     .fields      = (VMStateField[]) {
 277         VMSTATE_INT32(command_write_ptr, MilkymistMemcardState),
 278         VMSTATE_INT32(response_read_ptr, MilkymistMemcardState),
 279         VMSTATE_INT32(response_len, MilkymistMemcardState),
 280         VMSTATE_INT32(ignore_next_cmd, MilkymistMemcardState),
 281         VMSTATE_INT32(enabled, MilkymistMemcardState),
 282         VMSTATE_UINT8_ARRAY(command, MilkymistMemcardState, 6),
 283         VMSTATE_UINT8_ARRAY(response, MilkymistMemcardState, 17),
 284         VMSTATE_UINT32_ARRAY(regs, MilkymistMemcardState, R_MAX),
 285         VMSTATE_END_OF_LIST()
 286     }
 287 };
 288
 289 static void milkymist_memcard_class_init(ObjectClass *klass, void *data)
 290 {
 291     DeviceClass *dc = DEVICE_CLASS(klass);
 292     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 293
 294     k->init = milkymist_memcard_init;
 295     dc->reset = milkymist_memcard_reset;
 296     dc->vmsd = &vmstate_milkymist_memcard;
 297 }
 298
 299 static const TypeInfo milkymist_memcard_info = {
 300     .name          = TYPE_MILKYMIST_MEMCARD,
 301     .parent        = TYPE_SYS_BUS_DEVICE,
 302     .instance_size = sizeof(MilkymistMemcardState),
 303     .class_init    = milkymist_memcard_class_init,
 304 };
 305
 306 static void milkymist_memcard_register_types(void)
 307 {
 308     type_register_static(&milkymist_memcard_info);
 309 }
 310
 311 type_init(milkymist_memcard_register_types)