hw/serial.c

   1 /*
   2  * QEMU 16450 UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_SERIAL
  27
  28 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  29
  30 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  31 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  32 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  33 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  34
  35 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  36 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  37
  38 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  39 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  40 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  41 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  42
  43 /*
  44  * These are the definitions for the Modem Control Register
  45  */
  46 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  47 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  48 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  49 #define UART_MCR_RTS    0x02    /* RTS complement */
  50 #define UART_MCR_DTR    0x01    /* DTR complement */
  51
  52 /*
  53  * These are the definitions for the Modem Status Register
  54  */
  55 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  56 #define UART_MSR_RI     0x40    /* Ring Indicator */
  57 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  58 #define UART_MSR_CTS    0x10    /* Clear to Send */
  59 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  60 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  61 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  62 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  63 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  64
  65 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  66 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  67 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  68 #define UART_LSR_FE     0x08    /* Frame error indicator */
  69 #define UART_LSR_PE     0x04    /* Parity error indicator */
  70 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  71 #define UART_LSR_DR     0x01    /* Receiver data ready */
  72
  73 struct SerialState {
  74     uint8_t divider;
  75     uint8_t rbr; /* receive register */
  76     uint8_t ier;
  77     uint8_t iir; /* read only */
  78     uint8_t lcr;
  79     uint8_t mcr;
  80     uint8_t lsr; /* read only */
  81     uint8_t msr;
  82     uint8_t scr;
  83     /* NOTE: this hidden state is necessary for tx irq generation as
  84        it can be reset while reading iir */
  85     int thr_ipending;
  86     int irq;
  87     CharDriverState *chr;
  88     int last_break_enable;
  89 };
  90
  91 static void serial_update_irq(SerialState *s)
  92 {
  93     if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
  94         s->iir = UART_IIR_RDI;
  95     } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
  96         s->iir = UART_IIR_THRI;
  97     } else {
  98         s->iir = UART_IIR_NO_INT;
  99     }
 100     if (s->iir != UART_IIR_NO_INT) {
 101         pic_set_irq(s->irq, 1);
 102     } else {
 103         pic_set_irq(s->irq, 0);
 104     }
 105 }
 106
 107 static void serial_update_parameters(SerialState *s)
 108 {
 109     int speed, parity, data_bits, stop_bits;
 110     QEMUSerialSetParams ssp;
 111
 112     if (s->lcr & 0x08) {
 113         if (s->lcr & 0x10)
 114             parity = 'E';
 115         else
 116             parity = 'O';
 117     } else {
 118             parity = 'N';
 119     }
 120     if (s->lcr & 0x04)
 121         stop_bits = 2;
 122     else
 123         stop_bits = 1;
 124     data_bits = (s->lcr & 0x03) + 5;
 125     if (s->divider == 0)
 126         return;
 127     speed = 115200 / s->divider;
 128     ssp.speed = speed;
 129     ssp.parity = parity;
 130     ssp.data_bits = data_bits;
 131     ssp.stop_bits = stop_bits;
 132     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 133 #if 0
 134     printf("speed=%d parity=%c data=%d stop=%d\n",
 135            speed, parity, data_bits, stop_bits);
 136 #endif
 137 }
 138
 139 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 140 {
 141     SerialState *s = opaque;
 142     unsigned char ch;
 143
 144     addr &= 7;
 145 #ifdef DEBUG_SERIAL
 146     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 147 #endif
 148     switch(addr) {
 149     default:
 150     case 0:
 151         if (s->lcr & UART_LCR_DLAB) {
 152             s->divider = (s->divider & 0xff00) | val;
 153             serial_update_parameters(s);
 154         } else {
 155             s->thr_ipending = 0;
 156             s->lsr &= ~UART_LSR_THRE;
 157             serial_update_irq(s);
 158             ch = val;
 159             qemu_chr_write(s->chr, &ch, 1);
 160             s->thr_ipending = 1;
 161             s->lsr |= UART_LSR_THRE;
 162             s->lsr |= UART_LSR_TEMT;
 163             serial_update_irq(s);
 164         }
 165         break;
 166     case 1:
 167         if (s->lcr & UART_LCR_DLAB) {
 168             s->divider = (s->divider & 0x00ff) | (val << 8);
 169             serial_update_parameters(s);
 170         } else {
 171             s->ier = val & 0x0f;
 172             if (s->lsr & UART_LSR_THRE) {
 173                 s->thr_ipending = 1;
 174             }
 175             serial_update_irq(s);
 176         }
 177         break;
 178     case 2:
 179         break;
 180     case 3:
 181         {
 182             int break_enable;
 183             s->lcr = val;
 184             serial_update_parameters(s);
 185             break_enable = (val >> 6) & 1;
 186             if (break_enable != s->last_break_enable) {
 187                 s->last_break_enable = break_enable;
 188                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 189                                &break_enable);
 190             }
 191         }
 192         break;
 193     case 4:
 194         s->mcr = val & 0x1f;
 195         break;
 196     case 5:
 197         break;
 198     case 6:
 199         s->msr = val;
 200         break;
 201     case 7:
 202         s->scr = val;
 203         break;
 204     }
 205 }
 206
 207 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 208 {
 209     SerialState *s = opaque;
 210     uint32_t ret;
 211
 212     addr &= 7;
 213     switch(addr) {
 214     default:
 215     case 0:
 216         if (s->lcr & UART_LCR_DLAB) {
 217             ret = s->divider & 0xff;
 218         } else {
 219             ret = s->rbr;
 220             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 221             serial_update_irq(s);
 222         }
 223         break;
 224     case 1:
 225         if (s->lcr & UART_LCR_DLAB) {
 226             ret = (s->divider >> 8) & 0xff;
 227         } else {
 228             ret = s->ier;
 229         }
 230         break;
 231     case 2:
 232         ret = s->iir;
 233         /* reset THR pending bit */
 234         if ((ret & 0x7) == UART_IIR_THRI)
 235             s->thr_ipending = 0;
 236         serial_update_irq(s);
 237         break;
 238     case 3:
 239         ret = s->lcr;
 240         break;
 241     case 4:
 242         ret = s->mcr;
 243         break;
 244     case 5:
 245         ret = s->lsr;
 246         break;
 247     case 6:
 248         if (s->mcr & UART_MCR_LOOP) {
 249             /* in loopback, the modem output pins are connected to the
 250                inputs */
 251             ret = (s->mcr & 0x0c) << 4;
 252             ret |= (s->mcr & 0x02) << 3;
 253             ret |= (s->mcr & 0x01) << 5;
 254         } else {
 255             ret = s->msr;
 256         }
 257         break;
 258     case 7:
 259         ret = s->scr;
 260         break;
 261     }
 262 #ifdef DEBUG_SERIAL
 263     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 264 #endif
 265     return ret;
 266 }
 267
 268 static int serial_can_receive(SerialState *s)
 269 {
 270     return !(s->lsr & UART_LSR_DR);
 271 }
 272
 273 static void serial_receive_byte(SerialState *s, int ch)
 274 {
 275     s->rbr = ch;
 276     s->lsr |= UART_LSR_DR;
 277     serial_update_irq(s);
 278 }
 279
 280 static void serial_receive_break(SerialState *s)
 281 {
 282     s->rbr = 0;
 283     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 284     serial_update_irq(s);
 285 }
 286
 287 static int serial_can_receive1(void *opaque)
 288 {
 289     SerialState *s = opaque;
 290     return serial_can_receive(s);
 291 }
 292
 293 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 294 {
 295     SerialState *s = opaque;
 296     serial_receive_byte(s, buf[0]);
 297 }
 298
 299 static void serial_event(void *opaque, int event)
 300 {
 301     SerialState *s = opaque;
 302     if (event == CHR_EVENT_BREAK)
 303         serial_receive_break(s);
 304 }
 305
 306 static void serial_save(QEMUFile *f, void *opaque)
 307 {
 308     SerialState *s = opaque;
 309
 310     qemu_put_8s(f,&s->divider);
 311     qemu_put_8s(f,&s->rbr);
 312     qemu_put_8s(f,&s->ier);
 313     qemu_put_8s(f,&s->iir);
 314     qemu_put_8s(f,&s->lcr);
 315     qemu_put_8s(f,&s->mcr);
 316     qemu_put_8s(f,&s->lsr);
 317     qemu_put_8s(f,&s->msr);
 318     qemu_put_8s(f,&s->scr);
 319 }
 320
 321 static int serial_load(QEMUFile *f, void *opaque, int version_id)
 322 {
 323     SerialState *s = opaque;
 324
 325     if(version_id != 1)
 326         return -EINVAL;
 327
 328     qemu_get_8s(f,&s->divider);
 329     qemu_get_8s(f,&s->rbr);
 330     qemu_get_8s(f,&s->ier);
 331     qemu_get_8s(f,&s->iir);
 332     qemu_get_8s(f,&s->lcr);
 333     qemu_get_8s(f,&s->mcr);
 334     qemu_get_8s(f,&s->lsr);
 335     qemu_get_8s(f,&s->msr);
 336     qemu_get_8s(f,&s->scr);
 337
 338     return 0;
 339 }
 340
 341 /* If fd is zero, it means that the serial device uses the console */
 342 SerialState *serial_init(int base, int irq, CharDriverState *chr)
 343 {
 344     SerialState *s;
 345
 346     s = qemu_mallocz(sizeof(SerialState));
 347     if (!s)
 348         return NULL;
 349     s->irq = irq;
 350     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 351     s->iir = UART_IIR_NO_INT;
 352
 353     register_savevm("serial", base, 1, serial_save, serial_load, s);
 354
 355     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 356     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 357     s->chr = chr;
 358     qemu_chr_add_read_handler(chr, serial_can_receive1, serial_receive1, s);
 359     qemu_chr_add_event_handler(chr, serial_event);
 360     return s;
 361 }