hw/serial.c

   1 /*
   2  * QEMU 16450 UART emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "qemu-char.h"
  26 #include "isa.h"
  27 #include "pc.h"
  28 #include "qemu-timer.h"
  29
  30 //#define DEBUG_SERIAL
  31
  32 #define UART_LCR_DLAB   0x80    /* Divisor latch access bit */
  33
  34 #define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
  35 #define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
  36 #define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
  37 #define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
  38
  39 #define UART_IIR_NO_INT 0x01    /* No interrupts pending */
  40 #define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
  41
  42 #define UART_IIR_MSI    0x00    /* Modem status interrupt */
  43 #define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
  44 #define UART_IIR_RDI    0x04    /* Receiver data interrupt */
  45 #define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
  46
  47 /*
  48  * These are the definitions for the Modem Control Register
  49  */
  50 #define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
  51 #define UART_MCR_OUT2   0x08    /* Out2 complement */
  52 #define UART_MCR_OUT1   0x04    /* Out1 complement */
  53 #define UART_MCR_RTS    0x02    /* RTS complement */
  54 #define UART_MCR_DTR    0x01    /* DTR complement */
  55
  56 /*
  57  * These are the definitions for the Modem Status Register
  58  */
  59 #define UART_MSR_DCD    0x80    /* Data Carrier Detect */
  60 #define UART_MSR_RI     0x40    /* Ring Indicator */
  61 #define UART_MSR_DSR    0x20    /* Data Set Ready */
  62 #define UART_MSR_CTS    0x10    /* Clear to Send */
  63 #define UART_MSR_DDCD   0x08    /* Delta DCD */
  64 #define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
  65 #define UART_MSR_DDSR   0x02    /* Delta DSR */
  66 #define UART_MSR_DCTS   0x01    /* Delta CTS */
  67 #define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
  68
  69 #define UART_LSR_TEMT   0x40    /* Transmitter empty */
  70 #define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
  71 #define UART_LSR_BI     0x10    /* Break interrupt indicator */
  72 #define UART_LSR_FE     0x08    /* Frame error indicator */
  73 #define UART_LSR_PE     0x04    /* Parity error indicator */
  74 #define UART_LSR_OE     0x02    /* Overrun error indicator */
  75 #define UART_LSR_DR     0x01    /* Receiver data ready */
  76
  77 /*
  78  * Delay TX IRQ after sending as much characters as the given interval would
  79  * contain on real hardware. This avoids overloading the guest if it processes
  80  * its output buffer in a loop inside the TX IRQ handler.
  81  */
  82 #define THROTTLE_TX_INTERVAL    10 /* ms */
  83
  84 struct SerialState {
  85     uint16_t divider;
  86     uint8_t rbr; /* receive register */
  87     uint8_t ier;
  88     uint8_t iir; /* read only */
  89     uint8_t lcr;
  90     uint8_t mcr;
  91     uint8_t lsr; /* read only */
  92     uint8_t msr; /* read only */
  93     uint8_t scr;
  94     /* NOTE: this hidden state is necessary for tx irq generation as
  95        it can be reset while reading iir */
  96     int thr_ipending;
  97     qemu_irq irq;
  98     CharDriverState *chr;
  99     int last_break_enable;
 100     target_phys_addr_t base;
 101     int it_shift;
 102     QEMUTimer *tx_timer;
 103     int tx_burst;
 104 };
 105
 106 static void serial_receive_byte(SerialState *s, int ch);
 107
 108 static void serial_update_irq(SerialState *s)
 109 {
 110     if ((s->lsr & UART_LSR_DR) && (s->ier & UART_IER_RDI)) {
 111         s->iir = UART_IIR_RDI;
 112     } else if (s->thr_ipending && (s->ier & UART_IER_THRI)) {
 113         s->iir = UART_IIR_THRI;
 114     } else {
 115         s->iir = UART_IIR_NO_INT;
 116     }
 117     if (s->iir != UART_IIR_NO_INT) {
 118         qemu_irq_raise(s->irq);
 119     } else {
 120         qemu_irq_lower(s->irq);
 121     }
 122 }
 123
 124 static void serial_tx_done(void *opaque)
 125 {
 126     SerialState *s = opaque;
 127
 128     if (s->tx_burst < 0) {
 129         uint16_t divider;
 130
 131         if (s->divider)
 132           divider = s->divider;
 133         else
 134           divider = 1;
 135
 136         /* We assume 10 bits/char, OK for this purpose. */
 137         s->tx_burst = THROTTLE_TX_INTERVAL * 1000 /
 138             (1000000 * 10 / (115200 / divider));
 139     }
 140     s->thr_ipending = 1;
 141     s->lsr |= UART_LSR_THRE;
 142     s->lsr |= UART_LSR_TEMT;
 143     serial_update_irq(s);
 144 }
 145
 146 static void serial_update_parameters(SerialState *s)
 147 {
 148     int speed, parity, data_bits, stop_bits;
 149     QEMUSerialSetParams ssp;
 150
 151     if (s->lcr & 0x08) {
 152         if (s->lcr & 0x10)
 153             parity = 'E';
 154         else
 155             parity = 'O';
 156     } else {
 157             parity = 'N';
 158     }
 159     if (s->lcr & 0x04)
 160         stop_bits = 2;
 161     else
 162         stop_bits = 1;
 163     data_bits = (s->lcr & 0x03) + 5;
 164     if (s->divider == 0)
 165         return;
 166     speed = 115200 / s->divider;
 167     ssp.speed = speed;
 168     ssp.parity = parity;
 169     ssp.data_bits = data_bits;
 170     ssp.stop_bits = stop_bits;
 171     qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
 172 #if 0
 173     printf("speed=%d parity=%c data=%d stop=%d\n",
 174            speed, parity, data_bits, stop_bits);
 175 #endif
 176 }
 177
 178 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 179 {
 180     SerialState *s = opaque;
 181     unsigned char ch;
 182
 183     addr &= 7;
 184 #ifdef DEBUG_SERIAL
 185     printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
 186 #endif
 187     switch(addr) {
 188     default:
 189     case 0:
 190         if (s->lcr & UART_LCR_DLAB) {
 191             s->divider = (s->divider & 0xff00) | val;
 192             serial_update_parameters(s);
 193         } else {
 194             s->thr_ipending = 0;
 195             s->lsr &= ~UART_LSR_THRE;
 196             serial_update_irq(s);
 197             ch = val;
 198             if (!(s->mcr & UART_MCR_LOOP)) {
 199                 /* when not in loopback mode, send the char */
 200                 qemu_chr_write(s->chr, &ch, 1);
 201             } else {
 202                 /* in loopback mode, say that we just received a char */
 203                 serial_receive_byte(s, ch);
 204             }
 205             if (s->tx_burst > 0) {
 206                 s->tx_burst--;
 207                 serial_tx_done(s);
 208             } else if (s->tx_burst == 0) {
 209                 s->tx_burst--;
 210                 qemu_mod_timer(s->tx_timer, qemu_get_clock(vm_clock) +
 211                                ticks_per_sec * THROTTLE_TX_INTERVAL / 1000);
 212             }
 213         }
 214         break;
 215     case 1:
 216         if (s->lcr & UART_LCR_DLAB) {
 217             s->divider = (s->divider & 0x00ff) | (val << 8);
 218             serial_update_parameters(s);
 219         } else {
 220             s->ier = val & 0x0f;
 221             if (s->lsr & UART_LSR_THRE) {
 222                 s->thr_ipending = 1;
 223             }
 224             serial_update_irq(s);
 225         }
 226         break;
 227     case 2:
 228         break;
 229     case 3:
 230         {
 231             int break_enable;
 232             s->lcr = val;
 233             serial_update_parameters(s);
 234             break_enable = (val >> 6) & 1;
 235             if (break_enable != s->last_break_enable) {
 236                 s->last_break_enable = break_enable;
 237                 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
 238                                &break_enable);
 239             }
 240         }
 241         break;
 242     case 4:
 243         s->mcr = val & 0x1f;
 244         break;
 245     case 5:
 246         break;
 247     case 6:
 248         break;
 249     case 7:
 250         s->scr = val;
 251         break;
 252     }
 253 }
 254
 255 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
 256 {
 257     SerialState *s = opaque;
 258     uint32_t ret;
 259
 260     addr &= 7;
 261     switch(addr) {
 262     default:
 263     case 0:
 264         if (s->lcr & UART_LCR_DLAB) {
 265             ret = s->divider & 0xff;
 266         } else {
 267             ret = s->rbr;
 268             s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
 269             serial_update_irq(s);
 270             if (!(s->mcr & UART_MCR_LOOP)) {
 271                 /* in loopback mode, don't receive any data */
 272                 qemu_chr_accept_input(s->chr);
 273             }
 274         }
 275         break;
 276     case 1:
 277         if (s->lcr & UART_LCR_DLAB) {
 278             ret = (s->divider >> 8) & 0xff;
 279         } else {
 280             ret = s->ier;
 281         }
 282         break;
 283     case 2:
 284         ret = s->iir;
 285         /* reset THR pending bit */
 286         if ((ret & 0x7) == UART_IIR_THRI)
 287             s->thr_ipending = 0;
 288         serial_update_irq(s);
 289         break;
 290     case 3:
 291         ret = s->lcr;
 292         break;
 293     case 4:
 294         ret = s->mcr;
 295         break;
 296     case 5:
 297         ret = s->lsr;
 298         break;
 299     case 6:
 300         if (s->mcr & UART_MCR_LOOP) {
 301             /* in loopback, the modem output pins are connected to the
 302                inputs */
 303             ret = (s->mcr & 0x0c) << 4;
 304             ret |= (s->mcr & 0x02) << 3;
 305             ret |= (s->mcr & 0x01) << 5;
 306         } else {
 307             ret = s->msr;
 308         }
 309         break;
 310     case 7:
 311         ret = s->scr;
 312         break;
 313     }
 314 #ifdef DEBUG_SERIAL
 315     printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
 316 #endif
 317     return ret;
 318 }
 319
 320 static int serial_can_receive(SerialState *s)
 321 {
 322     return !(s->lsr & UART_LSR_DR);
 323 }
 324
 325 static void serial_receive_byte(SerialState *s, int ch)
 326 {
 327     s->rbr = ch;
 328     s->lsr |= UART_LSR_DR;
 329     serial_update_irq(s);
 330 }
 331
 332 static void serial_receive_break(SerialState *s)
 333 {
 334     s->rbr = 0;
 335     s->lsr |= UART_LSR_BI | UART_LSR_DR;
 336     serial_update_irq(s);
 337 }
 338
 339 static int serial_can_receive1(void *opaque)
 340 {
 341     SerialState *s = opaque;
 342     return serial_can_receive(s);
 343 }
 344
 345 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
 346 {
 347     SerialState *s = opaque;
 348     serial_receive_byte(s, buf[0]);
 349 }
 350
 351 static void serial_event(void *opaque, int event)
 352 {
 353     SerialState *s = opaque;
 354     if (event == CHR_EVENT_BREAK)
 355         serial_receive_break(s);
 356 }
 357
 358 static void serial_save(QEMUFile *f, void *opaque)
 359 {
 360     SerialState *s = opaque;
 361
 362     qemu_put_be16s(f,&s->divider);
 363     qemu_put_8s(f,&s->rbr);
 364     qemu_put_8s(f,&s->ier);
 365     qemu_put_8s(f,&s->iir);
 366     qemu_put_8s(f,&s->lcr);
 367     qemu_put_8s(f,&s->mcr);
 368     qemu_put_8s(f,&s->lsr);
 369     qemu_put_8s(f,&s->msr);
 370     qemu_put_8s(f,&s->scr);
 371 }
 372
 373 static int serial_load(QEMUFile *f, void *opaque, int version_id)
 374 {
 375     SerialState *s = opaque;
 376
 377     if(version_id > 2)
 378         return -EINVAL;
 379
 380     if (version_id >= 2)
 381         qemu_get_be16s(f, &s->divider);
 382     else
 383         s->divider = qemu_get_byte(f);
 384     qemu_get_8s(f,&s->rbr);
 385     qemu_get_8s(f,&s->ier);
 386     qemu_get_8s(f,&s->iir);
 387     qemu_get_8s(f,&s->lcr);
 388     qemu_get_8s(f,&s->mcr);
 389     qemu_get_8s(f,&s->lsr);
 390     qemu_get_8s(f,&s->msr);
 391     qemu_get_8s(f,&s->scr);
 392
 393     return 0;
 394 }
 395
 396 static void serial_reset(void *opaque)
 397 {
 398     SerialState *s = opaque;
 399
 400     s->divider = 0;
 401     s->rbr = 0;
 402     s->ier = 0;
 403     s->iir = UART_IIR_NO_INT;
 404     s->lcr = 0;
 405     s->mcr = 0;
 406     s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
 407     s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
 408     s->scr = 0;
 409
 410     s->thr_ipending = 0;
 411     s->last_break_enable = 0;
 412     qemu_irq_lower(s->irq);
 413 }
 414
 415 /* If fd is zero, it means that the serial device uses the console */
 416 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr)
 417 {
 418     SerialState *s;
 419
 420     s = qemu_mallocz(sizeof(SerialState));
 421     if (!s)
 422         return NULL;
 423     s->irq = irq;
 424
 425     s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
 426     if (!s->tx_timer)
 427         return NULL;
 428
 429     qemu_register_reset(serial_reset, s);
 430     serial_reset(s);
 431
 432     register_savevm("serial", base, 2, serial_save, serial_load, s);
 433
 434     register_ioport_write(base, 8, 1, serial_ioport_write, s);
 435     register_ioport_read(base, 8, 1, serial_ioport_read, s);
 436     s->chr = chr;
 437     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 438                           serial_event, s);
 439     return s;
 440 }
 441
 442 /* Memory mapped interface */
 443 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr)
 444 {
 445     SerialState *s = opaque;
 446
 447     return serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFF;
 448 }
 449
 450 void serial_mm_writeb (void *opaque,
 451                        target_phys_addr_t addr, uint32_t value)
 452 {
 453     SerialState *s = opaque;
 454
 455     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFF);
 456 }
 457
 458 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr)
 459 {
 460     SerialState *s = opaque;
 461     uint32_t val;
 462
 463     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift) & 0xFFFF;
 464 #ifdef TARGET_WORDS_BIGENDIAN
 465     val = bswap16(val);
 466 #endif
 467     return val;
 468 }
 469
 470 void serial_mm_writew (void *opaque,
 471                        target_phys_addr_t addr, uint32_t value)
 472 {
 473     SerialState *s = opaque;
 474 #ifdef TARGET_WORDS_BIGENDIAN
 475     value = bswap16(value);
 476 #endif
 477     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value & 0xFFFF);
 478 }
 479
 480 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr)
 481 {
 482     SerialState *s = opaque;
 483     uint32_t val;
 484
 485     val = serial_ioport_read(s, (addr - s->base) >> s->it_shift);
 486 #ifdef TARGET_WORDS_BIGENDIAN
 487     val = bswap32(val);
 488 #endif
 489     return val;
 490 }
 491
 492 void serial_mm_writel (void *opaque,
 493                        target_phys_addr_t addr, uint32_t value)
 494 {
 495     SerialState *s = opaque;
 496 #ifdef TARGET_WORDS_BIGENDIAN
 497     value = bswap32(value);
 498 #endif
 499     serial_ioport_write(s, (addr - s->base) >> s->it_shift, value);
 500 }
 501
 502 static CPUReadMemoryFunc *serial_mm_read[] = {
 503     &serial_mm_readb,
 504     &serial_mm_readw,
 505     &serial_mm_readl,
 506 };
 507
 508 static CPUWriteMemoryFunc *serial_mm_write[] = {
 509     &serial_mm_writeb,
 510     &serial_mm_writew,
 511     &serial_mm_writel,
 512 };
 513
 514 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
 515                              qemu_irq irq, CharDriverState *chr,
 516                              int ioregister)
 517 {
 518     SerialState *s;
 519     int s_io_memory;
 520
 521     s = qemu_mallocz(sizeof(SerialState));
 522     if (!s)
 523         return NULL;
 524     s->irq = irq;
 525     s->base = base;
 526     s->it_shift = it_shift;
 527
 528     s->tx_timer = qemu_new_timer(vm_clock, serial_tx_done, s);
 529     if (!s->tx_timer)
 530         return NULL;
 531
 532     qemu_register_reset(serial_reset, s);
 533     serial_reset(s);
 534
 535     register_savevm("serial", base, 2, serial_save, serial_load, s);
 536
 537     if (ioregister) {
 538         s_io_memory = cpu_register_io_memory(0, serial_mm_read,
 539                                              serial_mm_write, s);
 540         cpu_register_physical_memory(base, 8 << it_shift, s_io_memory);
 541     }
 542     s->chr = chr;
 543     qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
 544                           serial_event, s);
 545     return s;
 546 }