hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27
  28 //#define DEBUG_IRQ_COUNT
  29 //#define DEBUG_IRQ
  30
  31 #ifdef DEBUG_IRQ
  32 #define DPRINTF(fmt, args...) \
  33 do { printf("IRQ: " fmt , ##args); } while (0)
  34 #else
  35 #define DPRINTF(fmt, args...)
  36 #endif
  37
  38 /*
  39  * Registers of interrupt controller in sun4m.
  40  *
  41  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * There is a system master controller and one for each cpu.
  46  *
  47  */
  48
  49 #define MAX_CPUS 16
  50 #define MAX_PILS 16
  51
  52 typedef struct SLAVIO_INTCTLState {
  53     uint32_t intreg_pending[MAX_CPUS];
  54     uint32_t intregm_pending;
  55     uint32_t intregm_disabled;
  56     uint32_t target_cpu;
  57 #ifdef DEBUG_IRQ_COUNT
  58     uint64_t irq_count[32];
  59 #endif
  60     qemu_irq *cpu_irqs[MAX_CPUS];
  61     const uint32_t *intbit_to_level;
  62     uint32_t cputimer_bit;
  63     uint32_t pil_out[MAX_CPUS];
  64 } SLAVIO_INTCTLState;
  65
  66 #define INTCTL_MAXADDR 0xf
  67 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  68 #define INTCTLM_MAXADDR 0x13
  69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  70 #define INTCTLM_MASK 0x1f
  71 static void slavio_check_interrupts(void *opaque);
  72
  73 // per-cpu interrupt controller
  74 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  75 {
  76     SLAVIO_INTCTLState *s = opaque;
  77     uint32_t saddr, ret;
  78     int cpu;
  79
  80     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  81     saddr = (addr & INTCTL_MAXADDR) >> 2;
  82     switch (saddr) {
  83     case 0:
  84         ret = s->intreg_pending[cpu];
  85         break;
  86     default:
  87         ret = 0;
  88         break;
  89     }
  90     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
  91
  92     return ret;
  93 }
  94
  95 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  96 {
  97     SLAVIO_INTCTLState *s = opaque;
  98     uint32_t saddr;
  99     int cpu;
 100
 101     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
 102     saddr = (addr & INTCTL_MAXADDR) >> 2;
 103     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
 104     switch (saddr) {
 105     case 1: // clear pending softints
 106         if (val & 0x4000)
 107             val |= 80000000;
 108         val &= 0xfffe0000;
 109         s->intreg_pending[cpu] &= ~val;
 110         slavio_check_interrupts(s);
 111         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 112         break;
 113     case 2: // set softint
 114         val &= 0xfffe0000;
 115         s->intreg_pending[cpu] |= val;
 116         slavio_check_interrupts(s);
 117         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
 118         break;
 119     default:
 120         break;
 121     }
 122 }
 123
 124 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 125     slavio_intctl_mem_readl,
 126     slavio_intctl_mem_readl,
 127     slavio_intctl_mem_readl,
 128 };
 129
 130 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 131     slavio_intctl_mem_writel,
 132     slavio_intctl_mem_writel,
 133     slavio_intctl_mem_writel,
 134 };
 135
 136 // master system interrupt controller
 137 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 138 {
 139     SLAVIO_INTCTLState *s = opaque;
 140     uint32_t saddr, ret;
 141
 142     saddr = (addr & INTCTLM_MAXADDR) >> 2;
 143     switch (saddr) {
 144     case 0:
 145         ret = s->intregm_pending & 0x7fffffff;
 146         break;
 147     case 1:
 148         ret = s->intregm_disabled;
 149         break;
 150     case 4:
 151         ret = s->target_cpu;
 152         break;
 153     default:
 154         ret = 0;
 155         break;
 156     }
 157     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 158
 159     return ret;
 160 }
 161
 162 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 163 {
 164     SLAVIO_INTCTLState *s = opaque;
 165     uint32_t saddr;
 166
 167     saddr = (addr & INTCTLM_MASK) >> 2;
 168     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 169     switch (saddr) {
 170     case 2: // clear (enable)
 171         // Force clear unused bits
 172         val &= ~0x4fb2007f;
 173         s->intregm_disabled &= ~val;
 174         DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 175         slavio_check_interrupts(s);
 176         break;
 177     case 3: // set (disable, clear pending)
 178         // Force clear unused bits
 179         val &= ~0x4fb2007f;
 180         s->intregm_disabled |= val;
 181         s->intregm_pending &= ~val;
 182         slavio_check_interrupts(s);
 183         DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
 184         break;
 185     case 4:
 186         s->target_cpu = val & (MAX_CPUS - 1);
 187         slavio_check_interrupts(s);
 188         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 189         break;
 190     default:
 191         break;
 192     }
 193 }
 194
 195 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 196     slavio_intctlm_mem_readl,
 197     slavio_intctlm_mem_readl,
 198     slavio_intctlm_mem_readl,
 199 };
 200
 201 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 202     slavio_intctlm_mem_writel,
 203     slavio_intctlm_mem_writel,
 204     slavio_intctlm_mem_writel,
 205 };
 206
 207 void slavio_pic_info(void *opaque)
 208 {
 209     SLAVIO_INTCTLState *s = opaque;
 210     int i;
 211
 212     for (i = 0; i < MAX_CPUS; i++) {
 213         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 214     }
 215     term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
 216 }
 217
 218 void slavio_irq_info(void *opaque)
 219 {
 220 #ifndef DEBUG_IRQ_COUNT
 221     term_printf("irq statistic code not compiled.\n");
 222 #else
 223     SLAVIO_INTCTLState *s = opaque;
 224     int i;
 225     int64_t count;
 226
 227     term_printf("IRQ statistics:\n");
 228     for (i = 0; i < 32; i++) {
 229         count = s->irq_count[i];
 230         if (count > 0)
 231             term_printf("%2d: %" PRId64 "\n", i, count);
 232     }
 233 #endif
 234 }
 235
 236 static void slavio_check_interrupts(void *opaque)
 237 {
 238     SLAVIO_INTCTLState *s = opaque;
 239     uint32_t pending = s->intregm_pending, pil_pending;
 240     unsigned int i, j;
 241
 242     pending &= ~s->intregm_disabled;
 243
 244     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 245     for (i = 0; i < MAX_CPUS; i++) {
 246         pil_pending = 0;
 247         if (pending && !(s->intregm_disabled & 0x80000000) &&
 248             (i == s->target_cpu)) {
 249             for (j = 0; j < 32; j++) {
 250                 if (pending & (1 << j))
 251                     pil_pending |= 1 << s->intbit_to_level[j];
 252             }
 253         }
 254         pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe;
 255
 256         for (j = 0; j < MAX_PILS; j++) {
 257             if (pil_pending & (1 << j)) {
 258                 if (!(s->pil_out[i] & (1 << j)))
 259                     qemu_irq_raise(s->cpu_irqs[i][j]);
 260             } else {
 261                 if (s->pil_out[i] & (1 << j))
 262                     qemu_irq_lower(s->cpu_irqs[i][j]);
 263             }
 264         }
 265         s->pil_out[i] = pil_pending;
 266     }
 267 }
 268
 269 /*
 270  * "irq" here is the bit number in the system interrupt register to
 271  * separate serial and keyboard interrupts sharing a level.
 272  */
 273 static void slavio_set_irq(void *opaque, int irq, int level)
 274 {
 275     SLAVIO_INTCTLState *s = opaque;
 276     uint32_t mask = 1 << irq;
 277     uint32_t pil = s->intbit_to_level[irq];
 278
 279     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 280             level);
 281     if (pil > 0) {
 282         if (level) {
 283 #ifdef DEBUG_IRQ_COUNT
 284             s->irq_count[pil]++;
 285 #endif
 286             s->intregm_pending |= mask;
 287             s->intreg_pending[s->target_cpu] |= 1 << pil;
 288         } else {
 289             s->intregm_pending &= ~mask;
 290             s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 291         }
 292         slavio_check_interrupts(s);
 293     }
 294 }
 295
 296 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 297 {
 298     SLAVIO_INTCTLState *s = opaque;
 299
 300     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 301
 302     if (level)
 303         s->intreg_pending[cpu] |= s->cputimer_bit;
 304     else
 305         s->intreg_pending[cpu] &= ~s->cputimer_bit;
 306
 307     slavio_check_interrupts(s);
 308 }
 309
 310 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 311 {
 312     SLAVIO_INTCTLState *s = opaque;
 313     int i;
 314
 315     for (i = 0; i < MAX_CPUS; i++) {
 316         qemu_put_be32s(f, &s->intreg_pending[i]);
 317     }
 318     qemu_put_be32s(f, &s->intregm_pending);
 319     qemu_put_be32s(f, &s->intregm_disabled);
 320     qemu_put_be32s(f, &s->target_cpu);
 321 }
 322
 323 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 324 {
 325     SLAVIO_INTCTLState *s = opaque;
 326     int i;
 327
 328     if (version_id != 1)
 329         return -EINVAL;
 330
 331     for (i = 0; i < MAX_CPUS; i++) {
 332         qemu_get_be32s(f, &s->intreg_pending[i]);
 333     }
 334     qemu_get_be32s(f, &s->intregm_pending);
 335     qemu_get_be32s(f, &s->intregm_disabled);
 336     qemu_get_be32s(f, &s->target_cpu);
 337     slavio_check_interrupts(s);
 338     return 0;
 339 }
 340
 341 static void slavio_intctl_reset(void *opaque)
 342 {
 343     SLAVIO_INTCTLState *s = opaque;
 344     int i;
 345
 346     for (i = 0; i < MAX_CPUS; i++) {
 347         s->intreg_pending[i] = 0;
 348     }
 349     s->intregm_disabled = ~0xffb2007f;
 350     s->intregm_pending = 0;
 351     s->target_cpu = 0;
 352     slavio_check_interrupts(s);
 353 }
 354
 355 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 356                          const uint32_t *intbit_to_level,
 357                          qemu_irq **irq, qemu_irq **cpu_irq,
 358                          qemu_irq **parent_irq, unsigned int cputimer)
 359 {
 360     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 361     SLAVIO_INTCTLState *s;
 362
 363     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 364     if (!s)
 365         return NULL;
 366
 367     s->intbit_to_level = intbit_to_level;
 368     for (i = 0; i < MAX_CPUS; i++) {
 369         slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
 370         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 371                                      slavio_intctl_io_memory);
 372         s->cpu_irqs[i] = parent_irq[i];
 373     }
 374
 375     slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
 376     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 377
 378     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
 379     qemu_register_reset(slavio_intctl_reset, s);
 380     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 381
 382     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 383     s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
 384     slavio_intctl_reset(s);
 385     return s;
 386 }
 387