hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "monitor.h"
  27
  28 //#define DEBUG_IRQ_COUNT
  29 //#define DEBUG_IRQ
  30
  31 #ifdef DEBUG_IRQ
  32 #define DPRINTF(fmt, ...)                                       \
  33     do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
  34 #else
  35 #define DPRINTF(fmt, ...)
  36 #endif
  37
  38 /*
  39  * Registers of interrupt controller in sun4m.
  40  *
  41  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * There is a system master controller and one for each cpu.
  46  *
  47  */
  48
  49 #define MAX_CPUS 16
  50 #define MAX_PILS 16
  51
  52 struct SLAVIO_CPUINTCTLState;
  53
  54 typedef struct SLAVIO_INTCTLState {
  55     uint32_t intregm_pending;
  56     uint32_t intregm_disabled;
  57     uint32_t target_cpu;
  58 #ifdef DEBUG_IRQ_COUNT
  59     uint64_t irq_count[32];
  60 #endif
  61     qemu_irq *cpu_irqs[MAX_CPUS];
  62     const uint32_t *intbit_to_level;
  63     uint32_t cputimer_lbit, cputimer_mbit;
  64     uint32_t pil_out[MAX_CPUS];
  65     struct SLAVIO_CPUINTCTLState *slaves[MAX_CPUS];
  66 } SLAVIO_INTCTLState;
  67
  68 typedef struct SLAVIO_CPUINTCTLState {
  69     uint32_t intreg_pending;
  70     SLAVIO_INTCTLState *master;
  71     uint32_t cpu;
  72 } SLAVIO_CPUINTCTLState;
  73
  74 #define INTCTL_MAXADDR 0xf
  75 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  76 #define INTCTLM_SIZE 0x14
  77 #define MASTER_IRQ_MASK ~0x0fa2007f
  78 #define MASTER_DISABLE 0x80000000
  79 #define CPU_SOFTIRQ_MASK 0xfffe0000
  80 #define CPU_IRQ_INT15_IN 0x0004000
  81 #define CPU_IRQ_INT15_MASK 0x80000000
  82
  83 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs);
  84
  85 // per-cpu interrupt controller
  86 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  87 {
  88     SLAVIO_CPUINTCTLState *s = opaque;
  89     uint32_t saddr, ret;
  90
  91     saddr = addr >> 2;
  92     switch (saddr) {
  93     case 0:
  94         ret = s->intreg_pending;
  95         break;
  96     default:
  97         ret = 0;
  98         break;
  99     }
 100     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, ret);
 101
 102     return ret;
 103 }
 104
 105 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
 106                                      uint32_t val)
 107 {
 108     SLAVIO_CPUINTCTLState *s = opaque;
 109     uint32_t saddr;
 110
 111     saddr = addr >> 2;
 112     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", s->cpu, addr, val);
 113     switch (saddr) {
 114     case 1: // clear pending softints
 115         if (val & CPU_IRQ_INT15_IN)
 116             val |= CPU_IRQ_INT15_MASK;
 117         val &= CPU_SOFTIRQ_MASK;
 118         s->intreg_pending &= ~val;
 119         slavio_check_interrupts(s->master, 1);
 120         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 121                 s->intreg_pending);
 122         break;
 123     case 2: // set softint
 124         val &= CPU_SOFTIRQ_MASK;
 125         s->intreg_pending |= val;
 126         slavio_check_interrupts(s->master, 1);
 127         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", s->cpu, val,
 128                 s->intreg_pending);
 129         break;
 130     default:
 131         break;
 132     }
 133 }
 134
 135 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 136     NULL,
 137     NULL,
 138     slavio_intctl_mem_readl,
 139 };
 140
 141 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 142     NULL,
 143     NULL,
 144     slavio_intctl_mem_writel,
 145 };
 146
 147 // master system interrupt controller
 148 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 149 {
 150     SLAVIO_INTCTLState *s = opaque;
 151     uint32_t saddr, ret;
 152
 153     saddr = addr >> 2;
 154     switch (saddr) {
 155     case 0:
 156         ret = s->intregm_pending & ~MASTER_DISABLE;
 157         break;
 158     case 1:
 159         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 160         break;
 161     case 4:
 162         ret = s->target_cpu;
 163         break;
 164     default:
 165         ret = 0;
 166         break;
 167     }
 168     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 169
 170     return ret;
 171 }
 172
 173 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
 174                                       uint32_t val)
 175 {
 176     SLAVIO_INTCTLState *s = opaque;
 177     uint32_t saddr;
 178
 179     saddr = addr >> 2;
 180     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 181     switch (saddr) {
 182     case 2: // clear (enable)
 183         // Force clear unused bits
 184         val &= MASTER_IRQ_MASK;
 185         s->intregm_disabled &= ~val;
 186         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
 187                 s->intregm_disabled);
 188         slavio_check_interrupts(s, 1);
 189         break;
 190     case 3: // set (disable, clear pending)
 191         // Force clear unused bits
 192         val &= MASTER_IRQ_MASK;
 193         s->intregm_disabled |= val;
 194         s->intregm_pending &= ~val;
 195         slavio_check_interrupts(s, 1);
 196         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
 197                 s->intregm_disabled);
 198         break;
 199     case 4:
 200         s->target_cpu = val & (MAX_CPUS - 1);
 201         slavio_check_interrupts(s, 1);
 202         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 203         break;
 204     default:
 205         break;
 206     }
 207 }
 208
 209 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 210     NULL,
 211     NULL,
 212     slavio_intctlm_mem_readl,
 213 };
 214
 215 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 216     NULL,
 217     NULL,
 218     slavio_intctlm_mem_writel,
 219 };
 220
 221 void slavio_pic_info(Monitor *mon, void *opaque)
 222 {
 223     SLAVIO_INTCTLState *s = opaque;
 224     int i;
 225
 226     for (i = 0; i < MAX_CPUS; i++) {
 227         monitor_printf(mon, "per-cpu %d: pending 0x%08x\n", i,
 228                        s->slaves[i]->intreg_pending);
 229     }
 230     monitor_printf(mon, "master: pending 0x%08x, disabled 0x%08x\n",
 231                    s->intregm_pending, s->intregm_disabled);
 232 }
 233
 234 void slavio_irq_info(Monitor *mon, void *opaque)
 235 {
 236 #ifndef DEBUG_IRQ_COUNT
 237     monitor_printf(mon, "irq statistic code not compiled.\n");
 238 #else
 239     SLAVIO_INTCTLState *s = opaque;
 240     int i;
 241     int64_t count;
 242
 243     monitor_printf(mon, "IRQ statistics:\n");
 244     for (i = 0; i < 32; i++) {
 245         count = s->irq_count[i];
 246         if (count > 0)
 247             monitor_printf(mon, "%2d: %" PRId64 "\n", i, count);
 248     }
 249 #endif
 250 }
 251
 252 static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs)
 253 {
 254     uint32_t pending = s->intregm_pending, pil_pending;
 255     unsigned int i, j;
 256
 257     pending &= ~s->intregm_disabled;
 258
 259     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 260     for (i = 0; i < MAX_CPUS; i++) {
 261         pil_pending = 0;
 262         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 263             (i == s->target_cpu)) {
 264             for (j = 0; j < 32; j++) {
 265                 if (pending & (1 << j))
 266                     pil_pending |= 1 << s->intbit_to_level[j];
 267             }
 268         }
 269         pil_pending |= (s->slaves[i]->intreg_pending & CPU_SOFTIRQ_MASK) >> 16;
 270
 271         if (set_irqs) {
 272             for (j = 0; j < MAX_PILS; j++) {
 273                 if (pil_pending & (1 << j)) {
 274                     if (!(s->pil_out[i] & (1 << j))) {
 275                         qemu_irq_raise(s->cpu_irqs[i][j]);
 276                     }
 277                 } else {
 278                     if (s->pil_out[i] & (1 << j)) {
 279                         qemu_irq_lower(s->cpu_irqs[i][j]);
 280                     }
 281                 }
 282             }
 283         }
 284         s->pil_out[i] = pil_pending;
 285     }
 286 }
 287
 288 /*
 289  * "irq" here is the bit number in the system interrupt register to
 290  * separate serial and keyboard interrupts sharing a level.
 291  */
 292 static void slavio_set_irq(void *opaque, int irq, int level)
 293 {
 294     SLAVIO_INTCTLState *s = opaque;
 295     uint32_t mask = 1 << irq;
 296     uint32_t pil = s->intbit_to_level[irq];
 297
 298     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 299             level);
 300     if (pil > 0) {
 301         if (level) {
 302 #ifdef DEBUG_IRQ_COUNT
 303             s->irq_count[pil]++;
 304 #endif
 305             s->intregm_pending |= mask;
 306             s->slaves[s->target_cpu]->intreg_pending |= 1 << pil;
 307         } else {
 308             s->intregm_pending &= ~mask;
 309             s->slaves[s->target_cpu]->intreg_pending &= ~(1 << pil);
 310         }
 311         slavio_check_interrupts(s, 1);
 312     }
 313 }
 314
 315 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 316 {
 317     SLAVIO_INTCTLState *s = opaque;
 318
 319     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 320
 321     if (level) {
 322         s->intregm_pending |= s->cputimer_mbit;
 323         s->slaves[cpu]->intreg_pending |= s->cputimer_lbit;
 324     } else {
 325         s->intregm_pending &= ~s->cputimer_mbit;
 326         s->slaves[cpu]->intreg_pending &= ~s->cputimer_lbit;
 327     }
 328
 329     slavio_check_interrupts(s, 1);
 330 }
 331
 332 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 333 {
 334     SLAVIO_INTCTLState *s = opaque;
 335     int i;
 336
 337     for (i = 0; i < MAX_CPUS; i++) {
 338         qemu_put_be32s(f, &s->slaves[i]->intreg_pending);
 339     }
 340     qemu_put_be32s(f, &s->intregm_pending);
 341     qemu_put_be32s(f, &s->intregm_disabled);
 342     qemu_put_be32s(f, &s->target_cpu);
 343 }
 344
 345 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 346 {
 347     SLAVIO_INTCTLState *s = opaque;
 348     int i;
 349
 350     if (version_id != 1)
 351         return -EINVAL;
 352
 353     for (i = 0; i < MAX_CPUS; i++) {
 354         qemu_get_be32s(f, &s->slaves[i]->intreg_pending);
 355     }
 356     qemu_get_be32s(f, &s->intregm_pending);
 357     qemu_get_be32s(f, &s->intregm_disabled);
 358     qemu_get_be32s(f, &s->target_cpu);
 359     slavio_check_interrupts(s, 0);
 360     return 0;
 361 }
 362
 363 static void slavio_intctl_reset(void *opaque)
 364 {
 365     SLAVIO_INTCTLState *s = opaque;
 366     int i;
 367
 368     for (i = 0; i < MAX_CPUS; i++) {
 369         s->slaves[i]->intreg_pending = 0;
 370     }
 371     s->intregm_disabled = ~MASTER_IRQ_MASK;
 372     s->intregm_pending = 0;
 373     s->target_cpu = 0;
 374     slavio_check_interrupts(s, 0);
 375 }
 376
 377 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 378                          const uint32_t *intbit_to_level,
 379                          qemu_irq **irq, qemu_irq **cpu_irq,
 380                          qemu_irq **parent_irq, unsigned int cputimer)
 381 {
 382     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 383     SLAVIO_INTCTLState *s;
 384     SLAVIO_CPUINTCTLState *slave;
 385
 386     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 387
 388     s->intbit_to_level = intbit_to_level;
 389     for (i = 0; i < MAX_CPUS; i++) {
 390         slave = qemu_mallocz(sizeof(SLAVIO_CPUINTCTLState));
 391
 392         slave->cpu = i;
 393         slave->master = s;
 394
 395         slavio_intctl_io_memory = cpu_register_io_memory(slavio_intctl_mem_read,
 396                                                          slavio_intctl_mem_write,
 397                                                          slave);
 398         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 399                                      slavio_intctl_io_memory);
 400
 401         s->slaves[i] = slave;
 402         s->cpu_irqs[i] = parent_irq[i];
 403     }
 404
 405     slavio_intctlm_io_memory = cpu_register_io_memory(slavio_intctlm_mem_read,
 406                                                       slavio_intctlm_mem_write,
 407                                                       s);
 408     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 409
 410     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
 411                     slavio_intctl_load, s);
 412     qemu_register_reset(slavio_intctl_reset, s);
 413     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 414
 415     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 416     s->cputimer_mbit = 1 << cputimer;
 417     s->cputimer_lbit = 1 << intbit_to_level[cputimer];
 418     slavio_intctl_reset(s);
 419     return s;
 420 }