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git.proxmox.com Git - qemu.git/blob - hw/slavio_timer.c
2 * QEMU Sparc SLAVIO timer controller emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "qemu-timer.h"
31 #define DPRINTF(fmt, args...) \
32 do { printf("TIMER: " fmt , ##args); } while (0)
34 #define DPRINTF(fmt, args...)
38 * Registers of hardware timer in sun4m.
40 * This is the timer/counter part of chip STP2001 (Slave I/O), also
41 * produced as NCR89C105. See
42 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
44 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
45 * are zero. Bit 31 is 1 when count has been reached.
47 * Per-CPU timers interrupt local CPU, system timer uses normal
54 typedef struct SLAVIO_TIMERState
{
57 uint32_t count
, counthigh
, reached
;
61 struct SLAVIO_TIMERState
*master
;
64 unsigned int num_slaves
;
65 struct SLAVIO_TIMERState
*slave
[MAX_CPUS
];
69 #define TIMER_MAXADDR 0x1f
70 #define SYS_TIMER_SIZE 0x14
71 #define CPU_TIMER_SIZE 0x10
73 #define SYS_TIMER_OFFSET 0x10000ULL
74 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
77 #define TIMER_COUNTER 1
78 #define TIMER_COUNTER_NORST 2
79 #define TIMER_STATUS 3
82 #define TIMER_COUNT_MASK32 0xfffffe00
83 #define TIMER_LIMIT_MASK32 0x7fffffff
84 #define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
85 #define TIMER_MAX_COUNT32 0x7ffffe00ULL
86 #define TIMER_REACHED 0x80000000
87 #define TIMER_PERIOD 500ULL // 500ns
88 #define LIMIT_TO_PERIODS(l) ((l) >> 9)
89 #define PERIODS_TO_LIMIT(l) ((l) << 9)
91 static int slavio_timer_is_user(SLAVIO_TIMERState
*s
)
93 return s
->master
&& (s
->master
->slave_mode
& (1 << s
->slave_index
));
96 // Update count, set irq, update expire_time
97 // Convert from ptimer countdown units
98 static void slavio_timer_get_out(SLAVIO_TIMERState
*s
)
100 uint64_t count
, limit
;
102 if (s
->limit
== 0) /* free-run processor or system counter */
103 limit
= TIMER_MAX_COUNT32
;
108 count
= limit
- PERIODS_TO_LIMIT(ptimer_get_count(s
->timer
));
112 DPRINTF("get_out: limit %" PRIx64
" count %x%08x\n", s
->limit
,
113 s
->counthigh
, s
->count
);
114 s
->count
= count
& TIMER_COUNT_MASK32
;
115 s
->counthigh
= count
>> 32;
119 static void slavio_timer_irq(void *opaque
)
121 SLAVIO_TIMERState
*s
= opaque
;
123 slavio_timer_get_out(s
);
124 DPRINTF("callback: count %x%08x\n", s
->counthigh
, s
->count
);
125 if (!slavio_timer_is_user(s
)) {
126 s
->reached
= TIMER_REACHED
;
127 qemu_irq_raise(s
->irq
);
131 static uint32_t slavio_timer_mem_readl(void *opaque
, target_phys_addr_t addr
)
133 SLAVIO_TIMERState
*s
= opaque
;
136 saddr
= (addr
& TIMER_MAXADDR
) >> 2;
139 // read limit (system counter mode) or read most signifying
140 // part of counter (user mode)
141 if (slavio_timer_is_user(s
)) {
142 // read user timer MSW
143 slavio_timer_get_out(s
);
148 qemu_irq_lower(s
->irq
);
150 ret
= s
->limit
& TIMER_LIMIT_MASK32
;
154 // read counter and reached bit (system mode) or read lsbits
155 // of counter (user mode)
156 slavio_timer_get_out(s
);
157 if (slavio_timer_is_user(s
)) // read user timer LSW
158 ret
= s
->count
& TIMER_COUNT_MASK32
;
160 ret
= (s
->count
& TIMER_MAX_COUNT32
) | s
->reached
;
163 // only available in processor counter/timer
164 // read start/stop status
168 // only available in system counter
169 // read user/system mode
173 DPRINTF("invalid read address " TARGET_FMT_plx
"\n", addr
);
177 DPRINTF("read " TARGET_FMT_plx
" = %08x\n", addr
, ret
);
182 static void slavio_timer_mem_writel(void *opaque
, target_phys_addr_t addr
,
185 SLAVIO_TIMERState
*s
= opaque
;
188 DPRINTF("write " TARGET_FMT_plx
" %08x\n", addr
, val
);
189 saddr
= (addr
& TIMER_MAXADDR
) >> 2;
192 if (slavio_timer_is_user(s
)) {
193 // set user counter MSW, reset counter
194 qemu_irq_lower(s
->irq
);
195 s
->limit
= TIMER_MAX_COUNT64
;
196 DPRINTF("processor %d user timer reset\n", s
->slave_index
);
198 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 1);
200 // set limit, reset counter
201 qemu_irq_lower(s
->irq
);
202 s
->limit
= val
& TIMER_MAX_COUNT32
;
204 if (s
->limit
== 0) /* free-run */
205 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
207 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 1);
212 if (slavio_timer_is_user(s
)) {
213 // set user counter LSW, reset counter
214 qemu_irq_lower(s
->irq
);
215 s
->limit
= TIMER_MAX_COUNT64
;
216 DPRINTF("processor %d user timer reset\n", s
->slave_index
);
218 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 1);
220 DPRINTF("not user timer\n");
222 case TIMER_COUNTER_NORST
:
223 // set limit without resetting counter
224 s
->limit
= val
& TIMER_MAX_COUNT32
;
226 if (s
->limit
== 0) /* free-run */
227 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 0);
229 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(s
->limit
), 0);
233 if (slavio_timer_is_user(s
)) {
234 // start/stop user counter
235 if ((val
& 1) && !s
->running
) {
236 DPRINTF("processor %d user timer started\n", s
->slave_index
);
238 ptimer_run(s
->timer
, 0);
240 } else if (!(val
& 1) && s
->running
) {
241 DPRINTF("processor %d user timer stopped\n", s
->slave_index
);
243 ptimer_stop(s
->timer
);
249 if (s
->master
== NULL
) {
252 for (i
= 0; i
< s
->num_slaves
; i
++) {
253 if (val
& (1 << i
)) {
254 qemu_irq_lower(s
->slave
[i
]->irq
);
255 s
->slave
[i
]->limit
= -1ULL;
257 ptimer_stop(s
->slave
[i
]->timer
);
259 if ((val
& (1 << i
)) != (s
->slave_mode
& (1 << i
))) {
260 ptimer_stop(s
->slave
[i
]->timer
);
261 ptimer_set_limit(s
->slave
[i
]->timer
,
262 LIMIT_TO_PERIODS(s
->slave
[i
]->limit
), 1);
263 DPRINTF("processor %d timer changed\n",
264 s
->slave
[i
]->slave_index
);
265 ptimer_run(s
->slave
[i
]->timer
, 0);
268 s
->slave_mode
= val
& ((1 << s
->num_slaves
) - 1);
270 DPRINTF("not system timer\n");
273 DPRINTF("invalid write address " TARGET_FMT_plx
"\n", addr
);
278 static CPUReadMemoryFunc
*slavio_timer_mem_read
[3] = {
279 slavio_timer_mem_readl
,
280 slavio_timer_mem_readl
,
281 slavio_timer_mem_readl
,
284 static CPUWriteMemoryFunc
*slavio_timer_mem_write
[3] = {
285 slavio_timer_mem_writel
,
286 slavio_timer_mem_writel
,
287 slavio_timer_mem_writel
,
290 static void slavio_timer_save(QEMUFile
*f
, void *opaque
)
292 SLAVIO_TIMERState
*s
= opaque
;
294 qemu_put_be64s(f
, &s
->limit
);
295 qemu_put_be32s(f
, &s
->count
);
296 qemu_put_be32s(f
, &s
->counthigh
);
297 qemu_put_be32s(f
, &s
->reached
);
298 qemu_put_be32s(f
, &s
->running
);
300 qemu_put_ptimer(f
, s
->timer
);
303 static int slavio_timer_load(QEMUFile
*f
, void *opaque
, int version_id
)
305 SLAVIO_TIMERState
*s
= opaque
;
310 qemu_get_be64s(f
, &s
->limit
);
311 qemu_get_be32s(f
, &s
->count
);
312 qemu_get_be32s(f
, &s
->counthigh
);
313 qemu_get_be32s(f
, &s
->reached
);
314 qemu_get_be32s(f
, &s
->running
);
316 qemu_get_ptimer(f
, s
->timer
);
321 static void slavio_timer_reset(void *opaque
)
323 SLAVIO_TIMERState
*s
= opaque
;
329 if (!s
->master
|| s
->slave_index
< s
->master
->num_slaves
) {
330 ptimer_set_limit(s
->timer
, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32
), 1);
331 ptimer_run(s
->timer
, 0);
334 qemu_irq_lower(s
->irq
);
337 static SLAVIO_TIMERState
*slavio_timer_init(target_phys_addr_t addr
,
339 SLAVIO_TIMERState
*master
,
342 int slavio_timer_io_memory
;
343 SLAVIO_TIMERState
*s
;
346 s
= qemu_mallocz(sizeof(SLAVIO_TIMERState
));
351 s
->slave_index
= slave_index
;
352 if (!master
|| slave_index
< master
->num_slaves
) {
353 bh
= qemu_bh_new(slavio_timer_irq
, s
);
354 s
->timer
= ptimer_init(bh
);
355 ptimer_set_period(s
->timer
, TIMER_PERIOD
);
358 slavio_timer_io_memory
= cpu_register_io_memory(0, slavio_timer_mem_read
,
359 slavio_timer_mem_write
, s
);
361 cpu_register_physical_memory(addr
, CPU_TIMER_SIZE
,
362 slavio_timer_io_memory
);
364 cpu_register_physical_memory(addr
, SYS_TIMER_SIZE
,
365 slavio_timer_io_memory
);
366 register_savevm("slavio_timer", addr
, 3, slavio_timer_save
,
367 slavio_timer_load
, s
);
368 qemu_register_reset(slavio_timer_reset
, s
);
369 slavio_timer_reset(s
);
374 void slavio_timer_init_all(target_phys_addr_t base
, qemu_irq master_irq
,
375 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
377 SLAVIO_TIMERState
*master
;
380 master
= slavio_timer_init(base
+ SYS_TIMER_OFFSET
, master_irq
, NULL
, 0);
382 master
->num_slaves
= num_cpus
;
384 for (i
= 0; i
< MAX_CPUS
; i
++) {
385 master
->slave
[i
] = slavio_timer_init(base
+ (target_phys_addr_t
)
387 cpu_irqs
[i
], master
, i
);