hw/slavio_timer.c

   1 /*
   2  * QEMU Sparc SLAVIO timer controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 //#define DEBUG_TIMER
  27
  28 #ifdef DEBUG_TIMER
  29 #define DPRINTF(fmt, args...) \
  30 do { printf("TIMER: " fmt , ##args); } while (0)
  31 #else
  32 #define DPRINTF(fmt, args...)
  33 #endif
  34
  35 /*
  36  * Registers of hardware timer in sun4m.
  37  *
  38  * This is the timer/counter part of chip STP2001 (Slave I/O), also
  39  * produced as NCR89C105. See
  40  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  41  *
  42  * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
  43  * are zero. Bit 31 is 1 when count has been reached.
  44  *
  45  * Per-CPU timers interrupt local CPU, system timer uses normal
  46  * interrupt routing.
  47  *
  48  */
  49
  50 #define MAX_CPUS 16
  51
  52 typedef struct SLAVIO_TIMERState {
  53     qemu_irq irq;
  54     ptimer_state *timer;
  55     uint32_t count, counthigh, reached;
  56     uint64_t limit;
  57     int stopped;
  58     int mode; // 0 = processor, 1 = user, 2 = system
  59     struct SLAVIO_TIMERState *slave[MAX_CPUS];
  60     uint32_t slave_mode;
  61 } SLAVIO_TIMERState;
  62
  63 #define TIMER_MAXADDR 0x1f
  64 #define TIMER_SIZE (TIMER_MAXADDR + 1)
  65 #define CPU_TIMER_SIZE 0x10
  66
  67 // Update count, set irq, update expire_time
  68 // Convert from ptimer countdown units
  69 static void slavio_timer_get_out(SLAVIO_TIMERState *s)
  70 {
  71     uint64_t count;
  72
  73     count = s->limit - (ptimer_get_count(s->timer) << 9);
  74     DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
  75             s->count);
  76     s->count = count & 0xfffffe00;
  77     s->counthigh = count >> 32;
  78 }
  79
  80 // timer callback
  81 static void slavio_timer_irq(void *opaque)
  82 {
  83     SLAVIO_TIMERState *s = opaque;
  84
  85     slavio_timer_get_out(s);
  86     DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
  87     s->reached = 0x80000000;
  88     if (s->mode != 1)
  89         qemu_irq_raise(s->irq);
  90 }
  91
  92 static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
  93 {
  94     SLAVIO_TIMERState *s = opaque;
  95     uint32_t saddr, ret;
  96
  97     saddr = (addr & TIMER_MAXADDR) >> 2;
  98     switch (saddr) {
  99     case 0:
 100         // read limit (system counter mode) or read most signifying
 101         // part of counter (user mode)
 102         if (s->mode != 1) {
 103             // clear irq
 104             qemu_irq_lower(s->irq);
 105             s->reached = 0;
 106             ret = s->limit & 0x7fffffff;
 107         }
 108         else {
 109             slavio_timer_get_out(s);
 110             ret = s->counthigh & 0x7fffffff;
 111         }
 112         break;
 113     case 1:
 114         // read counter and reached bit (system mode) or read lsbits
 115         // of counter (user mode)
 116         slavio_timer_get_out(s);
 117         if (s->mode != 1)
 118             ret = (s->count & 0x7fffffff) | s->reached;
 119         else
 120             ret = s->count;
 121         break;
 122     case 3:
 123         // read start/stop status
 124         ret = s->stopped;
 125         break;
 126     case 4:
 127         // read user/system mode
 128         ret = s->slave_mode;
 129         break;
 130     default:
 131         ret = 0;
 132         break;
 133     }
 134     DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
 135
 136     return ret;
 137 }
 138
 139 static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 140 {
 141     SLAVIO_TIMERState *s = opaque;
 142     uint32_t saddr;
 143     int reload = 0;
 144
 145     DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
 146     saddr = (addr & TIMER_MAXADDR) >> 2;
 147     switch (saddr) {
 148     case 0:
 149         if (s->mode == 1) {
 150             // set user counter limit MSW, reset counter
 151             qemu_irq_lower(s->irq);
 152             s->limit &= 0xfffffe00ULL;
 153             s->limit |= (uint64_t)val << 32;
 154             if (!s->limit)
 155                 s->limit = 0x7ffffffffffffe00ULL;
 156             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 157             break;
 158         }
 159         // set limit, reset counter
 160         reload = 1;
 161         qemu_irq_lower(s->irq);
 162         // fall through
 163     case 2:
 164         // set limit without resetting counter
 165         s->limit = val & 0x7ffffe00ULL;
 166         if (!s->limit)
 167             s->limit = 0x7ffffe00ULL;
 168         ptimer_set_limit(s->timer, s->limit >> 9, reload);
 169         break;
 170     case 1:
 171         // set user counter limit LSW, reset counter
 172         if (s->mode == 1) {
 173             qemu_irq_lower(s->irq);
 174             s->limit &= 0x7fffffff00000000ULL;
 175             s->limit |= val & 0xfffffe00ULL;
 176             if (!s->limit)
 177                 s->limit = 0x7ffffffffffffe00ULL;
 178             ptimer_set_limit(s->timer, s->limit >> 9, 1);
 179         }
 180         break;
 181     case 3:
 182         // start/stop user counter
 183         if (s->mode == 1) {
 184             if (val & 1) {
 185                 ptimer_stop(s->timer);
 186                 s->stopped = 1;
 187             }
 188             else {
 189                 ptimer_run(s->timer, 0);
 190                 s->stopped = 0;
 191             }
 192         }
 193         break;
 194     case 4:
 195         // bit 0: user (1) or system (0) counter mode
 196         {
 197             unsigned int i;
 198
 199             for (i = 0; i < MAX_CPUS; i++) {
 200                 if (val & (1 << i)) {
 201                     qemu_irq_lower(s->slave[i]->irq);
 202                     s->slave[i]->limit = -1ULL;
 203                     s->slave[i]->mode = 1;
 204                 } else {
 205                     s->slave[i]->mode = 0;
 206                 }
 207                 ptimer_stop(s->slave[i]->timer);
 208                 ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9,
 209                                  1);
 210                 ptimer_run(s->slave[i]->timer, 0);
 211             }
 212             s->slave_mode = val & ((1 << MAX_CPUS) - 1);
 213         }
 214         break;
 215     default:
 216         break;
 217     }
 218 }
 219
 220 static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
 221     slavio_timer_mem_readl,
 222     slavio_timer_mem_readl,
 223     slavio_timer_mem_readl,
 224 };
 225
 226 static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
 227     slavio_timer_mem_writel,
 228     slavio_timer_mem_writel,
 229     slavio_timer_mem_writel,
 230 };
 231
 232 static void slavio_timer_save(QEMUFile *f, void *opaque)
 233 {
 234     SLAVIO_TIMERState *s = opaque;
 235
 236     qemu_put_be64s(f, &s->limit);
 237     qemu_put_be32s(f, &s->count);
 238     qemu_put_be32s(f, &s->counthigh);
 239     qemu_put_be32(f, 0); // Was irq
 240     qemu_put_be32s(f, &s->reached);
 241     qemu_put_be32s(f, &s->stopped);
 242     qemu_put_be32s(f, &s->mode);
 243     qemu_put_ptimer(f, s->timer);
 244 }
 245
 246 static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
 247 {
 248     SLAVIO_TIMERState *s = opaque;
 249     uint32_t tmp;
 250
 251     if (version_id != 2)
 252         return -EINVAL;
 253
 254     qemu_get_be64s(f, &s->limit);
 255     qemu_get_be32s(f, &s->count);
 256     qemu_get_be32s(f, &s->counthigh);
 257     qemu_get_be32s(f, &tmp); // Was irq
 258     qemu_get_be32s(f, &s->reached);
 259     qemu_get_be32s(f, &s->stopped);
 260     qemu_get_be32s(f, &s->mode);
 261     qemu_get_ptimer(f, s->timer);
 262
 263     return 0;
 264 }
 265
 266 static void slavio_timer_reset(void *opaque)
 267 {
 268     SLAVIO_TIMERState *s = opaque;
 269
 270     s->limit = 0x7ffffe00ULL;
 271     s->count = 0;
 272     s->reached = 0;
 273     s->mode &= 2;
 274     ptimer_set_limit(s->timer, s->limit >> 9, 1);
 275     ptimer_run(s->timer, 0);
 276     s->stopped = 1;
 277     qemu_irq_lower(s->irq);
 278 }
 279
 280 static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
 281                                             qemu_irq irq, int mode)
 282 {
 283     int slavio_timer_io_memory;
 284     SLAVIO_TIMERState *s;
 285     QEMUBH *bh;
 286
 287     s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
 288     if (!s)
 289         return s;
 290     s->irq = irq;
 291     s->mode = mode;
 292     bh = qemu_bh_new(slavio_timer_irq, s);
 293     s->timer = ptimer_init(bh);
 294     ptimer_set_period(s->timer, 500ULL);
 295
 296     slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
 297                                                     slavio_timer_mem_write, s);
 298     if (mode < 2)
 299         cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
 300     else
 301         cpu_register_physical_memory(addr, TIMER_SIZE,
 302                                      slavio_timer_io_memory);
 303     register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
 304     qemu_register_reset(slavio_timer_reset, s);
 305     slavio_timer_reset(s);
 306
 307     return s;
 308 }
 309
 310 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
 311                            qemu_irq *cpu_irqs)
 312 {
 313     SLAVIO_TIMERState *master;
 314     unsigned int i;
 315
 316     master = slavio_timer_init(base + 0x10000ULL, master_irq, 2);
 317
 318     for (i = 0; i < MAX_CPUS; i++) {
 319         master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
 320                                              (i * TARGET_PAGE_SIZE),
 321                                              cpu_irqs[i], 0);
 322     }
 323 }