]> git.proxmox.com Git - qemu.git/blob - hw/spapr.c
pseries: Instantiate USB interface when required
[qemu.git] / hw / spapr.c
1 /*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27 #include "sysemu.h"
28 #include "hw.h"
29 #include "elf.h"
30 #include "net.h"
31 #include "blockdev.h"
32 #include "cpus.h"
33 #include "kvm.h"
34 #include "kvm_ppc.h"
35
36 #include "hw/boards.h"
37 #include "hw/ppc.h"
38 #include "hw/loader.h"
39
40 #include "hw/spapr.h"
41 #include "hw/spapr_vio.h"
42 #include "hw/spapr_pci.h"
43 #include "hw/xics.h"
44 #include "hw/msi.h"
45
46 #include "kvm.h"
47 #include "kvm_ppc.h"
48 #include "pci.h"
49 #include "vga-pci.h"
50
51 #include "exec-memory.h"
52 #include "hw/usb.h"
53
54 #include <libfdt.h>
55
56 /* SLOF memory layout:
57 *
58 * SLOF raw image loaded at 0, copies its romfs right below the flat
59 * device-tree, then position SLOF itself 31M below that
60 *
61 * So we set FW_OVERHEAD to 40MB which should account for all of that
62 * and more
63 *
64 * We load our kernel at 4M, leaving space for SLOF initial image
65 */
66 #define FDT_MAX_SIZE 0x10000
67 #define RTAS_MAX_SIZE 0x10000
68 #define FW_MAX_SIZE 0x400000
69 #define FW_FILE_NAME "slof.bin"
70 #define FW_OVERHEAD 0x2800000
71 #define KERNEL_LOAD_ADDR FW_MAX_SIZE
72
73 #define MIN_RMA_SLOF 128UL
74
75 #define TIMEBASE_FREQ 512000000ULL
76
77 #define MAX_CPUS 256
78 #define XICS_IRQS 1024
79
80 #define SPAPR_PCI_BUID 0x800000020000001ULL
81 #define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000)
82 #define SPAPR_PCI_MEM_WIN_SIZE 0x20000000
83 #define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000)
84 #define SPAPR_PCI_MSI_WIN_ADDR (0x10000000000ULL + 0x90000000)
85
86 #define PHANDLE_XICP 0x00001111
87
88 sPAPREnvironment *spapr;
89
90 int spapr_allocate_irq(int hint, enum xics_irq_type type)
91 {
92 int irq;
93
94 if (hint) {
95 irq = hint;
96 /* FIXME: we should probably check for collisions somehow */
97 } else {
98 irq = spapr->next_irq++;
99 }
100
101 /* Configure irq type */
102 if (!xics_get_qirq(spapr->icp, irq)) {
103 return 0;
104 }
105
106 xics_set_irq_type(spapr->icp, irq, type);
107
108 return irq;
109 }
110
111 /* Allocate block of consequtive IRQs, returns a number of the first */
112 int spapr_allocate_irq_block(int num, enum xics_irq_type type)
113 {
114 int first = -1;
115 int i;
116
117 for (i = 0; i < num; ++i) {
118 int irq;
119
120 irq = spapr_allocate_irq(0, type);
121 if (!irq) {
122 return -1;
123 }
124
125 if (0 == i) {
126 first = irq;
127 }
128
129 /* If the above doesn't create a consecutive block then that's
130 * an internal bug */
131 assert(irq == (first + i));
132 }
133
134 return first;
135 }
136
137 static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
138 {
139 int ret = 0, offset;
140 CPUPPCState *env;
141 char cpu_model[32];
142 int smt = kvmppc_smt_threads();
143
144 assert(spapr->cpu_model);
145
146 for (env = first_cpu; env != NULL; env = env->next_cpu) {
147 uint32_t associativity[] = {cpu_to_be32(0x5),
148 cpu_to_be32(0x0),
149 cpu_to_be32(0x0),
150 cpu_to_be32(0x0),
151 cpu_to_be32(env->numa_node),
152 cpu_to_be32(env->cpu_index)};
153
154 if ((env->cpu_index % smt) != 0) {
155 continue;
156 }
157
158 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model,
159 env->cpu_index);
160
161 offset = fdt_path_offset(fdt, cpu_model);
162 if (offset < 0) {
163 return offset;
164 }
165
166 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
167 sizeof(associativity));
168 if (ret < 0) {
169 return ret;
170 }
171 }
172 return ret;
173 }
174
175
176 static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
177 size_t maxsize)
178 {
179 size_t maxcells = maxsize / sizeof(uint32_t);
180 int i, j, count;
181 uint32_t *p = prop;
182
183 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
184 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
185
186 if (!sps->page_shift) {
187 break;
188 }
189 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
190 if (sps->enc[count].page_shift == 0) {
191 break;
192 }
193 }
194 if ((p - prop) >= (maxcells - 3 - count * 2)) {
195 break;
196 }
197 *(p++) = cpu_to_be32(sps->page_shift);
198 *(p++) = cpu_to_be32(sps->slb_enc);
199 *(p++) = cpu_to_be32(count);
200 for (j = 0; j < count; j++) {
201 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
202 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
203 }
204 }
205
206 return (p - prop) * sizeof(uint32_t);
207 }
208
209 static void *spapr_create_fdt_skel(const char *cpu_model,
210 target_phys_addr_t rma_size,
211 target_phys_addr_t initrd_base,
212 target_phys_addr_t initrd_size,
213 target_phys_addr_t kernel_size,
214 const char *boot_device,
215 const char *kernel_cmdline,
216 long hash_shift)
217 {
218 void *fdt;
219 CPUPPCState *env;
220 uint64_t mem_reg_property[2];
221 uint32_t start_prop = cpu_to_be32(initrd_base);
222 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
223 uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
224 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
225 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
226 char qemu_hypertas_prop[] = "hcall-memop1";
227 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
228 int i;
229 char *modelname;
230 int smt = kvmppc_smt_threads();
231 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
232 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
233 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
234 cpu_to_be32(0x0), cpu_to_be32(0x0),
235 cpu_to_be32(0x0)};
236 char mem_name[32];
237 target_phys_addr_t node0_size, mem_start;
238
239 #define _FDT(exp) \
240 do { \
241 int ret = (exp); \
242 if (ret < 0) { \
243 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
244 #exp, fdt_strerror(ret)); \
245 exit(1); \
246 } \
247 } while (0)
248
249 fdt = g_malloc0(FDT_MAX_SIZE);
250 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
251
252 if (kernel_size) {
253 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
254 }
255 if (initrd_size) {
256 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
257 }
258 _FDT((fdt_finish_reservemap(fdt)));
259
260 /* Root node */
261 _FDT((fdt_begin_node(fdt, "")));
262 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
263 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
264
265 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
266 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
267
268 /* /chosen */
269 _FDT((fdt_begin_node(fdt, "chosen")));
270
271 /* Set Form1_affinity */
272 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
273
274 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
275 _FDT((fdt_property(fdt, "linux,initrd-start",
276 &start_prop, sizeof(start_prop))));
277 _FDT((fdt_property(fdt, "linux,initrd-end",
278 &end_prop, sizeof(end_prop))));
279 if (kernel_size) {
280 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
281 cpu_to_be64(kernel_size) };
282
283 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
284 }
285 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
286 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
287 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
288 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
289
290 _FDT((fdt_end_node(fdt)));
291
292 /* memory node(s) */
293 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
294 if (rma_size > node0_size) {
295 rma_size = node0_size;
296 }
297
298 /* RMA */
299 mem_reg_property[0] = 0;
300 mem_reg_property[1] = cpu_to_be64(rma_size);
301 _FDT((fdt_begin_node(fdt, "memory@0")));
302 _FDT((fdt_property_string(fdt, "device_type", "memory")));
303 _FDT((fdt_property(fdt, "reg", mem_reg_property,
304 sizeof(mem_reg_property))));
305 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
306 sizeof(associativity))));
307 _FDT((fdt_end_node(fdt)));
308
309 /* RAM: Node 0 */
310 if (node0_size > rma_size) {
311 mem_reg_property[0] = cpu_to_be64(rma_size);
312 mem_reg_property[1] = cpu_to_be64(node0_size - rma_size);
313
314 sprintf(mem_name, "memory@" TARGET_FMT_lx, rma_size);
315 _FDT((fdt_begin_node(fdt, mem_name)));
316 _FDT((fdt_property_string(fdt, "device_type", "memory")));
317 _FDT((fdt_property(fdt, "reg", mem_reg_property,
318 sizeof(mem_reg_property))));
319 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
320 sizeof(associativity))));
321 _FDT((fdt_end_node(fdt)));
322 }
323
324 /* RAM: Node 1 and beyond */
325 mem_start = node0_size;
326 for (i = 1; i < nb_numa_nodes; i++) {
327 mem_reg_property[0] = cpu_to_be64(mem_start);
328 mem_reg_property[1] = cpu_to_be64(node_mem[i]);
329 associativity[3] = associativity[4] = cpu_to_be32(i);
330 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
331 _FDT((fdt_begin_node(fdt, mem_name)));
332 _FDT((fdt_property_string(fdt, "device_type", "memory")));
333 _FDT((fdt_property(fdt, "reg", mem_reg_property,
334 sizeof(mem_reg_property))));
335 _FDT((fdt_property(fdt, "ibm,associativity", associativity,
336 sizeof(associativity))));
337 _FDT((fdt_end_node(fdt)));
338 mem_start += node_mem[i];
339 }
340
341 /* cpus */
342 _FDT((fdt_begin_node(fdt, "cpus")));
343
344 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
345 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
346
347 modelname = g_strdup(cpu_model);
348
349 for (i = 0; i < strlen(modelname); i++) {
350 modelname[i] = toupper(modelname[i]);
351 }
352
353 /* This is needed during FDT finalization */
354 spapr->cpu_model = g_strdup(modelname);
355
356 for (env = first_cpu; env != NULL; env = env->next_cpu) {
357 int index = env->cpu_index;
358 uint32_t servers_prop[smp_threads];
359 uint32_t gservers_prop[smp_threads * 2];
360 char *nodename;
361 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
362 0xffffffff, 0xffffffff};
363 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
364 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
365 uint32_t page_sizes_prop[64];
366 size_t page_sizes_prop_size;
367
368 if ((index % smt) != 0) {
369 continue;
370 }
371
372 if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
373 fprintf(stderr, "Allocation failure\n");
374 exit(1);
375 }
376
377 _FDT((fdt_begin_node(fdt, nodename)));
378
379 free(nodename);
380
381 _FDT((fdt_property_cell(fdt, "reg", index)));
382 _FDT((fdt_property_string(fdt, "device_type", "cpu")));
383
384 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
385 _FDT((fdt_property_cell(fdt, "dcache-block-size",
386 env->dcache_line_size)));
387 _FDT((fdt_property_cell(fdt, "icache-block-size",
388 env->icache_line_size)));
389 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
390 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
391 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
392 _FDT((fdt_property(fdt, "ibm,pft-size",
393 pft_size_prop, sizeof(pft_size_prop))));
394 _FDT((fdt_property_string(fdt, "status", "okay")));
395 _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
396
397 /* Build interrupt servers and gservers properties */
398 for (i = 0; i < smp_threads; i++) {
399 servers_prop[i] = cpu_to_be32(index + i);
400 /* Hack, direct the group queues back to cpu 0 */
401 gservers_prop[i*2] = cpu_to_be32(index + i);
402 gservers_prop[i*2 + 1] = 0;
403 }
404 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
405 servers_prop, sizeof(servers_prop))));
406 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
407 gservers_prop, sizeof(gservers_prop))));
408
409 if (env->mmu_model & POWERPC_MMU_1TSEG) {
410 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
411 segs, sizeof(segs))));
412 }
413
414 /* Advertise VMX/VSX (vector extensions) if available
415 * 0 / no property == no vector extensions
416 * 1 == VMX / Altivec available
417 * 2 == VSX available */
418 if (env->insns_flags & PPC_ALTIVEC) {
419 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
420
421 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
422 }
423
424 /* Advertise DFP (Decimal Floating Point) if available
425 * 0 / no property == no DFP
426 * 1 == DFP available */
427 if (env->insns_flags2 & PPC2_DFP) {
428 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
429 }
430
431 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
432 sizeof(page_sizes_prop));
433 if (page_sizes_prop_size) {
434 _FDT((fdt_property(fdt, "ibm,segment-page-sizes",
435 page_sizes_prop, page_sizes_prop_size)));
436 }
437
438 _FDT((fdt_end_node(fdt)));
439 }
440
441 g_free(modelname);
442
443 _FDT((fdt_end_node(fdt)));
444
445 /* RTAS */
446 _FDT((fdt_begin_node(fdt, "rtas")));
447
448 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
449 sizeof(hypertas_prop))));
450 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
451 sizeof(qemu_hypertas_prop))));
452
453 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
454 refpoints, sizeof(refpoints))));
455
456 _FDT((fdt_end_node(fdt)));
457
458 /* interrupt controller */
459 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
460
461 _FDT((fdt_property_string(fdt, "device_type",
462 "PowerPC-External-Interrupt-Presentation")));
463 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
464 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
465 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
466 interrupt_server_ranges_prop,
467 sizeof(interrupt_server_ranges_prop))));
468 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
469 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
470 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
471
472 _FDT((fdt_end_node(fdt)));
473
474 /* vdevice */
475 _FDT((fdt_begin_node(fdt, "vdevice")));
476
477 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
478 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
479 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
480 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
481 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
482 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
483
484 _FDT((fdt_end_node(fdt)));
485
486 _FDT((fdt_end_node(fdt))); /* close root node */
487 _FDT((fdt_finish(fdt)));
488
489 return fdt;
490 }
491
492 static void spapr_finalize_fdt(sPAPREnvironment *spapr,
493 target_phys_addr_t fdt_addr,
494 target_phys_addr_t rtas_addr,
495 target_phys_addr_t rtas_size)
496 {
497 int ret;
498 void *fdt;
499 sPAPRPHBState *phb;
500
501 fdt = g_malloc(FDT_MAX_SIZE);
502
503 /* open out the base tree into a temp buffer for the final tweaks */
504 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
505
506 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
507 if (ret < 0) {
508 fprintf(stderr, "couldn't setup vio devices in fdt\n");
509 exit(1);
510 }
511
512 QLIST_FOREACH(phb, &spapr->phbs, list) {
513 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
514 }
515
516 if (ret < 0) {
517 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
518 exit(1);
519 }
520
521 /* RTAS */
522 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
523 if (ret < 0) {
524 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
525 }
526
527 /* Advertise NUMA via ibm,associativity */
528 if (nb_numa_nodes > 1) {
529 ret = spapr_set_associativity(fdt, spapr);
530 if (ret < 0) {
531 fprintf(stderr, "Couldn't set up NUMA device tree properties\n");
532 }
533 }
534
535 if (!spapr->has_graphics) {
536 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
537 }
538
539 _FDT((fdt_pack(fdt)));
540
541 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
542 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
543 fdt_totalsize(fdt), FDT_MAX_SIZE);
544 exit(1);
545 }
546
547 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
548
549 g_free(fdt);
550 }
551
552 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
553 {
554 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
555 }
556
557 static void emulate_spapr_hypercall(CPUPPCState *env)
558 {
559 env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
560 }
561
562 static void spapr_reset(void *opaque)
563 {
564 sPAPREnvironment *spapr = (sPAPREnvironment *)opaque;
565
566 /* flush out the hash table */
567 memset(spapr->htab, 0, spapr->htab_size);
568
569 /* Load the fdt */
570 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
571 spapr->rtas_size);
572
573 /* Set up the entry state */
574 first_cpu->gpr[3] = spapr->fdt_addr;
575 first_cpu->gpr[5] = 0;
576 first_cpu->halted = 0;
577 first_cpu->nip = spapr->entry_point;
578
579 }
580
581 static void spapr_cpu_reset(void *opaque)
582 {
583 PowerPCCPU *cpu = opaque;
584
585 cpu_reset(CPU(cpu));
586 }
587
588 /* Returns whether we want to use VGA or not */
589 static int spapr_vga_init(PCIBus *pci_bus)
590 {
591 switch (vga_interface_type) {
592 case VGA_STD:
593 pci_vga_init(pci_bus);
594 return 1;
595 case VGA_NONE:
596 return 0;
597 default:
598 fprintf(stderr, "This vga model is not supported,"
599 "currently it only supports -vga std\n");
600 exit(0);
601 break;
602 }
603 }
604
605 /* pSeries LPAR / sPAPR hardware init */
606 static void ppc_spapr_init(ram_addr_t ram_size,
607 const char *boot_device,
608 const char *kernel_filename,
609 const char *kernel_cmdline,
610 const char *initrd_filename,
611 const char *cpu_model)
612 {
613 PowerPCCPU *cpu;
614 CPUPPCState *env;
615 int i;
616 MemoryRegion *sysmem = get_system_memory();
617 MemoryRegion *ram = g_new(MemoryRegion, 1);
618 target_phys_addr_t rma_alloc_size, rma_size;
619 uint32_t initrd_base = 0;
620 long kernel_size = 0, initrd_size = 0;
621 long load_limit, rtas_limit, fw_size;
622 long pteg_shift = 17;
623 char *filename;
624
625 msi_supported = true;
626
627 spapr = g_malloc0(sizeof(*spapr));
628 QLIST_INIT(&spapr->phbs);
629
630 cpu_ppc_hypercall = emulate_spapr_hypercall;
631
632 /* Allocate RMA if necessary */
633 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
634
635 if (rma_alloc_size == -1) {
636 hw_error("qemu: Unable to create RMA\n");
637 exit(1);
638 }
639 if (rma_alloc_size && (rma_alloc_size < ram_size)) {
640 rma_size = rma_alloc_size;
641 } else {
642 rma_size = ram_size;
643 }
644
645 /* We place the device tree and RTAS just below either the top of the RMA,
646 * or just below 2GB, whichever is lowere, so that it can be
647 * processed with 32-bit real mode code if necessary */
648 rtas_limit = MIN(rma_size, 0x80000000);
649 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
650 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
651 load_limit = spapr->fdt_addr - FW_OVERHEAD;
652
653 /* init CPUs */
654 if (cpu_model == NULL) {
655 cpu_model = kvm_enabled() ? "host" : "POWER7";
656 }
657 for (i = 0; i < smp_cpus; i++) {
658 cpu = cpu_ppc_init(cpu_model);
659 if (cpu == NULL) {
660 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
661 exit(1);
662 }
663 env = &cpu->env;
664
665 /* Set time-base frequency to 512 MHz */
666 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
667 qemu_register_reset(spapr_cpu_reset, cpu);
668
669 env->hreset_vector = 0x60;
670 env->hreset_excp_prefix = 0;
671 env->gpr[3] = env->cpu_index;
672 }
673
674 /* allocate RAM */
675 spapr->ram_limit = ram_size;
676 if (spapr->ram_limit > rma_alloc_size) {
677 ram_addr_t nonrma_base = rma_alloc_size;
678 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
679
680 memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
681 vmstate_register_ram_global(ram);
682 memory_region_add_subregion(sysmem, nonrma_base, ram);
683 }
684
685 /* allocate hash page table. For now we always make this 16mb,
686 * later we should probably make it scale to the size of guest
687 * RAM */
688 spapr->htab_size = 1ULL << (pteg_shift + 7);
689 spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size);
690
691 for (env = first_cpu; env != NULL; env = env->next_cpu) {
692 env->external_htab = spapr->htab;
693 env->htab_base = -1;
694 env->htab_mask = spapr->htab_size - 1;
695
696 /* Tell KVM that we're in PAPR mode */
697 env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
698 ((pteg_shift + 7) - 18);
699 env->spr[SPR_HIOR] = 0;
700
701 if (kvm_enabled()) {
702 kvmppc_set_papr(env);
703 }
704 }
705
706 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
707 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
708 rtas_limit - spapr->rtas_addr);
709 if (spapr->rtas_size < 0) {
710 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
711 exit(1);
712 }
713 if (spapr->rtas_size > RTAS_MAX_SIZE) {
714 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
715 spapr->rtas_size, RTAS_MAX_SIZE);
716 exit(1);
717 }
718 g_free(filename);
719
720
721 /* Set up Interrupt Controller */
722 spapr->icp = xics_system_init(XICS_IRQS);
723 spapr->next_irq = 16;
724
725 /* Set up IOMMU */
726 spapr_iommu_init();
727
728 /* Set up VIO bus */
729 spapr->vio_bus = spapr_vio_bus_init();
730
731 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
732 if (serial_hds[i]) {
733 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
734 }
735 }
736
737 /* Set up PCI */
738 spapr_pci_rtas_init();
739
740 spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
741 SPAPR_PCI_MEM_WIN_ADDR,
742 SPAPR_PCI_MEM_WIN_SIZE,
743 SPAPR_PCI_IO_WIN_ADDR,
744 SPAPR_PCI_MSI_WIN_ADDR);
745
746 for (i = 0; i < nb_nics; i++) {
747 NICInfo *nd = &nd_table[i];
748
749 if (!nd->model) {
750 nd->model = g_strdup("ibmveth");
751 }
752
753 if (strcmp(nd->model, "ibmveth") == 0) {
754 spapr_vlan_create(spapr->vio_bus, nd);
755 } else {
756 pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
757 }
758 }
759
760 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
761 spapr_vscsi_create(spapr->vio_bus);
762 }
763
764 /* Graphics */
765 if (spapr_vga_init(QLIST_FIRST(&spapr->phbs)->host_state.bus)) {
766 spapr->has_graphics = true;
767 }
768
769 if (usb_enabled) {
770 pci_create_simple(QLIST_FIRST(&spapr->phbs)->host_state.bus,
771 -1, "pci-ohci");
772 if (spapr->has_graphics) {
773 usbdevice_create("keyboard");
774 usbdevice_create("mouse");
775 }
776 }
777
778 if (rma_size < (MIN_RMA_SLOF << 20)) {
779 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
780 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
781 exit(1);
782 }
783
784 if (kernel_filename) {
785 uint64_t lowaddr = 0;
786
787 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
788 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
789 if (kernel_size < 0) {
790 kernel_size = load_image_targphys(kernel_filename,
791 KERNEL_LOAD_ADDR,
792 load_limit - KERNEL_LOAD_ADDR);
793 }
794 if (kernel_size < 0) {
795 fprintf(stderr, "qemu: could not load kernel '%s'\n",
796 kernel_filename);
797 exit(1);
798 }
799
800 /* load initrd */
801 if (initrd_filename) {
802 /* Try to locate the initrd in the gap between the kernel
803 * and the firmware. Add a bit of space just in case
804 */
805 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
806 initrd_size = load_image_targphys(initrd_filename, initrd_base,
807 load_limit - initrd_base);
808 if (initrd_size < 0) {
809 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
810 initrd_filename);
811 exit(1);
812 }
813 } else {
814 initrd_base = 0;
815 initrd_size = 0;
816 }
817 }
818
819 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
820 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
821 if (fw_size < 0) {
822 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
823 exit(1);
824 }
825 g_free(filename);
826
827 spapr->entry_point = 0x100;
828
829 /* SLOF will startup the secondary CPUs using RTAS */
830 for (env = first_cpu; env != NULL; env = env->next_cpu) {
831 env->halted = 1;
832 }
833
834 /* Prepare the device tree */
835 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, rma_size,
836 initrd_base, initrd_size,
837 kernel_size,
838 boot_device, kernel_cmdline,
839 pteg_shift + 7);
840 assert(spapr->fdt_skel != NULL);
841
842 qemu_register_reset(spapr_reset, spapr);
843 }
844
845 static QEMUMachine spapr_machine = {
846 .name = "pseries",
847 .desc = "pSeries Logical Partition (PAPR compliant)",
848 .init = ppc_spapr_init,
849 .max_cpus = MAX_CPUS,
850 .no_parallel = 1,
851 .use_scsi = 1,
852 };
853
854 static void spapr_machine_init(void)
855 {
856 qemu_register_machine(&spapr_machine);
857 }
858
859 machine_init(spapr_machine_init);