9 #define HPTES_PER_GROUP 8
11 #define HPTE_V_SSIZE_SHIFT 62
12 #define HPTE_V_AVPN_SHIFT 7
13 #define HPTE_V_AVPN 0x3fffffffffffff80ULL
14 #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
15 #define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
16 #define HPTE_V_BOLTED 0x0000000000000010ULL
17 #define HPTE_V_LOCK 0x0000000000000008ULL
18 #define HPTE_V_LARGE 0x0000000000000004ULL
19 #define HPTE_V_SECONDARY 0x0000000000000002ULL
20 #define HPTE_V_VALID 0x0000000000000001ULL
22 #define HPTE_R_PP0 0x8000000000000000ULL
23 #define HPTE_R_TS 0x4000000000000000ULL
24 #define HPTE_R_KEY_HI 0x3000000000000000ULL
25 #define HPTE_R_RPN_SHIFT 12
26 #define HPTE_R_RPN 0x3ffffffffffff000ULL
27 #define HPTE_R_FLAGS 0x00000000000003ffULL
28 #define HPTE_R_PP 0x0000000000000003ULL
29 #define HPTE_R_N 0x0000000000000004ULL
30 #define HPTE_R_G 0x0000000000000008ULL
31 #define HPTE_R_M 0x0000000000000010ULL
32 #define HPTE_R_I 0x0000000000000020ULL
33 #define HPTE_R_W 0x0000000000000040ULL
34 #define HPTE_R_WIMG 0x0000000000000078ULL
35 #define HPTE_R_C 0x0000000000000080ULL
36 #define HPTE_R_R 0x0000000000000100ULL
37 #define HPTE_R_KEY_LO 0x0000000000000e00ULL
39 #define HPTE_V_1TB_SEG 0x4000000000000000ULL
40 #define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL
42 #define HPTE_V_HVLOCK 0x40ULL
44 static inline int lock_hpte(void *hpte
, target_ulong bits
)
50 /* We're protected by qemu's global lock here */
54 stq_p(hpte
, pteh
| HPTE_V_HVLOCK
);
58 static target_ulong
compute_tlbie_rb(target_ulong v
, target_ulong r
,
59 target_ulong pte_index
)
61 target_ulong rb
, va_low
;
63 rb
= (v
& ~0x7fULL
) << 16; /* AVA field */
64 va_low
= pte_index
>> 3;
65 if (v
& HPTE_V_SECONDARY
) {
68 /* xor vsid from AVA */
69 if (!(v
& HPTE_V_1TB_SEG
)) {
75 if (v
& HPTE_V_LARGE
) {
76 rb
|= 1; /* L field */
77 #if 0 /* Disable that P7 specific bit for now */
79 /* non-16MB large page, must be 64k */
80 /* (masks depend on page size) */
81 rb
|= 0x1000; /* page encoding in LP field */
82 rb
|= (va_low
& 0x7f) << 16; /* 7b of VA in AVA/LP field */
83 rb
|= (va_low
& 0xfe); /* AVAL field */
88 rb
|= (va_low
& 0x7ff) << 12; /* remaining 11b of AVA */
90 rb
|= (v
>> 54) & 0x300; /* B field */
94 static target_ulong
h_enter(CPUState
*env
, sPAPREnvironment
*spapr
,
95 target_ulong opcode
, target_ulong
*args
)
97 target_ulong flags
= args
[0];
98 target_ulong pte_index
= args
[1];
99 target_ulong pteh
= args
[2];
100 target_ulong ptel
= args
[3];
105 /* only handle 4k and 16M pages for now */
107 if (pteh
& HPTE_V_LARGE
) {
108 #if 0 /* We don't support 64k pages yet */
109 if ((ptel
& 0xf000) == 0x1000) {
114 if ((ptel
& 0xff000) == 0) {
117 /* lowest AVA bit must be 0 for 16M pages */
126 pa
= ptel
& HPTE_R_RPN
;
127 /* FIXME: bounds check the pa? */
130 if ((ptel
& HPTE_R_WIMG
) != HPTE_R_M
) {
135 if ((pte_index
* HASH_PTE_SIZE_64
) & ~env
->htab_mask
) {
138 if (likely((flags
& H_EXACT
) == 0)) {
140 hpte
= env
->external_htab
+ (pte_index
* HASH_PTE_SIZE_64
);
145 if (((ldq_p(hpte
) & HPTE_V_VALID
) == 0) &&
146 lock_hpte(hpte
, HPTE_V_HVLOCK
| HPTE_V_VALID
)) {
149 hpte
+= HASH_PTE_SIZE_64
;
153 hpte
= env
->external_htab
+ (pte_index
* HASH_PTE_SIZE_64
);
154 if (!lock_hpte(hpte
, HPTE_V_HVLOCK
| HPTE_V_VALID
)) {
158 stq_p(hpte
+ (HASH_PTE_SIZE_64
/2), ptel
);
159 /* eieio(); FIXME: need some sort of barrier for smp? */
162 assert(!(ldq_p(hpte
) & HPTE_V_HVLOCK
));
163 args
[0] = pte_index
+ i
;
167 static target_ulong
h_remove(CPUState
*env
, sPAPREnvironment
*spapr
,
168 target_ulong opcode
, target_ulong
*args
)
170 target_ulong flags
= args
[0];
171 target_ulong pte_index
= args
[1];
172 target_ulong avpn
= args
[2];
174 target_ulong v
, r
, rb
;
176 if ((pte_index
* HASH_PTE_SIZE_64
) & ~env
->htab_mask
) {
180 hpte
= env
->external_htab
+ (pte_index
* HASH_PTE_SIZE_64
);
181 while (!lock_hpte(hpte
, HPTE_V_HVLOCK
)) {
182 /* We have no real concurrency in qemu soft-emulation, so we
183 * will never actually have a contested lock */
188 r
= ldq_p(hpte
+ (HASH_PTE_SIZE_64
/2));
190 if ((v
& HPTE_V_VALID
) == 0 ||
191 ((flags
& H_AVPN
) && (v
& ~0x7fULL
) != avpn
) ||
192 ((flags
& H_ANDCOND
) && (v
& avpn
) != 0)) {
193 stq_p(hpte
, v
& ~HPTE_V_HVLOCK
);
194 assert(!(ldq_p(hpte
) & HPTE_V_HVLOCK
));
197 args
[0] = v
& ~HPTE_V_HVLOCK
;
200 rb
= compute_tlbie_rb(v
, r
, pte_index
);
201 ppc_tlb_invalidate_one(env
, rb
);
202 assert(!(ldq_p(hpte
) & HPTE_V_HVLOCK
));
206 static target_ulong
h_protect(CPUState
*env
, sPAPREnvironment
*spapr
,
207 target_ulong opcode
, target_ulong
*args
)
209 target_ulong flags
= args
[0];
210 target_ulong pte_index
= args
[1];
211 target_ulong avpn
= args
[2];
213 target_ulong v
, r
, rb
;
215 if ((pte_index
* HASH_PTE_SIZE_64
) & ~env
->htab_mask
) {
219 hpte
= env
->external_htab
+ (pte_index
* HASH_PTE_SIZE_64
);
220 while (!lock_hpte(hpte
, HPTE_V_HVLOCK
)) {
221 /* We have no real concurrency in qemu soft-emulation, so we
222 * will never actually have a contested lock */
227 r
= ldq_p(hpte
+ (HASH_PTE_SIZE_64
/2));
229 if ((v
& HPTE_V_VALID
) == 0 ||
230 ((flags
& H_AVPN
) && (v
& ~0x7fULL
) != avpn
)) {
231 stq_p(hpte
, v
& ~HPTE_V_HVLOCK
);
232 assert(!(ldq_p(hpte
) & HPTE_V_HVLOCK
));
236 r
&= ~(HPTE_R_PP0
| HPTE_R_PP
| HPTE_R_N
|
237 HPTE_R_KEY_HI
| HPTE_R_KEY_LO
);
238 r
|= (flags
<< 55) & HPTE_R_PP0
;
239 r
|= (flags
<< 48) & HPTE_R_KEY_HI
;
240 r
|= flags
& (HPTE_R_PP
| HPTE_R_N
| HPTE_R_KEY_LO
);
241 rb
= compute_tlbie_rb(v
, r
, pte_index
);
242 stq_p(hpte
, v
& ~HPTE_V_VALID
);
243 ppc_tlb_invalidate_one(env
, rb
);
244 stq_p(hpte
+ (HASH_PTE_SIZE_64
/2), r
);
245 /* Don't need a memory barrier, due to qemu's global lock */
246 stq_p(hpte
, v
& ~HPTE_V_HVLOCK
);
247 assert(!(ldq_p(hpte
) & HPTE_V_HVLOCK
));
251 spapr_hcall_fn hypercall_table
[(MAX_HCALL_OPCODE
/ 4) + 1];
253 void spapr_register_hypercall(target_ulong opcode
, spapr_hcall_fn fn
)
255 spapr_hcall_fn old_fn
;
257 assert(opcode
<= MAX_HCALL_OPCODE
);
258 assert((opcode
& 0x3) == 0);
260 old_fn
= hypercall_table
[opcode
/ 4];
262 assert(!old_fn
|| (fn
== old_fn
));
264 hypercall_table
[opcode
/ 4] = fn
;
267 target_ulong
spapr_hypercall(CPUState
*env
, target_ulong opcode
,
271 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
275 if ((opcode
<= MAX_HCALL_OPCODE
)
276 && ((opcode
& 0x3) == 0)) {
277 spapr_hcall_fn fn
= hypercall_table
[opcode
/ 4];
280 return fn(env
, spapr
, opcode
, args
);
284 hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx
"\n", opcode
);
288 static void hypercall_init(void)
291 spapr_register_hypercall(H_ENTER
, h_enter
);
292 spapr_register_hypercall(H_REMOVE
, h_remove
);
293 spapr_register_hypercall(H_PROTECT
, h_protect
);
295 device_init(hypercall_init
);