2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sparc/sun4m.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/sparc/sparc32_dma.h"
29 #include "hw/block/fdc.h"
30 #include "sysemu/sysemu.h"
32 #include "hw/boards.h"
33 #include "hw/nvram/openbios_firmware_abi.h"
34 #include "hw/scsi/esp.h"
35 #include "hw/i386/pc.h"
36 #include "hw/isa/isa.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/char/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/loader.h"
42 #include "sysemu/blockdev.h"
46 * Sun4m architecture was used in the following machines:
48 * SPARCserver 6xxMP/xx
49 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
50 * SPARCclassic X (4/10)
51 * SPARCstation LX/ZX (4/30)
52 * SPARCstation Voyager
53 * SPARCstation 10/xx, SPARCserver 10/xx
54 * SPARCstation 5, SPARCserver 5
55 * SPARCstation 20/xx, SPARCserver 20
58 * See for example: http://www.sunhelp.org/faq/sunref1.html
61 #define KERNEL_LOAD_ADDR 0x00004000
62 #define CMDLINE_ADDR 0x007ff000
63 #define INITRD_LOAD_ADDR 0x00800000
64 #define PROM_SIZE_MAX (1024 * 1024)
65 #define PROM_VADDR 0xffd00000
66 #define PROM_FILENAME "openbios-sparc32"
67 #define CFG_ADDR 0xd00000510ULL
68 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
69 #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01)
70 #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02)
76 #define ESCC_CLOCK 4915200
79 hwaddr iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
80 hwaddr intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
81 hwaddr serial_base
, fd_base
;
82 hwaddr afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
83 hwaddr tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
84 hwaddr bpp_base
, dbri_base
, sx_base
;
86 hwaddr reg_base
, vram_base
;
90 const char * const default_cpu_model
;
92 uint32_t iommu_version
;
94 uint8_t nvram_machine_id
;
97 int DMA_get_channel_mode (int nchan
)
101 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
105 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
109 void DMA_hold_DREQ (int nchan
) {}
110 void DMA_release_DREQ (int nchan
) {}
111 void DMA_schedule(int nchan
) {}
113 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
117 void DMA_register_channel (int nchan
,
118 DMA_transfer_handler transfer_handler
,
123 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
125 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
129 static void nvram_init(M48t59State
*nvram
, uint8_t *macaddr
,
130 const char *cmdline
, const char *boot_devices
,
131 ram_addr_t RAM_size
, uint32_t kernel_size
,
132 int width
, int height
, int depth
,
133 int nvram_machine_id
, const char *arch
)
137 uint8_t image
[0x1ff0];
138 struct OpenBIOS_nvpart_v1
*part_header
;
140 memset(image
, '\0', sizeof(image
));
144 // OpenBIOS nvram variables
145 // Variable partition
146 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
147 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
148 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
150 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
151 for (i
= 0; i
< nb_prom_envs
; i
++)
152 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
157 end
= start
+ ((end
- start
+ 15) & ~15);
158 OpenBIOS_finish_partition(part_header
, end
- start
);
162 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
163 part_header
->signature
= OPENBIOS_PART_FREE
;
164 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
167 OpenBIOS_finish_partition(part_header
, end
- start
);
169 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
172 for (i
= 0; i
< sizeof(image
); i
++)
173 m48t59_write(nvram
, i
, image
[i
]);
176 static DeviceState
*slavio_intctl
;
178 void sun4m_pic_info(Monitor
*mon
, const QDict
*qdict
)
181 slavio_pic_info(mon
, slavio_intctl
);
184 void sun4m_irq_info(Monitor
*mon
, const QDict
*qdict
)
187 slavio_irq_info(mon
, slavio_intctl
);
190 void cpu_check_irqs(CPUSPARCState
*env
)
194 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
195 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
198 for (i
= 15; i
> 0; i
--) {
199 if (env
->pil_in
& (1 << i
)) {
200 int old_interrupt
= env
->interrupt_index
;
202 env
->interrupt_index
= TT_EXTINT
| i
;
203 if (old_interrupt
!= env
->interrupt_index
) {
204 cs
= CPU(sparc_env_get_cpu(env
));
205 trace_sun4m_cpu_interrupt(i
);
206 cpu_interrupt(cs
, CPU_INTERRUPT_HARD
);
211 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
212 cs
= CPU(sparc_env_get_cpu(env
));
213 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
214 env
->interrupt_index
= 0;
215 cpu_reset_interrupt(cs
, CPU_INTERRUPT_HARD
);
219 static void cpu_kick_irq(SPARCCPU
*cpu
)
221 CPUSPARCState
*env
= &cpu
->env
;
222 CPUState
*cs
= CPU(cpu
);
229 static void cpu_set_irq(void *opaque
, int irq
, int level
)
231 SPARCCPU
*cpu
= opaque
;
232 CPUSPARCState
*env
= &cpu
->env
;
235 trace_sun4m_cpu_set_irq_raise(irq
);
236 env
->pil_in
|= 1 << irq
;
239 trace_sun4m_cpu_set_irq_lower(irq
);
240 env
->pil_in
&= ~(1 << irq
);
245 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
249 static void main_cpu_reset(void *opaque
)
251 SPARCCPU
*cpu
= opaque
;
252 CPUState
*cs
= CPU(cpu
);
258 static void secondary_cpu_reset(void *opaque
)
260 SPARCCPU
*cpu
= opaque
;
261 CPUState
*cs
= CPU(cpu
);
267 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
269 if (level
&& current_cpu
) {
270 cpu_interrupt(current_cpu
, CPU_INTERRUPT_HALT
);
274 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
276 return addr
- 0xf0000000ULL
;
279 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
280 const char *initrd_filename
,
285 long initrd_size
, kernel_size
;
288 linux_boot
= (kernel_filename
!= NULL
);
299 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
300 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
302 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
303 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
306 kernel_size
= load_image_targphys(kernel_filename
,
308 RAM_size
- KERNEL_LOAD_ADDR
);
309 if (kernel_size
< 0) {
310 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
317 if (initrd_filename
) {
318 initrd_size
= load_image_targphys(initrd_filename
,
320 RAM_size
- INITRD_LOAD_ADDR
);
321 if (initrd_size
< 0) {
322 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
327 if (initrd_size
> 0) {
328 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
329 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
330 if (ldl_p(ptr
) == 0x48647253) { // HdrS
331 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
332 stl_p(ptr
+ 20, initrd_size
);
341 static void *iommu_init(hwaddr addr
, uint32_t version
, qemu_irq irq
)
346 dev
= qdev_create(NULL
, "iommu");
347 qdev_prop_set_uint32(dev
, "version", version
);
348 qdev_init_nofail(dev
);
349 s
= SYS_BUS_DEVICE(dev
);
350 sysbus_connect_irq(s
, 0, irq
);
351 sysbus_mmio_map(s
, 0, addr
);
356 static void *sparc32_dma_init(hwaddr daddr
, qemu_irq parent_irq
,
357 void *iommu
, qemu_irq
*dev_irq
, int is_ledma
)
362 dev
= qdev_create(NULL
, "sparc32_dma");
363 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
364 qdev_prop_set_uint32(dev
, "is_ledma", is_ledma
);
365 qdev_init_nofail(dev
);
366 s
= SYS_BUS_DEVICE(dev
);
367 sysbus_connect_irq(s
, 0, parent_irq
);
368 *dev_irq
= qdev_get_gpio_in(dev
, 0);
369 sysbus_mmio_map(s
, 0, daddr
);
374 static void lance_init(NICInfo
*nd
, hwaddr leaddr
,
375 void *dma_opaque
, qemu_irq irq
)
381 qemu_check_nic_model(&nd_table
[0], "lance");
383 dev
= qdev_create(NULL
, "lance");
384 qdev_set_nic_properties(dev
, nd
);
385 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
386 qdev_init_nofail(dev
);
387 s
= SYS_BUS_DEVICE(dev
);
388 sysbus_mmio_map(s
, 0, leaddr
);
389 sysbus_connect_irq(s
, 0, irq
);
390 reset
= qdev_get_gpio_in(dev
, 0);
391 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
394 static DeviceState
*slavio_intctl_init(hwaddr addr
,
396 qemu_irq
**parent_irq
)
402 dev
= qdev_create(NULL
, "slavio_intctl");
403 qdev_init_nofail(dev
);
405 s
= SYS_BUS_DEVICE(dev
);
407 for (i
= 0; i
< MAX_CPUS
; i
++) {
408 for (j
= 0; j
< MAX_PILS
; j
++) {
409 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
412 sysbus_mmio_map(s
, 0, addrg
);
413 for (i
= 0; i
< MAX_CPUS
; i
++) {
414 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
420 #define SYS_TIMER_OFFSET 0x10000ULL
421 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
423 static void slavio_timer_init_all(hwaddr addr
, qemu_irq master_irq
,
424 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
430 dev
= qdev_create(NULL
, "slavio_timer");
431 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
432 qdev_init_nofail(dev
);
433 s
= SYS_BUS_DEVICE(dev
);
434 sysbus_connect_irq(s
, 0, master_irq
);
435 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
437 for (i
= 0; i
< MAX_CPUS
; i
++) {
438 sysbus_mmio_map(s
, i
+ 1, addr
+ (hwaddr
)CPU_TIMER_OFFSET(i
));
439 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
443 static qemu_irq slavio_system_powerdown
;
445 static void slavio_powerdown_req(Notifier
*n
, void *opaque
)
447 qemu_irq_raise(slavio_system_powerdown
);
450 static Notifier slavio_system_powerdown_notifier
= {
451 .notify
= slavio_powerdown_req
454 #define MISC_LEDS 0x01600000
455 #define MISC_CFG 0x01800000
456 #define MISC_DIAG 0x01a00000
457 #define MISC_MDM 0x01b00000
458 #define MISC_SYS 0x01f00000
460 static void slavio_misc_init(hwaddr base
,
462 hwaddr aux2_base
, qemu_irq irq
,
468 dev
= qdev_create(NULL
, "slavio_misc");
469 qdev_init_nofail(dev
);
470 s
= SYS_BUS_DEVICE(dev
);
472 /* 8 bit registers */
474 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
476 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
478 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
479 /* 16 bit registers */
480 /* ss600mp diag LEDs */
481 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
482 /* 32 bit registers */
484 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
487 /* AUX 1 (Misc System Functions) */
488 sysbus_mmio_map(s
, 5, aux1_base
);
491 /* AUX 2 (Software Powerdown Control) */
492 sysbus_mmio_map(s
, 6, aux2_base
);
494 sysbus_connect_irq(s
, 0, irq
);
495 sysbus_connect_irq(s
, 1, fdc_tc
);
496 slavio_system_powerdown
= qdev_get_gpio_in(dev
, 0);
497 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier
);
500 static void ecc_init(hwaddr base
, qemu_irq irq
, uint32_t version
)
505 dev
= qdev_create(NULL
, "eccmemctl");
506 qdev_prop_set_uint32(dev
, "version", version
);
507 qdev_init_nofail(dev
);
508 s
= SYS_BUS_DEVICE(dev
);
509 sysbus_connect_irq(s
, 0, irq
);
510 sysbus_mmio_map(s
, 0, base
);
511 if (version
== 0) { // SS-600MP only
512 sysbus_mmio_map(s
, 1, base
+ 0x1000);
516 static void apc_init(hwaddr power_base
, qemu_irq cpu_halt
)
521 dev
= qdev_create(NULL
, "apc");
522 qdev_init_nofail(dev
);
523 s
= SYS_BUS_DEVICE(dev
);
524 /* Power management (APC) XXX: not a Slavio device */
525 sysbus_mmio_map(s
, 0, power_base
);
526 sysbus_connect_irq(s
, 0, cpu_halt
);
529 static void tcx_init(hwaddr addr
, int vram_size
, int width
,
530 int height
, int depth
)
535 dev
= qdev_create(NULL
, "SUNW,tcx");
536 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
537 qdev_prop_set_uint16(dev
, "width", width
);
538 qdev_prop_set_uint16(dev
, "height", height
);
539 qdev_prop_set_uint16(dev
, "depth", depth
);
540 qdev_init_nofail(dev
);
541 s
= SYS_BUS_DEVICE(dev
);
543 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
545 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
547 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
548 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
549 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
552 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
554 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
556 /* THC 8 bit (dummy) */
557 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
561 /* NCR89C100/MACIO Internal ID register */
562 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
564 static void idreg_init(hwaddr addr
)
569 dev
= qdev_create(NULL
, "macio_idreg");
570 qdev_init_nofail(dev
);
571 s
= SYS_BUS_DEVICE(dev
);
573 sysbus_mmio_map(s
, 0, addr
);
574 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
577 typedef struct IDRegState
{
582 static int idreg_init1(SysBusDevice
*dev
)
584 IDRegState
*s
= FROM_SYSBUS(IDRegState
, dev
);
586 memory_region_init_ram(&s
->mem
, OBJECT(s
),
587 "sun4m.idreg", sizeof(idreg_data
));
588 vmstate_register_ram_global(&s
->mem
);
589 memory_region_set_readonly(&s
->mem
, true);
590 sysbus_init_mmio(dev
, &s
->mem
);
594 static void idreg_class_init(ObjectClass
*klass
, void *data
)
596 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
598 k
->init
= idreg_init1
;
601 static const TypeInfo idreg_info
= {
602 .name
= "macio_idreg",
603 .parent
= TYPE_SYS_BUS_DEVICE
,
604 .instance_size
= sizeof(IDRegState
),
605 .class_init
= idreg_class_init
,
608 typedef struct AFXState
{
613 /* SS-5 TCX AFX register */
614 static void afx_init(hwaddr addr
)
619 dev
= qdev_create(NULL
, "tcx_afx");
620 qdev_init_nofail(dev
);
621 s
= SYS_BUS_DEVICE(dev
);
623 sysbus_mmio_map(s
, 0, addr
);
626 static int afx_init1(SysBusDevice
*dev
)
628 AFXState
*s
= FROM_SYSBUS(AFXState
, dev
);
630 memory_region_init_ram(&s
->mem
, OBJECT(s
), "sun4m.afx", 4);
631 vmstate_register_ram_global(&s
->mem
);
632 sysbus_init_mmio(dev
, &s
->mem
);
636 static void afx_class_init(ObjectClass
*klass
, void *data
)
638 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
643 static const TypeInfo afx_info
= {
645 .parent
= TYPE_SYS_BUS_DEVICE
,
646 .instance_size
= sizeof(AFXState
),
647 .class_init
= afx_class_init
,
650 typedef struct PROMState
{
655 /* Boot PROM (OpenBIOS) */
656 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
658 hwaddr
*base_addr
= (hwaddr
*)opaque
;
659 return addr
+ *base_addr
- PROM_VADDR
;
662 static void prom_init(hwaddr addr
, const char *bios_name
)
669 dev
= qdev_create(NULL
, "openprom");
670 qdev_init_nofail(dev
);
671 s
= SYS_BUS_DEVICE(dev
);
673 sysbus_mmio_map(s
, 0, addr
);
676 if (bios_name
== NULL
) {
677 bios_name
= PROM_FILENAME
;
679 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
681 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
682 NULL
, NULL
, 1, ELF_MACHINE
, 0);
683 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
684 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
690 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
691 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
696 static int prom_init1(SysBusDevice
*dev
)
698 PROMState
*s
= FROM_SYSBUS(PROMState
, dev
);
700 memory_region_init_ram(&s
->prom
, OBJECT(s
), "sun4m.prom", PROM_SIZE_MAX
);
701 vmstate_register_ram_global(&s
->prom
);
702 memory_region_set_readonly(&s
->prom
, true);
703 sysbus_init_mmio(dev
, &s
->prom
);
707 static Property prom_properties
[] = {
708 {/* end of property list */},
711 static void prom_class_init(ObjectClass
*klass
, void *data
)
713 DeviceClass
*dc
= DEVICE_CLASS(klass
);
714 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
716 k
->init
= prom_init1
;
717 dc
->props
= prom_properties
;
720 static const TypeInfo prom_info
= {
722 .parent
= TYPE_SYS_BUS_DEVICE
,
723 .instance_size
= sizeof(PROMState
),
724 .class_init
= prom_class_init
,
727 typedef struct RamDevice
735 static int ram_init1(SysBusDevice
*dev
)
737 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
739 memory_region_init_ram(&d
->ram
, OBJECT(d
), "sun4m.ram", d
->size
);
740 vmstate_register_ram_global(&d
->ram
);
741 sysbus_init_mmio(dev
, &d
->ram
);
745 static void ram_init(hwaddr addr
, ram_addr_t RAM_size
,
753 if ((uint64_t)RAM_size
> max_mem
) {
755 "qemu: Too much memory for this machine: %d, maximum %d\n",
756 (unsigned int)(RAM_size
/ (1024 * 1024)),
757 (unsigned int)(max_mem
/ (1024 * 1024)));
760 dev
= qdev_create(NULL
, "memory");
761 s
= SYS_BUS_DEVICE(dev
);
763 d
= FROM_SYSBUS(RamDevice
, s
);
765 qdev_init_nofail(dev
);
767 sysbus_mmio_map(s
, 0, addr
);
770 static Property ram_properties
[] = {
771 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
772 DEFINE_PROP_END_OF_LIST(),
775 static void ram_class_init(ObjectClass
*klass
, void *data
)
777 DeviceClass
*dc
= DEVICE_CLASS(klass
);
778 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
781 dc
->props
= ram_properties
;
784 static const TypeInfo ram_info
= {
786 .parent
= TYPE_SYS_BUS_DEVICE
,
787 .instance_size
= sizeof(RamDevice
),
788 .class_init
= ram_class_init
,
791 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
792 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
798 cpu
= cpu_sparc_init(cpu_model
);
800 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
805 cpu_sparc_set_id(env
, id
);
807 qemu_register_reset(main_cpu_reset
, cpu
);
809 qemu_register_reset(secondary_cpu_reset
, cpu
);
813 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, cpu
, MAX_PILS
);
814 env
->prom_addr
= prom_addr
;
817 static void dummy_fdc_tc(void *opaque
, int irq
, int level
)
821 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
822 const char *boot_device
,
823 const char *kernel_filename
,
824 const char *kernel_cmdline
,
825 const char *initrd_filename
, const char *cpu_model
)
828 void *iommu
, *espdma
, *ledma
, *nvram
;
829 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
830 espdma_irq
, ledma_irq
;
831 qemu_irq esp_reset
, dma_enable
;
834 unsigned long kernel_size
;
835 DriveInfo
*fd
[MAX_FD
];
837 unsigned int num_vsimms
;
841 cpu_model
= hwdef
->default_cpu_model
;
843 for(i
= 0; i
< smp_cpus
; i
++) {
844 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
847 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
848 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
852 ram_init(0, RAM_size
, hwdef
->max_mem
);
853 /* models without ECC don't trap when missing ram is accessed */
854 if (!hwdef
->ecc_base
) {
855 empty_slot_init(RAM_size
, hwdef
->max_mem
- RAM_size
);
858 prom_init(hwdef
->slavio_base
, bios_name
);
860 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
861 hwdef
->intctl_base
+ 0x10000ULL
,
864 for (i
= 0; i
< 32; i
++) {
865 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
867 for (i
= 0; i
< MAX_CPUS
; i
++) {
868 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
871 if (hwdef
->idreg_base
) {
872 idreg_init(hwdef
->idreg_base
);
875 if (hwdef
->afx_base
) {
876 afx_init(hwdef
->afx_base
);
879 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
882 if (hwdef
->iommu_pad_base
) {
883 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
884 Software shouldn't use aliased addresses, neither should it crash
885 when does. Using empty_slot instead of aliasing can help with
886 debugging such accesses */
887 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
890 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
891 iommu
, &espdma_irq
, 0);
893 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
894 slavio_irq
[16], iommu
, &ledma_irq
, 1);
896 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
897 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
901 if (num_vsimms
== 0) {
902 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
906 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
907 /* vsimm registers probed by OBP */
908 if (hwdef
->vsimm
[i
].reg_base
) {
909 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
913 if (hwdef
->sx_base
) {
914 empty_slot_init(hwdef
->sx_base
, 0x2000);
917 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
919 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
921 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
923 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
924 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
925 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
926 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
927 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
928 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
930 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
931 if (hwdef
->apc_base
) {
932 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
935 if (hwdef
->fd_base
) {
936 /* there is zero or one floppy drive */
937 memset(fd
, 0, sizeof(fd
));
938 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
939 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
942 fdc_tc
= *qemu_allocate_irqs(dummy_fdc_tc
, NULL
, 1);
945 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
946 slavio_irq
[30], fdc_tc
);
948 if (drive_get_max_bus(IF_SCSI
) > 0) {
949 fprintf(stderr
, "qemu: too many SCSI bus\n");
953 esp_init(hwdef
->esp_base
, 2,
954 espdma_memory_read
, espdma_memory_write
,
955 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
957 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
958 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
960 if (hwdef
->cs_base
) {
961 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
965 if (hwdef
->dbri_base
) {
966 /* ISDN chip with attached CS4215 audio codec */
968 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
970 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
973 if (hwdef
->bpp_base
) {
975 empty_slot_init(hwdef
->bpp_base
, 0x20);
978 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
981 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
982 boot_device
, RAM_size
, kernel_size
, graphic_width
,
983 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
987 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
990 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
991 fw_cfg_add_i16(fw_cfg
, FW_CFG_MAX_CPUS
, (uint16_t)max_cpus
);
992 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
993 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
994 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
995 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
996 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_WIDTH
, graphic_width
);
997 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_HEIGHT
, graphic_height
);
998 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
999 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1000 if (kernel_cmdline
) {
1001 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1002 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1003 fw_cfg_add_string(fw_cfg
, FW_CFG_CMDLINE_DATA
, kernel_cmdline
);
1004 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1005 strlen(kernel_cmdline
) + 1);
1007 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1008 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1010 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1011 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1012 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1013 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1028 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1031 .iommu_base
= 0x10000000,
1032 .iommu_pad_base
= 0x10004000,
1033 .iommu_pad_len
= 0x0fffb000,
1034 .tcx_base
= 0x50000000,
1035 .cs_base
= 0x6c000000,
1036 .slavio_base
= 0x70000000,
1037 .ms_kb_base
= 0x71000000,
1038 .serial_base
= 0x71100000,
1039 .nvram_base
= 0x71200000,
1040 .fd_base
= 0x71400000,
1041 .counter_base
= 0x71d00000,
1042 .intctl_base
= 0x71e00000,
1043 .idreg_base
= 0x78000000,
1044 .dma_base
= 0x78400000,
1045 .esp_base
= 0x78800000,
1046 .le_base
= 0x78c00000,
1047 .apc_base
= 0x6a000000,
1048 .afx_base
= 0x6e000000,
1049 .aux1_base
= 0x71900000,
1050 .aux2_base
= 0x71910000,
1051 .nvram_machine_id
= 0x80,
1052 .machine_id
= ss5_id
,
1053 .iommu_version
= 0x05000000,
1054 .max_mem
= 0x10000000,
1055 .default_cpu_model
= "Fujitsu MB86904",
1059 .iommu_base
= 0xfe0000000ULL
,
1060 .tcx_base
= 0xe20000000ULL
,
1061 .slavio_base
= 0xff0000000ULL
,
1062 .ms_kb_base
= 0xff1000000ULL
,
1063 .serial_base
= 0xff1100000ULL
,
1064 .nvram_base
= 0xff1200000ULL
,
1065 .fd_base
= 0xff1700000ULL
,
1066 .counter_base
= 0xff1300000ULL
,
1067 .intctl_base
= 0xff1400000ULL
,
1068 .idreg_base
= 0xef0000000ULL
,
1069 .dma_base
= 0xef0400000ULL
,
1070 .esp_base
= 0xef0800000ULL
,
1071 .le_base
= 0xef0c00000ULL
,
1072 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1073 .aux1_base
= 0xff1800000ULL
,
1074 .aux2_base
= 0xff1a01000ULL
,
1075 .ecc_base
= 0xf00000000ULL
,
1076 .ecc_version
= 0x10000000, // version 0, implementation 1
1077 .nvram_machine_id
= 0x72,
1078 .machine_id
= ss10_id
,
1079 .iommu_version
= 0x03000000,
1080 .max_mem
= 0xf00000000ULL
,
1081 .default_cpu_model
= "TI SuperSparc II",
1085 .iommu_base
= 0xfe0000000ULL
,
1086 .tcx_base
= 0xe20000000ULL
,
1087 .slavio_base
= 0xff0000000ULL
,
1088 .ms_kb_base
= 0xff1000000ULL
,
1089 .serial_base
= 0xff1100000ULL
,
1090 .nvram_base
= 0xff1200000ULL
,
1091 .counter_base
= 0xff1300000ULL
,
1092 .intctl_base
= 0xff1400000ULL
,
1093 .dma_base
= 0xef0081000ULL
,
1094 .esp_base
= 0xef0080000ULL
,
1095 .le_base
= 0xef0060000ULL
,
1096 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1097 .aux1_base
= 0xff1800000ULL
,
1098 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1099 .ecc_base
= 0xf00000000ULL
,
1100 .ecc_version
= 0x00000000, // version 0, implementation 0
1101 .nvram_machine_id
= 0x71,
1102 .machine_id
= ss600mp_id
,
1103 .iommu_version
= 0x01000000,
1104 .max_mem
= 0xf00000000ULL
,
1105 .default_cpu_model
= "TI SuperSparc II",
1109 .iommu_base
= 0xfe0000000ULL
,
1110 .tcx_base
= 0xe20000000ULL
,
1111 .slavio_base
= 0xff0000000ULL
,
1112 .ms_kb_base
= 0xff1000000ULL
,
1113 .serial_base
= 0xff1100000ULL
,
1114 .nvram_base
= 0xff1200000ULL
,
1115 .fd_base
= 0xff1700000ULL
,
1116 .counter_base
= 0xff1300000ULL
,
1117 .intctl_base
= 0xff1400000ULL
,
1118 .idreg_base
= 0xef0000000ULL
,
1119 .dma_base
= 0xef0400000ULL
,
1120 .esp_base
= 0xef0800000ULL
,
1121 .le_base
= 0xef0c00000ULL
,
1122 .bpp_base
= 0xef4800000ULL
,
1123 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1124 .aux1_base
= 0xff1800000ULL
,
1125 .aux2_base
= 0xff1a01000ULL
,
1126 .dbri_base
= 0xee0000000ULL
,
1127 .sx_base
= 0xf80000000ULL
,
1130 .reg_base
= 0x9c000000ULL
,
1131 .vram_base
= 0xfc000000ULL
1133 .reg_base
= 0x90000000ULL
,
1134 .vram_base
= 0xf0000000ULL
1136 .reg_base
= 0x94000000ULL
1138 .reg_base
= 0x98000000ULL
1141 .ecc_base
= 0xf00000000ULL
,
1142 .ecc_version
= 0x20000000, // version 0, implementation 2
1143 .nvram_machine_id
= 0x72,
1144 .machine_id
= ss20_id
,
1145 .iommu_version
= 0x13000000,
1146 .max_mem
= 0xf00000000ULL
,
1147 .default_cpu_model
= "TI SuperSparc II",
1151 .iommu_base
= 0x10000000,
1152 .tcx_base
= 0x50000000,
1153 .slavio_base
= 0x70000000,
1154 .ms_kb_base
= 0x71000000,
1155 .serial_base
= 0x71100000,
1156 .nvram_base
= 0x71200000,
1157 .fd_base
= 0x71400000,
1158 .counter_base
= 0x71d00000,
1159 .intctl_base
= 0x71e00000,
1160 .idreg_base
= 0x78000000,
1161 .dma_base
= 0x78400000,
1162 .esp_base
= 0x78800000,
1163 .le_base
= 0x78c00000,
1164 .apc_base
= 0x71300000, // pmc
1165 .aux1_base
= 0x71900000,
1166 .aux2_base
= 0x71910000,
1167 .nvram_machine_id
= 0x80,
1168 .machine_id
= vger_id
,
1169 .iommu_version
= 0x05000000,
1170 .max_mem
= 0x10000000,
1171 .default_cpu_model
= "Fujitsu MB86904",
1175 .iommu_base
= 0x10000000,
1176 .iommu_pad_base
= 0x10004000,
1177 .iommu_pad_len
= 0x0fffb000,
1178 .tcx_base
= 0x50000000,
1179 .slavio_base
= 0x70000000,
1180 .ms_kb_base
= 0x71000000,
1181 .serial_base
= 0x71100000,
1182 .nvram_base
= 0x71200000,
1183 .fd_base
= 0x71400000,
1184 .counter_base
= 0x71d00000,
1185 .intctl_base
= 0x71e00000,
1186 .idreg_base
= 0x78000000,
1187 .dma_base
= 0x78400000,
1188 .esp_base
= 0x78800000,
1189 .le_base
= 0x78c00000,
1190 .aux1_base
= 0x71900000,
1191 .aux2_base
= 0x71910000,
1192 .nvram_machine_id
= 0x80,
1193 .machine_id
= lx_id
,
1194 .iommu_version
= 0x04000000,
1195 .max_mem
= 0x10000000,
1196 .default_cpu_model
= "TI MicroSparc I",
1200 .iommu_base
= 0x10000000,
1201 .tcx_base
= 0x50000000,
1202 .cs_base
= 0x6c000000,
1203 .slavio_base
= 0x70000000,
1204 .ms_kb_base
= 0x71000000,
1205 .serial_base
= 0x71100000,
1206 .nvram_base
= 0x71200000,
1207 .fd_base
= 0x71400000,
1208 .counter_base
= 0x71d00000,
1209 .intctl_base
= 0x71e00000,
1210 .idreg_base
= 0x78000000,
1211 .dma_base
= 0x78400000,
1212 .esp_base
= 0x78800000,
1213 .le_base
= 0x78c00000,
1214 .apc_base
= 0x6a000000,
1215 .aux1_base
= 0x71900000,
1216 .aux2_base
= 0x71910000,
1217 .nvram_machine_id
= 0x80,
1218 .machine_id
= ss4_id
,
1219 .iommu_version
= 0x05000000,
1220 .max_mem
= 0x10000000,
1221 .default_cpu_model
= "Fujitsu MB86904",
1225 .iommu_base
= 0x10000000,
1226 .tcx_base
= 0x50000000,
1227 .slavio_base
= 0x70000000,
1228 .ms_kb_base
= 0x71000000,
1229 .serial_base
= 0x71100000,
1230 .nvram_base
= 0x71200000,
1231 .fd_base
= 0x71400000,
1232 .counter_base
= 0x71d00000,
1233 .intctl_base
= 0x71e00000,
1234 .idreg_base
= 0x78000000,
1235 .dma_base
= 0x78400000,
1236 .esp_base
= 0x78800000,
1237 .le_base
= 0x78c00000,
1238 .apc_base
= 0x6a000000,
1239 .aux1_base
= 0x71900000,
1240 .aux2_base
= 0x71910000,
1241 .nvram_machine_id
= 0x80,
1242 .machine_id
= scls_id
,
1243 .iommu_version
= 0x05000000,
1244 .max_mem
= 0x10000000,
1245 .default_cpu_model
= "TI MicroSparc I",
1249 .iommu_base
= 0x10000000,
1250 .tcx_base
= 0x50000000, // XXX
1251 .slavio_base
= 0x70000000,
1252 .ms_kb_base
= 0x71000000,
1253 .serial_base
= 0x71100000,
1254 .nvram_base
= 0x71200000,
1255 .fd_base
= 0x71400000,
1256 .counter_base
= 0x71d00000,
1257 .intctl_base
= 0x71e00000,
1258 .idreg_base
= 0x78000000,
1259 .dma_base
= 0x78400000,
1260 .esp_base
= 0x78800000,
1261 .le_base
= 0x78c00000,
1262 .apc_base
= 0x6a000000,
1263 .aux1_base
= 0x71900000,
1264 .aux2_base
= 0x71910000,
1265 .nvram_machine_id
= 0x80,
1266 .machine_id
= sbook_id
,
1267 .iommu_version
= 0x05000000,
1268 .max_mem
= 0x10000000,
1269 .default_cpu_model
= "TI MicroSparc I",
1273 /* SPARCstation 5 hardware initialisation */
1274 static void ss5_init(QEMUMachineInitArgs
*args
)
1276 ram_addr_t RAM_size
= args
->ram_size
;
1277 const char *cpu_model
= args
->cpu_model
;
1278 const char *kernel_filename
= args
->kernel_filename
;
1279 const char *kernel_cmdline
= args
->kernel_cmdline
;
1280 const char *initrd_filename
= args
->initrd_filename
;
1281 const char *boot_device
= args
->boot_device
;
1282 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1283 kernel_cmdline
, initrd_filename
, cpu_model
);
1286 /* SPARCstation 10 hardware initialisation */
1287 static void ss10_init(QEMUMachineInitArgs
*args
)
1289 ram_addr_t RAM_size
= args
->ram_size
;
1290 const char *cpu_model
= args
->cpu_model
;
1291 const char *kernel_filename
= args
->kernel_filename
;
1292 const char *kernel_cmdline
= args
->kernel_cmdline
;
1293 const char *initrd_filename
= args
->initrd_filename
;
1294 const char *boot_device
= args
->boot_device
;
1295 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1296 kernel_cmdline
, initrd_filename
, cpu_model
);
1299 /* SPARCserver 600MP hardware initialisation */
1300 static void ss600mp_init(QEMUMachineInitArgs
*args
)
1302 ram_addr_t RAM_size
= args
->ram_size
;
1303 const char *cpu_model
= args
->cpu_model
;
1304 const char *kernel_filename
= args
->kernel_filename
;
1305 const char *kernel_cmdline
= args
->kernel_cmdline
;
1306 const char *initrd_filename
= args
->initrd_filename
;
1307 const char *boot_device
= args
->boot_device
;
1308 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1309 kernel_cmdline
, initrd_filename
, cpu_model
);
1312 /* SPARCstation 20 hardware initialisation */
1313 static void ss20_init(QEMUMachineInitArgs
*args
)
1315 ram_addr_t RAM_size
= args
->ram_size
;
1316 const char *cpu_model
= args
->cpu_model
;
1317 const char *kernel_filename
= args
->kernel_filename
;
1318 const char *kernel_cmdline
= args
->kernel_cmdline
;
1319 const char *initrd_filename
= args
->initrd_filename
;
1320 const char *boot_device
= args
->boot_device
;
1321 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1322 kernel_cmdline
, initrd_filename
, cpu_model
);
1325 /* SPARCstation Voyager hardware initialisation */
1326 static void vger_init(QEMUMachineInitArgs
*args
)
1328 ram_addr_t RAM_size
= args
->ram_size
;
1329 const char *cpu_model
= args
->cpu_model
;
1330 const char *kernel_filename
= args
->kernel_filename
;
1331 const char *kernel_cmdline
= args
->kernel_cmdline
;
1332 const char *initrd_filename
= args
->initrd_filename
;
1333 const char *boot_device
= args
->boot_device
;
1334 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1335 kernel_cmdline
, initrd_filename
, cpu_model
);
1338 /* SPARCstation LX hardware initialisation */
1339 static void ss_lx_init(QEMUMachineInitArgs
*args
)
1341 ram_addr_t RAM_size
= args
->ram_size
;
1342 const char *cpu_model
= args
->cpu_model
;
1343 const char *kernel_filename
= args
->kernel_filename
;
1344 const char *kernel_cmdline
= args
->kernel_cmdline
;
1345 const char *initrd_filename
= args
->initrd_filename
;
1346 const char *boot_device
= args
->boot_device
;
1347 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1348 kernel_cmdline
, initrd_filename
, cpu_model
);
1351 /* SPARCstation 4 hardware initialisation */
1352 static void ss4_init(QEMUMachineInitArgs
*args
)
1354 ram_addr_t RAM_size
= args
->ram_size
;
1355 const char *cpu_model
= args
->cpu_model
;
1356 const char *kernel_filename
= args
->kernel_filename
;
1357 const char *kernel_cmdline
= args
->kernel_cmdline
;
1358 const char *initrd_filename
= args
->initrd_filename
;
1359 const char *boot_device
= args
->boot_device
;
1360 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1361 kernel_cmdline
, initrd_filename
, cpu_model
);
1364 /* SPARCClassic hardware initialisation */
1365 static void scls_init(QEMUMachineInitArgs
*args
)
1367 ram_addr_t RAM_size
= args
->ram_size
;
1368 const char *cpu_model
= args
->cpu_model
;
1369 const char *kernel_filename
= args
->kernel_filename
;
1370 const char *kernel_cmdline
= args
->kernel_cmdline
;
1371 const char *initrd_filename
= args
->initrd_filename
;
1372 const char *boot_device
= args
->boot_device
;
1373 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1374 kernel_cmdline
, initrd_filename
, cpu_model
);
1377 /* SPARCbook hardware initialisation */
1378 static void sbook_init(QEMUMachineInitArgs
*args
)
1380 ram_addr_t RAM_size
= args
->ram_size
;
1381 const char *cpu_model
= args
->cpu_model
;
1382 const char *kernel_filename
= args
->kernel_filename
;
1383 const char *kernel_cmdline
= args
->kernel_cmdline
;
1384 const char *initrd_filename
= args
->initrd_filename
;
1385 const char *boot_device
= args
->boot_device
;
1386 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1387 kernel_cmdline
, initrd_filename
, cpu_model
);
1390 static QEMUMachine ss5_machine
= {
1392 .desc
= "Sun4m platform, SPARCstation 5",
1394 .block_default_type
= IF_SCSI
,
1396 DEFAULT_MACHINE_OPTIONS
,
1399 static QEMUMachine ss10_machine
= {
1401 .desc
= "Sun4m platform, SPARCstation 10",
1403 .block_default_type
= IF_SCSI
,
1405 DEFAULT_MACHINE_OPTIONS
,
1408 static QEMUMachine ss600mp_machine
= {
1410 .desc
= "Sun4m platform, SPARCserver 600MP",
1411 .init
= ss600mp_init
,
1412 .block_default_type
= IF_SCSI
,
1414 DEFAULT_MACHINE_OPTIONS
,
1417 static QEMUMachine ss20_machine
= {
1419 .desc
= "Sun4m platform, SPARCstation 20",
1421 .block_default_type
= IF_SCSI
,
1423 DEFAULT_MACHINE_OPTIONS
,
1426 static QEMUMachine voyager_machine
= {
1428 .desc
= "Sun4m platform, SPARCstation Voyager",
1430 .block_default_type
= IF_SCSI
,
1431 DEFAULT_MACHINE_OPTIONS
,
1434 static QEMUMachine ss_lx_machine
= {
1436 .desc
= "Sun4m platform, SPARCstation LX",
1438 .block_default_type
= IF_SCSI
,
1439 DEFAULT_MACHINE_OPTIONS
,
1442 static QEMUMachine ss4_machine
= {
1444 .desc
= "Sun4m platform, SPARCstation 4",
1446 .block_default_type
= IF_SCSI
,
1447 DEFAULT_MACHINE_OPTIONS
,
1450 static QEMUMachine scls_machine
= {
1451 .name
= "SPARCClassic",
1452 .desc
= "Sun4m platform, SPARCClassic",
1454 .block_default_type
= IF_SCSI
,
1455 DEFAULT_MACHINE_OPTIONS
,
1458 static QEMUMachine sbook_machine
= {
1459 .name
= "SPARCbook",
1460 .desc
= "Sun4m platform, SPARCbook",
1462 .block_default_type
= IF_SCSI
,
1463 DEFAULT_MACHINE_OPTIONS
,
1466 static void sun4m_register_types(void)
1468 type_register_static(&idreg_info
);
1469 type_register_static(&afx_info
);
1470 type_register_static(&prom_info
);
1471 type_register_static(&ram_info
);
1474 static void sun4m_machine_init(void)
1476 qemu_register_machine(&ss5_machine
);
1477 qemu_register_machine(&ss10_machine
);
1478 qemu_register_machine(&ss600mp_machine
);
1479 qemu_register_machine(&ss20_machine
);
1480 qemu_register_machine(&voyager_machine
);
1481 qemu_register_machine(&ss_lx_machine
);
1482 qemu_register_machine(&ss4_machine
);
1483 qemu_register_machine(&scls_machine
);
1484 qemu_register_machine(&sbook_machine
);
1487 type_init(sun4m_register_types
)
1488 machine_init(sun4m_machine_init
);