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cpu: Move halted and interrupt_request fields to CPUState
[qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sun4m.h"
27 #include "hw/nvram.h"
28 #include "hw/sparc32_dma.h"
29 #include "hw/fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/firmware_abi.h"
34 #include "hw/esp.h"
35 #include "hw/pc.h"
36 #include "hw/isa.h"
37 #include "hw/fw_cfg.h"
38 #include "hw/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/qdev-addr.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "sysemu/blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
92 hwaddr serial_base, fd_base;
93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 hwaddr bpp_base, dbri_base, sx_base;
96 struct {
97 hwaddr reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 hwaddr ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
112 hwaddr counter_base, nvram_base, ms_kb_base;
113 hwaddr serial_base;
114 hwaddr espdma_base, esp_base;
115 hwaddr ledma_base, le_base;
116 hwaddr tcx_base;
117 hwaddr sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 hwaddr iommu_base, slavio_base;
127 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
128 hwaddr serial_base, fd_base;
129 hwaddr idreg_base, dma_base, esp_base, le_base;
130 hwaddr tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(SPARCCPU *cpu)
257 {
258 CPUSPARCState *env = &cpu->env;
259 CPUState *cs = CPU(cpu);
260
261 cs->halted = 0;
262 cpu_check_irqs(env);
263 qemu_cpu_kick(cs);
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 SPARCCPU *cpu = opaque;
269 CPUSPARCState *env = &cpu->env;
270
271 if (level) {
272 trace_sun4m_cpu_set_irq_raise(irq);
273 env->pil_in |= 1 << irq;
274 cpu_kick_irq(cpu);
275 } else {
276 trace_sun4m_cpu_set_irq_lower(irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void main_cpu_reset(void *opaque)
287 {
288 SPARCCPU *cpu = opaque;
289 CPUState *cs = CPU(cpu);
290
291 cpu_reset(cs);
292 cs->halted = 0;
293 }
294
295 static void secondary_cpu_reset(void *opaque)
296 {
297 SPARCCPU *cpu = opaque;
298 CPUState *cs = CPU(cpu);
299
300 cpu_reset(cs);
301 cs->halted = 1;
302 }
303
304 static void cpu_halt_signal(void *opaque, int irq, int level)
305 {
306 if (level && cpu_single_env)
307 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
308 }
309
310 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
311 {
312 return addr - 0xf0000000ULL;
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322 uint8_t *ptr;
323
324 linux_boot = (kernel_filename != NULL);
325
326 kernel_size = 0;
327 if (linux_boot) {
328 int bswap_needed;
329
330 #ifdef BSWAP_NEEDED
331 bswap_needed = 1;
332 #else
333 bswap_needed = 0;
334 #endif
335 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
336 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
337 if (kernel_size < 0)
338 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
339 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
340 TARGET_PAGE_SIZE);
341 if (kernel_size < 0)
342 kernel_size = load_image_targphys(kernel_filename,
343 KERNEL_LOAD_ADDR,
344 RAM_size - KERNEL_LOAD_ADDR);
345 if (kernel_size < 0) {
346 fprintf(stderr, "qemu: could not load kernel '%s'\n",
347 kernel_filename);
348 exit(1);
349 }
350
351 /* load initrd */
352 initrd_size = 0;
353 if (initrd_filename) {
354 initrd_size = load_image_targphys(initrd_filename,
355 INITRD_LOAD_ADDR,
356 RAM_size - INITRD_LOAD_ADDR);
357 if (initrd_size < 0) {
358 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
359 initrd_filename);
360 exit(1);
361 }
362 }
363 if (initrd_size > 0) {
364 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
365 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
366 if (ldl_p(ptr) == 0x48647253) { // HdrS
367 stl_p(ptr + 16, INITRD_LOAD_ADDR);
368 stl_p(ptr + 20, initrd_size);
369 break;
370 }
371 }
372 }
373 }
374 return kernel_size;
375 }
376
377 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
378 {
379 DeviceState *dev;
380 SysBusDevice *s;
381
382 dev = qdev_create(NULL, "iommu");
383 qdev_prop_set_uint32(dev, "version", version);
384 qdev_init_nofail(dev);
385 s = SYS_BUS_DEVICE(dev);
386 sysbus_connect_irq(s, 0, irq);
387 sysbus_mmio_map(s, 0, addr);
388
389 return s;
390 }
391
392 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
393 void *iommu, qemu_irq *dev_irq, int is_ledma)
394 {
395 DeviceState *dev;
396 SysBusDevice *s;
397
398 dev = qdev_create(NULL, "sparc32_dma");
399 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
400 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
401 qdev_init_nofail(dev);
402 s = SYS_BUS_DEVICE(dev);
403 sysbus_connect_irq(s, 0, parent_irq);
404 *dev_irq = qdev_get_gpio_in(dev, 0);
405 sysbus_mmio_map(s, 0, daddr);
406
407 return s;
408 }
409
410 static void lance_init(NICInfo *nd, hwaddr leaddr,
411 void *dma_opaque, qemu_irq irq)
412 {
413 DeviceState *dev;
414 SysBusDevice *s;
415 qemu_irq reset;
416
417 qemu_check_nic_model(&nd_table[0], "lance");
418
419 dev = qdev_create(NULL, "lance");
420 qdev_set_nic_properties(dev, nd);
421 qdev_prop_set_ptr(dev, "dma", dma_opaque);
422 qdev_init_nofail(dev);
423 s = SYS_BUS_DEVICE(dev);
424 sysbus_mmio_map(s, 0, leaddr);
425 sysbus_connect_irq(s, 0, irq);
426 reset = qdev_get_gpio_in(dev, 0);
427 qdev_connect_gpio_out(dma_opaque, 0, reset);
428 }
429
430 static DeviceState *slavio_intctl_init(hwaddr addr,
431 hwaddr addrg,
432 qemu_irq **parent_irq)
433 {
434 DeviceState *dev;
435 SysBusDevice *s;
436 unsigned int i, j;
437
438 dev = qdev_create(NULL, "slavio_intctl");
439 qdev_init_nofail(dev);
440
441 s = SYS_BUS_DEVICE(dev);
442
443 for (i = 0; i < MAX_CPUS; i++) {
444 for (j = 0; j < MAX_PILS; j++) {
445 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
446 }
447 }
448 sysbus_mmio_map(s, 0, addrg);
449 for (i = 0; i < MAX_CPUS; i++) {
450 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
451 }
452
453 return dev;
454 }
455
456 #define SYS_TIMER_OFFSET 0x10000ULL
457 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
458
459 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
460 qemu_irq *cpu_irqs, unsigned int num_cpus)
461 {
462 DeviceState *dev;
463 SysBusDevice *s;
464 unsigned int i;
465
466 dev = qdev_create(NULL, "slavio_timer");
467 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
468 qdev_init_nofail(dev);
469 s = SYS_BUS_DEVICE(dev);
470 sysbus_connect_irq(s, 0, master_irq);
471 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
472
473 for (i = 0; i < MAX_CPUS; i++) {
474 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
475 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
476 }
477 }
478
479 static qemu_irq slavio_system_powerdown;
480
481 static void slavio_powerdown_req(Notifier *n, void *opaque)
482 {
483 qemu_irq_raise(slavio_system_powerdown);
484 }
485
486 static Notifier slavio_system_powerdown_notifier = {
487 .notify = slavio_powerdown_req
488 };
489
490 #define MISC_LEDS 0x01600000
491 #define MISC_CFG 0x01800000
492 #define MISC_DIAG 0x01a00000
493 #define MISC_MDM 0x01b00000
494 #define MISC_SYS 0x01f00000
495
496 static void slavio_misc_init(hwaddr base,
497 hwaddr aux1_base,
498 hwaddr aux2_base, qemu_irq irq,
499 qemu_irq fdc_tc)
500 {
501 DeviceState *dev;
502 SysBusDevice *s;
503
504 dev = qdev_create(NULL, "slavio_misc");
505 qdev_init_nofail(dev);
506 s = SYS_BUS_DEVICE(dev);
507 if (base) {
508 /* 8 bit registers */
509 /* Slavio control */
510 sysbus_mmio_map(s, 0, base + MISC_CFG);
511 /* Diagnostics */
512 sysbus_mmio_map(s, 1, base + MISC_DIAG);
513 /* Modem control */
514 sysbus_mmio_map(s, 2, base + MISC_MDM);
515 /* 16 bit registers */
516 /* ss600mp diag LEDs */
517 sysbus_mmio_map(s, 3, base + MISC_LEDS);
518 /* 32 bit registers */
519 /* System control */
520 sysbus_mmio_map(s, 4, base + MISC_SYS);
521 }
522 if (aux1_base) {
523 /* AUX 1 (Misc System Functions) */
524 sysbus_mmio_map(s, 5, aux1_base);
525 }
526 if (aux2_base) {
527 /* AUX 2 (Software Powerdown Control) */
528 sysbus_mmio_map(s, 6, aux2_base);
529 }
530 sysbus_connect_irq(s, 0, irq);
531 sysbus_connect_irq(s, 1, fdc_tc);
532 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
533 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
534 }
535
536 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
537 {
538 DeviceState *dev;
539 SysBusDevice *s;
540
541 dev = qdev_create(NULL, "eccmemctl");
542 qdev_prop_set_uint32(dev, "version", version);
543 qdev_init_nofail(dev);
544 s = SYS_BUS_DEVICE(dev);
545 sysbus_connect_irq(s, 0, irq);
546 sysbus_mmio_map(s, 0, base);
547 if (version == 0) { // SS-600MP only
548 sysbus_mmio_map(s, 1, base + 0x1000);
549 }
550 }
551
552 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
553 {
554 DeviceState *dev;
555 SysBusDevice *s;
556
557 dev = qdev_create(NULL, "apc");
558 qdev_init_nofail(dev);
559 s = SYS_BUS_DEVICE(dev);
560 /* Power management (APC) XXX: not a Slavio device */
561 sysbus_mmio_map(s, 0, power_base);
562 sysbus_connect_irq(s, 0, cpu_halt);
563 }
564
565 static void tcx_init(hwaddr addr, int vram_size, int width,
566 int height, int depth)
567 {
568 DeviceState *dev;
569 SysBusDevice *s;
570
571 dev = qdev_create(NULL, "SUNW,tcx");
572 qdev_prop_set_taddr(dev, "addr", addr);
573 qdev_prop_set_uint32(dev, "vram_size", vram_size);
574 qdev_prop_set_uint16(dev, "width", width);
575 qdev_prop_set_uint16(dev, "height", height);
576 qdev_prop_set_uint16(dev, "depth", depth);
577 qdev_init_nofail(dev);
578 s = SYS_BUS_DEVICE(dev);
579 /* 8-bit plane */
580 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
581 /* DAC */
582 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
583 /* TEC (dummy) */
584 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
585 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
586 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
587 if (depth == 24) {
588 /* 24-bit plane */
589 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
590 /* Control plane */
591 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
592 } else {
593 /* THC 8 bit (dummy) */
594 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
595 }
596 }
597
598 /* NCR89C100/MACIO Internal ID register */
599 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
600
601 static void idreg_init(hwaddr addr)
602 {
603 DeviceState *dev;
604 SysBusDevice *s;
605
606 dev = qdev_create(NULL, "macio_idreg");
607 qdev_init_nofail(dev);
608 s = SYS_BUS_DEVICE(dev);
609
610 sysbus_mmio_map(s, 0, addr);
611 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
612 }
613
614 typedef struct IDRegState {
615 SysBusDevice busdev;
616 MemoryRegion mem;
617 } IDRegState;
618
619 static int idreg_init1(SysBusDevice *dev)
620 {
621 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
622
623 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
624 vmstate_register_ram_global(&s->mem);
625 memory_region_set_readonly(&s->mem, true);
626 sysbus_init_mmio(dev, &s->mem);
627 return 0;
628 }
629
630 static void idreg_class_init(ObjectClass *klass, void *data)
631 {
632 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
633
634 k->init = idreg_init1;
635 }
636
637 static const TypeInfo idreg_info = {
638 .name = "macio_idreg",
639 .parent = TYPE_SYS_BUS_DEVICE,
640 .instance_size = sizeof(IDRegState),
641 .class_init = idreg_class_init,
642 };
643
644 typedef struct AFXState {
645 SysBusDevice busdev;
646 MemoryRegion mem;
647 } AFXState;
648
649 /* SS-5 TCX AFX register */
650 static void afx_init(hwaddr addr)
651 {
652 DeviceState *dev;
653 SysBusDevice *s;
654
655 dev = qdev_create(NULL, "tcx_afx");
656 qdev_init_nofail(dev);
657 s = SYS_BUS_DEVICE(dev);
658
659 sysbus_mmio_map(s, 0, addr);
660 }
661
662 static int afx_init1(SysBusDevice *dev)
663 {
664 AFXState *s = FROM_SYSBUS(AFXState, dev);
665
666 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
667 vmstate_register_ram_global(&s->mem);
668 sysbus_init_mmio(dev, &s->mem);
669 return 0;
670 }
671
672 static void afx_class_init(ObjectClass *klass, void *data)
673 {
674 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
675
676 k->init = afx_init1;
677 }
678
679 static const TypeInfo afx_info = {
680 .name = "tcx_afx",
681 .parent = TYPE_SYS_BUS_DEVICE,
682 .instance_size = sizeof(AFXState),
683 .class_init = afx_class_init,
684 };
685
686 typedef struct PROMState {
687 SysBusDevice busdev;
688 MemoryRegion prom;
689 } PROMState;
690
691 /* Boot PROM (OpenBIOS) */
692 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
693 {
694 hwaddr *base_addr = (hwaddr *)opaque;
695 return addr + *base_addr - PROM_VADDR;
696 }
697
698 static void prom_init(hwaddr addr, const char *bios_name)
699 {
700 DeviceState *dev;
701 SysBusDevice *s;
702 char *filename;
703 int ret;
704
705 dev = qdev_create(NULL, "openprom");
706 qdev_init_nofail(dev);
707 s = SYS_BUS_DEVICE(dev);
708
709 sysbus_mmio_map(s, 0, addr);
710
711 /* load boot prom */
712 if (bios_name == NULL) {
713 bios_name = PROM_FILENAME;
714 }
715 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
716 if (filename) {
717 ret = load_elf(filename, translate_prom_address, &addr, NULL,
718 NULL, NULL, 1, ELF_MACHINE, 0);
719 if (ret < 0 || ret > PROM_SIZE_MAX) {
720 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
721 }
722 g_free(filename);
723 } else {
724 ret = -1;
725 }
726 if (ret < 0 || ret > PROM_SIZE_MAX) {
727 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
728 exit(1);
729 }
730 }
731
732 static int prom_init1(SysBusDevice *dev)
733 {
734 PROMState *s = FROM_SYSBUS(PROMState, dev);
735
736 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
737 vmstate_register_ram_global(&s->prom);
738 memory_region_set_readonly(&s->prom, true);
739 sysbus_init_mmio(dev, &s->prom);
740 return 0;
741 }
742
743 static Property prom_properties[] = {
744 {/* end of property list */},
745 };
746
747 static void prom_class_init(ObjectClass *klass, void *data)
748 {
749 DeviceClass *dc = DEVICE_CLASS(klass);
750 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
751
752 k->init = prom_init1;
753 dc->props = prom_properties;
754 }
755
756 static const TypeInfo prom_info = {
757 .name = "openprom",
758 .parent = TYPE_SYS_BUS_DEVICE,
759 .instance_size = sizeof(PROMState),
760 .class_init = prom_class_init,
761 };
762
763 typedef struct RamDevice
764 {
765 SysBusDevice busdev;
766 MemoryRegion ram;
767 uint64_t size;
768 } RamDevice;
769
770 /* System RAM */
771 static int ram_init1(SysBusDevice *dev)
772 {
773 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
774
775 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
776 vmstate_register_ram_global(&d->ram);
777 sysbus_init_mmio(dev, &d->ram);
778 return 0;
779 }
780
781 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
782 uint64_t max_mem)
783 {
784 DeviceState *dev;
785 SysBusDevice *s;
786 RamDevice *d;
787
788 /* allocate RAM */
789 if ((uint64_t)RAM_size > max_mem) {
790 fprintf(stderr,
791 "qemu: Too much memory for this machine: %d, maximum %d\n",
792 (unsigned int)(RAM_size / (1024 * 1024)),
793 (unsigned int)(max_mem / (1024 * 1024)));
794 exit(1);
795 }
796 dev = qdev_create(NULL, "memory");
797 s = SYS_BUS_DEVICE(dev);
798
799 d = FROM_SYSBUS(RamDevice, s);
800 d->size = RAM_size;
801 qdev_init_nofail(dev);
802
803 sysbus_mmio_map(s, 0, addr);
804 }
805
806 static Property ram_properties[] = {
807 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
808 DEFINE_PROP_END_OF_LIST(),
809 };
810
811 static void ram_class_init(ObjectClass *klass, void *data)
812 {
813 DeviceClass *dc = DEVICE_CLASS(klass);
814 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
815
816 k->init = ram_init1;
817 dc->props = ram_properties;
818 }
819
820 static const TypeInfo ram_info = {
821 .name = "memory",
822 .parent = TYPE_SYS_BUS_DEVICE,
823 .instance_size = sizeof(RamDevice),
824 .class_init = ram_class_init,
825 };
826
827 static void cpu_devinit(const char *cpu_model, unsigned int id,
828 uint64_t prom_addr, qemu_irq **cpu_irqs)
829 {
830 CPUState *cs;
831 SPARCCPU *cpu;
832 CPUSPARCState *env;
833
834 cpu = cpu_sparc_init(cpu_model);
835 if (cpu == NULL) {
836 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
837 exit(1);
838 }
839 env = &cpu->env;
840
841 cpu_sparc_set_id(env, id);
842 if (id == 0) {
843 qemu_register_reset(main_cpu_reset, cpu);
844 } else {
845 qemu_register_reset(secondary_cpu_reset, cpu);
846 cs = CPU(cpu);
847 cs->halted = 1;
848 }
849 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
850 env->prom_addr = prom_addr;
851 }
852
853 static void dummy_fdc_tc(void *opaque, int irq, int level)
854 {
855 }
856
857 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
858 const char *boot_device,
859 const char *kernel_filename,
860 const char *kernel_cmdline,
861 const char *initrd_filename, const char *cpu_model)
862 {
863 unsigned int i;
864 void *iommu, *espdma, *ledma, *nvram;
865 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
866 espdma_irq, ledma_irq;
867 qemu_irq esp_reset, dma_enable;
868 qemu_irq fdc_tc;
869 qemu_irq *cpu_halt;
870 unsigned long kernel_size;
871 DriveInfo *fd[MAX_FD];
872 void *fw_cfg;
873 unsigned int num_vsimms;
874
875 /* init CPUs */
876 if (!cpu_model)
877 cpu_model = hwdef->default_cpu_model;
878
879 for(i = 0; i < smp_cpus; i++) {
880 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
881 }
882
883 for (i = smp_cpus; i < MAX_CPUS; i++)
884 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
885
886
887 /* set up devices */
888 ram_init(0, RAM_size, hwdef->max_mem);
889 /* models without ECC don't trap when missing ram is accessed */
890 if (!hwdef->ecc_base) {
891 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
892 }
893
894 prom_init(hwdef->slavio_base, bios_name);
895
896 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
897 hwdef->intctl_base + 0x10000ULL,
898 cpu_irqs);
899
900 for (i = 0; i < 32; i++) {
901 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
902 }
903 for (i = 0; i < MAX_CPUS; i++) {
904 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
905 }
906
907 if (hwdef->idreg_base) {
908 idreg_init(hwdef->idreg_base);
909 }
910
911 if (hwdef->afx_base) {
912 afx_init(hwdef->afx_base);
913 }
914
915 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
916 slavio_irq[30]);
917
918 if (hwdef->iommu_pad_base) {
919 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
920 Software shouldn't use aliased addresses, neither should it crash
921 when does. Using empty_slot instead of aliasing can help with
922 debugging such accesses */
923 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
924 }
925
926 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
927 iommu, &espdma_irq, 0);
928
929 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
930 slavio_irq[16], iommu, &ledma_irq, 1);
931
932 if (graphic_depth != 8 && graphic_depth != 24) {
933 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
934 exit (1);
935 }
936 num_vsimms = 0;
937 if (num_vsimms == 0) {
938 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
939 graphic_depth);
940 }
941
942 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
943 /* vsimm registers probed by OBP */
944 if (hwdef->vsimm[i].reg_base) {
945 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
946 }
947 }
948
949 if (hwdef->sx_base) {
950 empty_slot_init(hwdef->sx_base, 0x2000);
951 }
952
953 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
954
955 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
956
957 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
958
959 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
960 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
961 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
962 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
963 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
964 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
965
966 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
967 if (hwdef->apc_base) {
968 apc_init(hwdef->apc_base, cpu_halt[0]);
969 }
970
971 if (hwdef->fd_base) {
972 /* there is zero or one floppy drive */
973 memset(fd, 0, sizeof(fd));
974 fd[0] = drive_get(IF_FLOPPY, 0, 0);
975 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
976 &fdc_tc);
977 } else {
978 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
979 }
980
981 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
982 slavio_irq[30], fdc_tc);
983
984 if (drive_get_max_bus(IF_SCSI) > 0) {
985 fprintf(stderr, "qemu: too many SCSI bus\n");
986 exit(1);
987 }
988
989 esp_init(hwdef->esp_base, 2,
990 espdma_memory_read, espdma_memory_write,
991 espdma, espdma_irq, &esp_reset, &dma_enable);
992
993 qdev_connect_gpio_out(espdma, 0, esp_reset);
994 qdev_connect_gpio_out(espdma, 1, dma_enable);
995
996 if (hwdef->cs_base) {
997 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
998 slavio_irq[5]);
999 }
1000
1001 if (hwdef->dbri_base) {
1002 /* ISDN chip with attached CS4215 audio codec */
1003 /* prom space */
1004 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1005 /* reg space */
1006 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1007 }
1008
1009 if (hwdef->bpp_base) {
1010 /* parallel port */
1011 empty_slot_init(hwdef->bpp_base, 0x20);
1012 }
1013
1014 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1015 RAM_size);
1016
1017 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1018 boot_device, RAM_size, kernel_size, graphic_width,
1019 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1020 "Sun4m");
1021
1022 if (hwdef->ecc_base)
1023 ecc_init(hwdef->ecc_base, slavio_irq[28],
1024 hwdef->ecc_version);
1025
1026 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1027 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1028 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1029 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1030 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1031 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1032 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1033 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1034 if (kernel_cmdline) {
1035 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1036 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1037 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1038 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1039 strlen(kernel_cmdline) + 1);
1040 } else {
1041 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1043 }
1044 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1045 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1046 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1047 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1048 }
1049
1050 enum {
1051 ss2_id = 0,
1052 ss5_id = 32,
1053 vger_id,
1054 lx_id,
1055 ss4_id,
1056 scls_id,
1057 sbook_id,
1058 ss10_id = 64,
1059 ss20_id,
1060 ss600mp_id,
1061 ss1000_id = 96,
1062 ss2000_id,
1063 };
1064
1065 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1066 /* SS-5 */
1067 {
1068 .iommu_base = 0x10000000,
1069 .iommu_pad_base = 0x10004000,
1070 .iommu_pad_len = 0x0fffb000,
1071 .tcx_base = 0x50000000,
1072 .cs_base = 0x6c000000,
1073 .slavio_base = 0x70000000,
1074 .ms_kb_base = 0x71000000,
1075 .serial_base = 0x71100000,
1076 .nvram_base = 0x71200000,
1077 .fd_base = 0x71400000,
1078 .counter_base = 0x71d00000,
1079 .intctl_base = 0x71e00000,
1080 .idreg_base = 0x78000000,
1081 .dma_base = 0x78400000,
1082 .esp_base = 0x78800000,
1083 .le_base = 0x78c00000,
1084 .apc_base = 0x6a000000,
1085 .afx_base = 0x6e000000,
1086 .aux1_base = 0x71900000,
1087 .aux2_base = 0x71910000,
1088 .nvram_machine_id = 0x80,
1089 .machine_id = ss5_id,
1090 .iommu_version = 0x05000000,
1091 .max_mem = 0x10000000,
1092 .default_cpu_model = "Fujitsu MB86904",
1093 },
1094 /* SS-10 */
1095 {
1096 .iommu_base = 0xfe0000000ULL,
1097 .tcx_base = 0xe20000000ULL,
1098 .slavio_base = 0xff0000000ULL,
1099 .ms_kb_base = 0xff1000000ULL,
1100 .serial_base = 0xff1100000ULL,
1101 .nvram_base = 0xff1200000ULL,
1102 .fd_base = 0xff1700000ULL,
1103 .counter_base = 0xff1300000ULL,
1104 .intctl_base = 0xff1400000ULL,
1105 .idreg_base = 0xef0000000ULL,
1106 .dma_base = 0xef0400000ULL,
1107 .esp_base = 0xef0800000ULL,
1108 .le_base = 0xef0c00000ULL,
1109 .apc_base = 0xefa000000ULL, // XXX should not exist
1110 .aux1_base = 0xff1800000ULL,
1111 .aux2_base = 0xff1a01000ULL,
1112 .ecc_base = 0xf00000000ULL,
1113 .ecc_version = 0x10000000, // version 0, implementation 1
1114 .nvram_machine_id = 0x72,
1115 .machine_id = ss10_id,
1116 .iommu_version = 0x03000000,
1117 .max_mem = 0xf00000000ULL,
1118 .default_cpu_model = "TI SuperSparc II",
1119 },
1120 /* SS-600MP */
1121 {
1122 .iommu_base = 0xfe0000000ULL,
1123 .tcx_base = 0xe20000000ULL,
1124 .slavio_base = 0xff0000000ULL,
1125 .ms_kb_base = 0xff1000000ULL,
1126 .serial_base = 0xff1100000ULL,
1127 .nvram_base = 0xff1200000ULL,
1128 .counter_base = 0xff1300000ULL,
1129 .intctl_base = 0xff1400000ULL,
1130 .dma_base = 0xef0081000ULL,
1131 .esp_base = 0xef0080000ULL,
1132 .le_base = 0xef0060000ULL,
1133 .apc_base = 0xefa000000ULL, // XXX should not exist
1134 .aux1_base = 0xff1800000ULL,
1135 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1136 .ecc_base = 0xf00000000ULL,
1137 .ecc_version = 0x00000000, // version 0, implementation 0
1138 .nvram_machine_id = 0x71,
1139 .machine_id = ss600mp_id,
1140 .iommu_version = 0x01000000,
1141 .max_mem = 0xf00000000ULL,
1142 .default_cpu_model = "TI SuperSparc II",
1143 },
1144 /* SS-20 */
1145 {
1146 .iommu_base = 0xfe0000000ULL,
1147 .tcx_base = 0xe20000000ULL,
1148 .slavio_base = 0xff0000000ULL,
1149 .ms_kb_base = 0xff1000000ULL,
1150 .serial_base = 0xff1100000ULL,
1151 .nvram_base = 0xff1200000ULL,
1152 .fd_base = 0xff1700000ULL,
1153 .counter_base = 0xff1300000ULL,
1154 .intctl_base = 0xff1400000ULL,
1155 .idreg_base = 0xef0000000ULL,
1156 .dma_base = 0xef0400000ULL,
1157 .esp_base = 0xef0800000ULL,
1158 .le_base = 0xef0c00000ULL,
1159 .bpp_base = 0xef4800000ULL,
1160 .apc_base = 0xefa000000ULL, // XXX should not exist
1161 .aux1_base = 0xff1800000ULL,
1162 .aux2_base = 0xff1a01000ULL,
1163 .dbri_base = 0xee0000000ULL,
1164 .sx_base = 0xf80000000ULL,
1165 .vsimm = {
1166 {
1167 .reg_base = 0x9c000000ULL,
1168 .vram_base = 0xfc000000ULL
1169 }, {
1170 .reg_base = 0x90000000ULL,
1171 .vram_base = 0xf0000000ULL
1172 }, {
1173 .reg_base = 0x94000000ULL
1174 }, {
1175 .reg_base = 0x98000000ULL
1176 }
1177 },
1178 .ecc_base = 0xf00000000ULL,
1179 .ecc_version = 0x20000000, // version 0, implementation 2
1180 .nvram_machine_id = 0x72,
1181 .machine_id = ss20_id,
1182 .iommu_version = 0x13000000,
1183 .max_mem = 0xf00000000ULL,
1184 .default_cpu_model = "TI SuperSparc II",
1185 },
1186 /* Voyager */
1187 {
1188 .iommu_base = 0x10000000,
1189 .tcx_base = 0x50000000,
1190 .slavio_base = 0x70000000,
1191 .ms_kb_base = 0x71000000,
1192 .serial_base = 0x71100000,
1193 .nvram_base = 0x71200000,
1194 .fd_base = 0x71400000,
1195 .counter_base = 0x71d00000,
1196 .intctl_base = 0x71e00000,
1197 .idreg_base = 0x78000000,
1198 .dma_base = 0x78400000,
1199 .esp_base = 0x78800000,
1200 .le_base = 0x78c00000,
1201 .apc_base = 0x71300000, // pmc
1202 .aux1_base = 0x71900000,
1203 .aux2_base = 0x71910000,
1204 .nvram_machine_id = 0x80,
1205 .machine_id = vger_id,
1206 .iommu_version = 0x05000000,
1207 .max_mem = 0x10000000,
1208 .default_cpu_model = "Fujitsu MB86904",
1209 },
1210 /* LX */
1211 {
1212 .iommu_base = 0x10000000,
1213 .iommu_pad_base = 0x10004000,
1214 .iommu_pad_len = 0x0fffb000,
1215 .tcx_base = 0x50000000,
1216 .slavio_base = 0x70000000,
1217 .ms_kb_base = 0x71000000,
1218 .serial_base = 0x71100000,
1219 .nvram_base = 0x71200000,
1220 .fd_base = 0x71400000,
1221 .counter_base = 0x71d00000,
1222 .intctl_base = 0x71e00000,
1223 .idreg_base = 0x78000000,
1224 .dma_base = 0x78400000,
1225 .esp_base = 0x78800000,
1226 .le_base = 0x78c00000,
1227 .aux1_base = 0x71900000,
1228 .aux2_base = 0x71910000,
1229 .nvram_machine_id = 0x80,
1230 .machine_id = lx_id,
1231 .iommu_version = 0x04000000,
1232 .max_mem = 0x10000000,
1233 .default_cpu_model = "TI MicroSparc I",
1234 },
1235 /* SS-4 */
1236 {
1237 .iommu_base = 0x10000000,
1238 .tcx_base = 0x50000000,
1239 .cs_base = 0x6c000000,
1240 .slavio_base = 0x70000000,
1241 .ms_kb_base = 0x71000000,
1242 .serial_base = 0x71100000,
1243 .nvram_base = 0x71200000,
1244 .fd_base = 0x71400000,
1245 .counter_base = 0x71d00000,
1246 .intctl_base = 0x71e00000,
1247 .idreg_base = 0x78000000,
1248 .dma_base = 0x78400000,
1249 .esp_base = 0x78800000,
1250 .le_base = 0x78c00000,
1251 .apc_base = 0x6a000000,
1252 .aux1_base = 0x71900000,
1253 .aux2_base = 0x71910000,
1254 .nvram_machine_id = 0x80,
1255 .machine_id = ss4_id,
1256 .iommu_version = 0x05000000,
1257 .max_mem = 0x10000000,
1258 .default_cpu_model = "Fujitsu MB86904",
1259 },
1260 /* SPARCClassic */
1261 {
1262 .iommu_base = 0x10000000,
1263 .tcx_base = 0x50000000,
1264 .slavio_base = 0x70000000,
1265 .ms_kb_base = 0x71000000,
1266 .serial_base = 0x71100000,
1267 .nvram_base = 0x71200000,
1268 .fd_base = 0x71400000,
1269 .counter_base = 0x71d00000,
1270 .intctl_base = 0x71e00000,
1271 .idreg_base = 0x78000000,
1272 .dma_base = 0x78400000,
1273 .esp_base = 0x78800000,
1274 .le_base = 0x78c00000,
1275 .apc_base = 0x6a000000,
1276 .aux1_base = 0x71900000,
1277 .aux2_base = 0x71910000,
1278 .nvram_machine_id = 0x80,
1279 .machine_id = scls_id,
1280 .iommu_version = 0x05000000,
1281 .max_mem = 0x10000000,
1282 .default_cpu_model = "TI MicroSparc I",
1283 },
1284 /* SPARCbook */
1285 {
1286 .iommu_base = 0x10000000,
1287 .tcx_base = 0x50000000, // XXX
1288 .slavio_base = 0x70000000,
1289 .ms_kb_base = 0x71000000,
1290 .serial_base = 0x71100000,
1291 .nvram_base = 0x71200000,
1292 .fd_base = 0x71400000,
1293 .counter_base = 0x71d00000,
1294 .intctl_base = 0x71e00000,
1295 .idreg_base = 0x78000000,
1296 .dma_base = 0x78400000,
1297 .esp_base = 0x78800000,
1298 .le_base = 0x78c00000,
1299 .apc_base = 0x6a000000,
1300 .aux1_base = 0x71900000,
1301 .aux2_base = 0x71910000,
1302 .nvram_machine_id = 0x80,
1303 .machine_id = sbook_id,
1304 .iommu_version = 0x05000000,
1305 .max_mem = 0x10000000,
1306 .default_cpu_model = "TI MicroSparc I",
1307 },
1308 };
1309
1310 /* SPARCstation 5 hardware initialisation */
1311 static void ss5_init(QEMUMachineInitArgs *args)
1312 {
1313 ram_addr_t RAM_size = args->ram_size;
1314 const char *cpu_model = args->cpu_model;
1315 const char *kernel_filename = args->kernel_filename;
1316 const char *kernel_cmdline = args->kernel_cmdline;
1317 const char *initrd_filename = args->initrd_filename;
1318 const char *boot_device = args->boot_device;
1319 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1320 kernel_cmdline, initrd_filename, cpu_model);
1321 }
1322
1323 /* SPARCstation 10 hardware initialisation */
1324 static void ss10_init(QEMUMachineInitArgs *args)
1325 {
1326 ram_addr_t RAM_size = args->ram_size;
1327 const char *cpu_model = args->cpu_model;
1328 const char *kernel_filename = args->kernel_filename;
1329 const char *kernel_cmdline = args->kernel_cmdline;
1330 const char *initrd_filename = args->initrd_filename;
1331 const char *boot_device = args->boot_device;
1332 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1333 kernel_cmdline, initrd_filename, cpu_model);
1334 }
1335
1336 /* SPARCserver 600MP hardware initialisation */
1337 static void ss600mp_init(QEMUMachineInitArgs *args)
1338 {
1339 ram_addr_t RAM_size = args->ram_size;
1340 const char *cpu_model = args->cpu_model;
1341 const char *kernel_filename = args->kernel_filename;
1342 const char *kernel_cmdline = args->kernel_cmdline;
1343 const char *initrd_filename = args->initrd_filename;
1344 const char *boot_device = args->boot_device;
1345 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1346 kernel_cmdline, initrd_filename, cpu_model);
1347 }
1348
1349 /* SPARCstation 20 hardware initialisation */
1350 static void ss20_init(QEMUMachineInitArgs *args)
1351 {
1352 ram_addr_t RAM_size = args->ram_size;
1353 const char *cpu_model = args->cpu_model;
1354 const char *kernel_filename = args->kernel_filename;
1355 const char *kernel_cmdline = args->kernel_cmdline;
1356 const char *initrd_filename = args->initrd_filename;
1357 const char *boot_device = args->boot_device;
1358 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1359 kernel_cmdline, initrd_filename, cpu_model);
1360 }
1361
1362 /* SPARCstation Voyager hardware initialisation */
1363 static void vger_init(QEMUMachineInitArgs *args)
1364 {
1365 ram_addr_t RAM_size = args->ram_size;
1366 const char *cpu_model = args->cpu_model;
1367 const char *kernel_filename = args->kernel_filename;
1368 const char *kernel_cmdline = args->kernel_cmdline;
1369 const char *initrd_filename = args->initrd_filename;
1370 const char *boot_device = args->boot_device;
1371 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1372 kernel_cmdline, initrd_filename, cpu_model);
1373 }
1374
1375 /* SPARCstation LX hardware initialisation */
1376 static void ss_lx_init(QEMUMachineInitArgs *args)
1377 {
1378 ram_addr_t RAM_size = args->ram_size;
1379 const char *cpu_model = args->cpu_model;
1380 const char *kernel_filename = args->kernel_filename;
1381 const char *kernel_cmdline = args->kernel_cmdline;
1382 const char *initrd_filename = args->initrd_filename;
1383 const char *boot_device = args->boot_device;
1384 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1385 kernel_cmdline, initrd_filename, cpu_model);
1386 }
1387
1388 /* SPARCstation 4 hardware initialisation */
1389 static void ss4_init(QEMUMachineInitArgs *args)
1390 {
1391 ram_addr_t RAM_size = args->ram_size;
1392 const char *cpu_model = args->cpu_model;
1393 const char *kernel_filename = args->kernel_filename;
1394 const char *kernel_cmdline = args->kernel_cmdline;
1395 const char *initrd_filename = args->initrd_filename;
1396 const char *boot_device = args->boot_device;
1397 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1398 kernel_cmdline, initrd_filename, cpu_model);
1399 }
1400
1401 /* SPARCClassic hardware initialisation */
1402 static void scls_init(QEMUMachineInitArgs *args)
1403 {
1404 ram_addr_t RAM_size = args->ram_size;
1405 const char *cpu_model = args->cpu_model;
1406 const char *kernel_filename = args->kernel_filename;
1407 const char *kernel_cmdline = args->kernel_cmdline;
1408 const char *initrd_filename = args->initrd_filename;
1409 const char *boot_device = args->boot_device;
1410 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1411 kernel_cmdline, initrd_filename, cpu_model);
1412 }
1413
1414 /* SPARCbook hardware initialisation */
1415 static void sbook_init(QEMUMachineInitArgs *args)
1416 {
1417 ram_addr_t RAM_size = args->ram_size;
1418 const char *cpu_model = args->cpu_model;
1419 const char *kernel_filename = args->kernel_filename;
1420 const char *kernel_cmdline = args->kernel_cmdline;
1421 const char *initrd_filename = args->initrd_filename;
1422 const char *boot_device = args->boot_device;
1423 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1424 kernel_cmdline, initrd_filename, cpu_model);
1425 }
1426
1427 static QEMUMachine ss5_machine = {
1428 .name = "SS-5",
1429 .desc = "Sun4m platform, SPARCstation 5",
1430 .init = ss5_init,
1431 .block_default_type = IF_SCSI,
1432 .is_default = 1,
1433 DEFAULT_MACHINE_OPTIONS,
1434 };
1435
1436 static QEMUMachine ss10_machine = {
1437 .name = "SS-10",
1438 .desc = "Sun4m platform, SPARCstation 10",
1439 .init = ss10_init,
1440 .block_default_type = IF_SCSI,
1441 .max_cpus = 4,
1442 DEFAULT_MACHINE_OPTIONS,
1443 };
1444
1445 static QEMUMachine ss600mp_machine = {
1446 .name = "SS-600MP",
1447 .desc = "Sun4m platform, SPARCserver 600MP",
1448 .init = ss600mp_init,
1449 .block_default_type = IF_SCSI,
1450 .max_cpus = 4,
1451 DEFAULT_MACHINE_OPTIONS,
1452 };
1453
1454 static QEMUMachine ss20_machine = {
1455 .name = "SS-20",
1456 .desc = "Sun4m platform, SPARCstation 20",
1457 .init = ss20_init,
1458 .block_default_type = IF_SCSI,
1459 .max_cpus = 4,
1460 DEFAULT_MACHINE_OPTIONS,
1461 };
1462
1463 static QEMUMachine voyager_machine = {
1464 .name = "Voyager",
1465 .desc = "Sun4m platform, SPARCstation Voyager",
1466 .init = vger_init,
1467 .block_default_type = IF_SCSI,
1468 DEFAULT_MACHINE_OPTIONS,
1469 };
1470
1471 static QEMUMachine ss_lx_machine = {
1472 .name = "LX",
1473 .desc = "Sun4m platform, SPARCstation LX",
1474 .init = ss_lx_init,
1475 .block_default_type = IF_SCSI,
1476 DEFAULT_MACHINE_OPTIONS,
1477 };
1478
1479 static QEMUMachine ss4_machine = {
1480 .name = "SS-4",
1481 .desc = "Sun4m platform, SPARCstation 4",
1482 .init = ss4_init,
1483 .block_default_type = IF_SCSI,
1484 DEFAULT_MACHINE_OPTIONS,
1485 };
1486
1487 static QEMUMachine scls_machine = {
1488 .name = "SPARCClassic",
1489 .desc = "Sun4m platform, SPARCClassic",
1490 .init = scls_init,
1491 .block_default_type = IF_SCSI,
1492 DEFAULT_MACHINE_OPTIONS,
1493 };
1494
1495 static QEMUMachine sbook_machine = {
1496 .name = "SPARCbook",
1497 .desc = "Sun4m platform, SPARCbook",
1498 .init = sbook_init,
1499 .block_default_type = IF_SCSI,
1500 DEFAULT_MACHINE_OPTIONS,
1501 };
1502
1503 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1504 /* SS-1000 */
1505 {
1506 .iounit_bases = {
1507 0xfe0200000ULL,
1508 0xfe1200000ULL,
1509 0xfe2200000ULL,
1510 0xfe3200000ULL,
1511 -1,
1512 },
1513 .tcx_base = 0x820000000ULL,
1514 .slavio_base = 0xf00000000ULL,
1515 .ms_kb_base = 0xf00240000ULL,
1516 .serial_base = 0xf00200000ULL,
1517 .nvram_base = 0xf00280000ULL,
1518 .counter_base = 0xf00300000ULL,
1519 .espdma_base = 0x800081000ULL,
1520 .esp_base = 0x800080000ULL,
1521 .ledma_base = 0x800040000ULL,
1522 .le_base = 0x800060000ULL,
1523 .sbi_base = 0xf02800000ULL,
1524 .nvram_machine_id = 0x80,
1525 .machine_id = ss1000_id,
1526 .iounit_version = 0x03000000,
1527 .max_mem = 0xf00000000ULL,
1528 .default_cpu_model = "TI SuperSparc II",
1529 },
1530 /* SS-2000 */
1531 {
1532 .iounit_bases = {
1533 0xfe0200000ULL,
1534 0xfe1200000ULL,
1535 0xfe2200000ULL,
1536 0xfe3200000ULL,
1537 0xfe4200000ULL,
1538 },
1539 .tcx_base = 0x820000000ULL,
1540 .slavio_base = 0xf00000000ULL,
1541 .ms_kb_base = 0xf00240000ULL,
1542 .serial_base = 0xf00200000ULL,
1543 .nvram_base = 0xf00280000ULL,
1544 .counter_base = 0xf00300000ULL,
1545 .espdma_base = 0x800081000ULL,
1546 .esp_base = 0x800080000ULL,
1547 .ledma_base = 0x800040000ULL,
1548 .le_base = 0x800060000ULL,
1549 .sbi_base = 0xf02800000ULL,
1550 .nvram_machine_id = 0x80,
1551 .machine_id = ss2000_id,
1552 .iounit_version = 0x03000000,
1553 .max_mem = 0xf00000000ULL,
1554 .default_cpu_model = "TI SuperSparc II",
1555 },
1556 };
1557
1558 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1559 {
1560 DeviceState *dev;
1561 SysBusDevice *s;
1562 unsigned int i;
1563
1564 dev = qdev_create(NULL, "sbi");
1565 qdev_init_nofail(dev);
1566
1567 s = SYS_BUS_DEVICE(dev);
1568
1569 for (i = 0; i < MAX_CPUS; i++) {
1570 sysbus_connect_irq(s, i, *parent_irq[i]);
1571 }
1572
1573 sysbus_mmio_map(s, 0, addr);
1574
1575 return dev;
1576 }
1577
1578 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1579 const char *boot_device,
1580 const char *kernel_filename,
1581 const char *kernel_cmdline,
1582 const char *initrd_filename, const char *cpu_model)
1583 {
1584 unsigned int i;
1585 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1586 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1587 espdma_irq, ledma_irq;
1588 qemu_irq esp_reset, dma_enable;
1589 unsigned long kernel_size;
1590 void *fw_cfg;
1591 DeviceState *dev;
1592
1593 /* init CPUs */
1594 if (!cpu_model)
1595 cpu_model = hwdef->default_cpu_model;
1596
1597 for(i = 0; i < smp_cpus; i++) {
1598 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1599 }
1600
1601 for (i = smp_cpus; i < MAX_CPUS; i++)
1602 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1603
1604 /* set up devices */
1605 ram_init(0, RAM_size, hwdef->max_mem);
1606
1607 prom_init(hwdef->slavio_base, bios_name);
1608
1609 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1610
1611 for (i = 0; i < 32; i++) {
1612 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1613 }
1614 for (i = 0; i < MAX_CPUS; i++) {
1615 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1616 }
1617
1618 for (i = 0; i < MAX_IOUNITS; i++)
1619 if (hwdef->iounit_bases[i] != (hwaddr)-1)
1620 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1621 hwdef->iounit_version,
1622 sbi_irq[0]);
1623
1624 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1625 iounits[0], &espdma_irq, 0);
1626
1627 /* should be lebuffer instead */
1628 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1629 iounits[0], &ledma_irq, 0);
1630
1631 if (graphic_depth != 8 && graphic_depth != 24) {
1632 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1633 exit (1);
1634 }
1635 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1636 graphic_depth);
1637
1638 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1639
1640 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1641
1642 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1643
1644 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1645 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1646 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1647 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1648 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1649 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1650
1651 if (drive_get_max_bus(IF_SCSI) > 0) {
1652 fprintf(stderr, "qemu: too many SCSI bus\n");
1653 exit(1);
1654 }
1655
1656 esp_init(hwdef->esp_base, 2,
1657 espdma_memory_read, espdma_memory_write,
1658 espdma, espdma_irq, &esp_reset, &dma_enable);
1659
1660 qdev_connect_gpio_out(espdma, 0, esp_reset);
1661 qdev_connect_gpio_out(espdma, 1, dma_enable);
1662
1663 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1664 RAM_size);
1665
1666 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1667 boot_device, RAM_size, kernel_size, graphic_width,
1668 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1669 "Sun4d");
1670
1671 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1672 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1673 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1674 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1675 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1676 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1677 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1678 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1679 if (kernel_cmdline) {
1680 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1681 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1682 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1683 } else {
1684 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1685 }
1686 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1687 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1688 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1689 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1690 }
1691
1692 /* SPARCserver 1000 hardware initialisation */
1693 static void ss1000_init(QEMUMachineInitArgs *args)
1694 {
1695 ram_addr_t RAM_size = args->ram_size;
1696 const char *cpu_model = args->cpu_model;
1697 const char *kernel_filename = args->kernel_filename;
1698 const char *kernel_cmdline = args->kernel_cmdline;
1699 const char *initrd_filename = args->initrd_filename;
1700 const char *boot_device = args->boot_device;
1701 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1702 kernel_cmdline, initrd_filename, cpu_model);
1703 }
1704
1705 /* SPARCcenter 2000 hardware initialisation */
1706 static void ss2000_init(QEMUMachineInitArgs *args)
1707 {
1708 ram_addr_t RAM_size = args->ram_size;
1709 const char *cpu_model = args->cpu_model;
1710 const char *kernel_filename = args->kernel_filename;
1711 const char *kernel_cmdline = args->kernel_cmdline;
1712 const char *initrd_filename = args->initrd_filename;
1713 const char *boot_device = args->boot_device;
1714 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1715 kernel_cmdline, initrd_filename, cpu_model);
1716 }
1717
1718 static QEMUMachine ss1000_machine = {
1719 .name = "SS-1000",
1720 .desc = "Sun4d platform, SPARCserver 1000",
1721 .init = ss1000_init,
1722 .block_default_type = IF_SCSI,
1723 .max_cpus = 8,
1724 DEFAULT_MACHINE_OPTIONS,
1725 };
1726
1727 static QEMUMachine ss2000_machine = {
1728 .name = "SS-2000",
1729 .desc = "Sun4d platform, SPARCcenter 2000",
1730 .init = ss2000_init,
1731 .block_default_type = IF_SCSI,
1732 .max_cpus = 20,
1733 DEFAULT_MACHINE_OPTIONS,
1734 };
1735
1736 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1737 /* SS-2 */
1738 {
1739 .iommu_base = 0xf8000000,
1740 .tcx_base = 0xfe000000,
1741 .slavio_base = 0xf6000000,
1742 .intctl_base = 0xf5000000,
1743 .counter_base = 0xf3000000,
1744 .ms_kb_base = 0xf0000000,
1745 .serial_base = 0xf1000000,
1746 .nvram_base = 0xf2000000,
1747 .fd_base = 0xf7200000,
1748 .dma_base = 0xf8400000,
1749 .esp_base = 0xf8800000,
1750 .le_base = 0xf8c00000,
1751 .aux1_base = 0xf7400003,
1752 .nvram_machine_id = 0x55,
1753 .machine_id = ss2_id,
1754 .max_mem = 0x10000000,
1755 .default_cpu_model = "Cypress CY7C601",
1756 },
1757 };
1758
1759 static DeviceState *sun4c_intctl_init(hwaddr addr,
1760 qemu_irq *parent_irq)
1761 {
1762 DeviceState *dev;
1763 SysBusDevice *s;
1764 unsigned int i;
1765
1766 dev = qdev_create(NULL, "sun4c_intctl");
1767 qdev_init_nofail(dev);
1768
1769 s = SYS_BUS_DEVICE(dev);
1770
1771 for (i = 0; i < MAX_PILS; i++) {
1772 sysbus_connect_irq(s, i, parent_irq[i]);
1773 }
1774 sysbus_mmio_map(s, 0, addr);
1775
1776 return dev;
1777 }
1778
1779 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1780 const char *boot_device,
1781 const char *kernel_filename,
1782 const char *kernel_cmdline,
1783 const char *initrd_filename, const char *cpu_model)
1784 {
1785 void *iommu, *espdma, *ledma, *nvram;
1786 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1787 qemu_irq esp_reset, dma_enable;
1788 qemu_irq fdc_tc;
1789 unsigned long kernel_size;
1790 DriveInfo *fd[MAX_FD];
1791 void *fw_cfg;
1792 DeviceState *dev;
1793 unsigned int i;
1794
1795 /* init CPU */
1796 if (!cpu_model)
1797 cpu_model = hwdef->default_cpu_model;
1798
1799 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1800
1801 /* set up devices */
1802 ram_init(0, RAM_size, hwdef->max_mem);
1803
1804 prom_init(hwdef->slavio_base, bios_name);
1805
1806 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1807
1808 for (i = 0; i < 8; i++) {
1809 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1810 }
1811
1812 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1813 slavio_irq[1]);
1814
1815 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1816 iommu, &espdma_irq, 0);
1817
1818 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1819 slavio_irq[3], iommu, &ledma_irq, 1);
1820
1821 if (graphic_depth != 8 && graphic_depth != 24) {
1822 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1823 exit (1);
1824 }
1825 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1826 graphic_depth);
1827
1828 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1829
1830 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1831
1832 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1833 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1834 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1835 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1836 escc_init(hwdef->serial_base, slavio_irq[1],
1837 slavio_irq[1], serial_hds[0], serial_hds[1],
1838 ESCC_CLOCK, 1);
1839
1840 if (hwdef->fd_base != (hwaddr)-1) {
1841 /* there is zero or one floppy drive */
1842 memset(fd, 0, sizeof(fd));
1843 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1844 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1845 &fdc_tc);
1846 } else {
1847 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1848 }
1849
1850 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1851
1852 if (drive_get_max_bus(IF_SCSI) > 0) {
1853 fprintf(stderr, "qemu: too many SCSI bus\n");
1854 exit(1);
1855 }
1856
1857 esp_init(hwdef->esp_base, 2,
1858 espdma_memory_read, espdma_memory_write,
1859 espdma, espdma_irq, &esp_reset, &dma_enable);
1860
1861 qdev_connect_gpio_out(espdma, 0, esp_reset);
1862 qdev_connect_gpio_out(espdma, 1, dma_enable);
1863
1864 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1865 RAM_size);
1866
1867 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1868 boot_device, RAM_size, kernel_size, graphic_width,
1869 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1870 "Sun4c");
1871
1872 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1873 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1874 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1875 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1876 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1877 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1878 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1879 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1880 if (kernel_cmdline) {
1881 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1882 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1883 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1884 } else {
1885 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1886 }
1887 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1888 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1889 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1890 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1891 }
1892
1893 /* SPARCstation 2 hardware initialisation */
1894 static void ss2_init(QEMUMachineInitArgs *args)
1895 {
1896 ram_addr_t RAM_size = args->ram_size;
1897 const char *cpu_model = args->cpu_model;
1898 const char *kernel_filename = args->kernel_filename;
1899 const char *kernel_cmdline = args->kernel_cmdline;
1900 const char *initrd_filename = args->initrd_filename;
1901 const char *boot_device = args->boot_device;
1902 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1903 kernel_cmdline, initrd_filename, cpu_model);
1904 }
1905
1906 static QEMUMachine ss2_machine = {
1907 .name = "SS-2",
1908 .desc = "Sun4c platform, SPARCstation 2",
1909 .init = ss2_init,
1910 .block_default_type = IF_SCSI,
1911 DEFAULT_MACHINE_OPTIONS,
1912 };
1913
1914 static void sun4m_register_types(void)
1915 {
1916 type_register_static(&idreg_info);
1917 type_register_static(&afx_info);
1918 type_register_static(&prom_info);
1919 type_register_static(&ram_info);
1920 }
1921
1922 static void ss2_machine_init(void)
1923 {
1924 qemu_register_machine(&ss5_machine);
1925 qemu_register_machine(&ss10_machine);
1926 qemu_register_machine(&ss600mp_machine);
1927 qemu_register_machine(&ss20_machine);
1928 qemu_register_machine(&voyager_machine);
1929 qemu_register_machine(&ss_lx_machine);
1930 qemu_register_machine(&ss4_machine);
1931 qemu_register_machine(&scls_machine);
1932 qemu_register_machine(&sbook_machine);
1933 qemu_register_machine(&ss1000_machine);
1934 qemu_register_machine(&ss2000_machine);
1935 qemu_register_machine(&ss2_machine);
1936 }
1937
1938 type_init(sun4m_register_types)
1939 machine_init(ss2_machine_init);
Qemu copy for testing