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Merge remote-tracking branch 'afaerber/qom-cpu' into staging
[qemu.git] / hw / sparc / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/sysbus.h"
25 #include "qemu/timer.h"
26 #include "hw/sun4m.h"
27 #include "hw/nvram.h"
28 #include "hw/sparc32_dma.h"
29 #include "hw/fdc.h"
30 #include "sysemu/sysemu.h"
31 #include "net/net.h"
32 #include "hw/boards.h"
33 #include "hw/firmware_abi.h"
34 #include "hw/esp.h"
35 #include "hw/pc.h"
36 #include "hw/isa.h"
37 #include "hw/fw_cfg.h"
38 #include "hw/escc.h"
39 #include "hw/empty_slot.h"
40 #include "hw/qdev-addr.h"
41 #include "hw/loader.h"
42 #include "elf.h"
43 #include "sysemu/blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
92 hwaddr serial_base, fd_base;
93 hwaddr afx_base, idreg_base, dma_base, esp_base, le_base;
94 hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 hwaddr bpp_base, dbri_base, sx_base;
96 struct {
97 hwaddr reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 hwaddr ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 hwaddr iounit_bases[MAX_IOUNITS], slavio_base;
112 hwaddr counter_base, nvram_base, ms_kb_base;
113 hwaddr serial_base;
114 hwaddr espdma_base, esp_base;
115 hwaddr ledma_base, le_base;
116 hwaddr tcx_base;
117 hwaddr sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 hwaddr iommu_base, slavio_base;
127 hwaddr intctl_base, counter_base, nvram_base, ms_kb_base;
128 hwaddr serial_base, fd_base;
129 hwaddr idreg_base, dma_base, esp_base, le_base;
130 hwaddr tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon, const QDict *qdict)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon, const QDict *qdict)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUSPARCState *env)
232 {
233 CPUState *cs;
234
235 if (env->pil_in && (env->interrupt_index == 0 ||
236 (env->interrupt_index & ~15) == TT_EXTINT)) {
237 unsigned int i;
238
239 for (i = 15; i > 0; i--) {
240 if (env->pil_in & (1 << i)) {
241 int old_interrupt = env->interrupt_index;
242
243 env->interrupt_index = TT_EXTINT | i;
244 if (old_interrupt != env->interrupt_index) {
245 cs = CPU(sparc_env_get_cpu(env));
246 trace_sun4m_cpu_interrupt(i);
247 cpu_interrupt(cs, CPU_INTERRUPT_HARD);
248 }
249 break;
250 }
251 }
252 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
253 cs = CPU(sparc_env_get_cpu(env));
254 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
255 env->interrupt_index = 0;
256 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
257 }
258 }
259
260 static void cpu_kick_irq(SPARCCPU *cpu)
261 {
262 CPUSPARCState *env = &cpu->env;
263 CPUState *cs = CPU(cpu);
264
265 cs->halted = 0;
266 cpu_check_irqs(env);
267 qemu_cpu_kick(cs);
268 }
269
270 static void cpu_set_irq(void *opaque, int irq, int level)
271 {
272 SPARCCPU *cpu = opaque;
273 CPUSPARCState *env = &cpu->env;
274
275 if (level) {
276 trace_sun4m_cpu_set_irq_raise(irq);
277 env->pil_in |= 1 << irq;
278 cpu_kick_irq(cpu);
279 } else {
280 trace_sun4m_cpu_set_irq_lower(irq);
281 env->pil_in &= ~(1 << irq);
282 cpu_check_irqs(env);
283 }
284 }
285
286 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
287 {
288 }
289
290 static void main_cpu_reset(void *opaque)
291 {
292 SPARCCPU *cpu = opaque;
293 CPUState *cs = CPU(cpu);
294
295 cpu_reset(cs);
296 cs->halted = 0;
297 }
298
299 static void secondary_cpu_reset(void *opaque)
300 {
301 SPARCCPU *cpu = opaque;
302 CPUState *cs = CPU(cpu);
303
304 cpu_reset(cs);
305 cs->halted = 1;
306 }
307
308 static void cpu_halt_signal(void *opaque, int irq, int level)
309 {
310 if (level && cpu_single_env) {
311 cpu_interrupt(CPU(sparc_env_get_cpu(cpu_single_env)),
312 CPU_INTERRUPT_HALT);
313 }
314 }
315
316 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
317 {
318 return addr - 0xf0000000ULL;
319 }
320
321 static unsigned long sun4m_load_kernel(const char *kernel_filename,
322 const char *initrd_filename,
323 ram_addr_t RAM_size)
324 {
325 int linux_boot;
326 unsigned int i;
327 long initrd_size, kernel_size;
328 uint8_t *ptr;
329
330 linux_boot = (kernel_filename != NULL);
331
332 kernel_size = 0;
333 if (linux_boot) {
334 int bswap_needed;
335
336 #ifdef BSWAP_NEEDED
337 bswap_needed = 1;
338 #else
339 bswap_needed = 0;
340 #endif
341 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
342 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
343 if (kernel_size < 0)
344 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
345 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
346 TARGET_PAGE_SIZE);
347 if (kernel_size < 0)
348 kernel_size = load_image_targphys(kernel_filename,
349 KERNEL_LOAD_ADDR,
350 RAM_size - KERNEL_LOAD_ADDR);
351 if (kernel_size < 0) {
352 fprintf(stderr, "qemu: could not load kernel '%s'\n",
353 kernel_filename);
354 exit(1);
355 }
356
357 /* load initrd */
358 initrd_size = 0;
359 if (initrd_filename) {
360 initrd_size = load_image_targphys(initrd_filename,
361 INITRD_LOAD_ADDR,
362 RAM_size - INITRD_LOAD_ADDR);
363 if (initrd_size < 0) {
364 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
365 initrd_filename);
366 exit(1);
367 }
368 }
369 if (initrd_size > 0) {
370 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
371 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
372 if (ldl_p(ptr) == 0x48647253) { // HdrS
373 stl_p(ptr + 16, INITRD_LOAD_ADDR);
374 stl_p(ptr + 20, initrd_size);
375 break;
376 }
377 }
378 }
379 }
380 return kernel_size;
381 }
382
383 static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq)
384 {
385 DeviceState *dev;
386 SysBusDevice *s;
387
388 dev = qdev_create(NULL, "iommu");
389 qdev_prop_set_uint32(dev, "version", version);
390 qdev_init_nofail(dev);
391 s = SYS_BUS_DEVICE(dev);
392 sysbus_connect_irq(s, 0, irq);
393 sysbus_mmio_map(s, 0, addr);
394
395 return s;
396 }
397
398 static void *sparc32_dma_init(hwaddr daddr, qemu_irq parent_irq,
399 void *iommu, qemu_irq *dev_irq, int is_ledma)
400 {
401 DeviceState *dev;
402 SysBusDevice *s;
403
404 dev = qdev_create(NULL, "sparc32_dma");
405 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
406 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
407 qdev_init_nofail(dev);
408 s = SYS_BUS_DEVICE(dev);
409 sysbus_connect_irq(s, 0, parent_irq);
410 *dev_irq = qdev_get_gpio_in(dev, 0);
411 sysbus_mmio_map(s, 0, daddr);
412
413 return s;
414 }
415
416 static void lance_init(NICInfo *nd, hwaddr leaddr,
417 void *dma_opaque, qemu_irq irq)
418 {
419 DeviceState *dev;
420 SysBusDevice *s;
421 qemu_irq reset;
422
423 qemu_check_nic_model(&nd_table[0], "lance");
424
425 dev = qdev_create(NULL, "lance");
426 qdev_set_nic_properties(dev, nd);
427 qdev_prop_set_ptr(dev, "dma", dma_opaque);
428 qdev_init_nofail(dev);
429 s = SYS_BUS_DEVICE(dev);
430 sysbus_mmio_map(s, 0, leaddr);
431 sysbus_connect_irq(s, 0, irq);
432 reset = qdev_get_gpio_in(dev, 0);
433 qdev_connect_gpio_out(dma_opaque, 0, reset);
434 }
435
436 static DeviceState *slavio_intctl_init(hwaddr addr,
437 hwaddr addrg,
438 qemu_irq **parent_irq)
439 {
440 DeviceState *dev;
441 SysBusDevice *s;
442 unsigned int i, j;
443
444 dev = qdev_create(NULL, "slavio_intctl");
445 qdev_init_nofail(dev);
446
447 s = SYS_BUS_DEVICE(dev);
448
449 for (i = 0; i < MAX_CPUS; i++) {
450 for (j = 0; j < MAX_PILS; j++) {
451 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
452 }
453 }
454 sysbus_mmio_map(s, 0, addrg);
455 for (i = 0; i < MAX_CPUS; i++) {
456 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
457 }
458
459 return dev;
460 }
461
462 #define SYS_TIMER_OFFSET 0x10000ULL
463 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
464
465 static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq,
466 qemu_irq *cpu_irqs, unsigned int num_cpus)
467 {
468 DeviceState *dev;
469 SysBusDevice *s;
470 unsigned int i;
471
472 dev = qdev_create(NULL, "slavio_timer");
473 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
474 qdev_init_nofail(dev);
475 s = SYS_BUS_DEVICE(dev);
476 sysbus_connect_irq(s, 0, master_irq);
477 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
478
479 for (i = 0; i < MAX_CPUS; i++) {
480 sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i));
481 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
482 }
483 }
484
485 static qemu_irq slavio_system_powerdown;
486
487 static void slavio_powerdown_req(Notifier *n, void *opaque)
488 {
489 qemu_irq_raise(slavio_system_powerdown);
490 }
491
492 static Notifier slavio_system_powerdown_notifier = {
493 .notify = slavio_powerdown_req
494 };
495
496 #define MISC_LEDS 0x01600000
497 #define MISC_CFG 0x01800000
498 #define MISC_DIAG 0x01a00000
499 #define MISC_MDM 0x01b00000
500 #define MISC_SYS 0x01f00000
501
502 static void slavio_misc_init(hwaddr base,
503 hwaddr aux1_base,
504 hwaddr aux2_base, qemu_irq irq,
505 qemu_irq fdc_tc)
506 {
507 DeviceState *dev;
508 SysBusDevice *s;
509
510 dev = qdev_create(NULL, "slavio_misc");
511 qdev_init_nofail(dev);
512 s = SYS_BUS_DEVICE(dev);
513 if (base) {
514 /* 8 bit registers */
515 /* Slavio control */
516 sysbus_mmio_map(s, 0, base + MISC_CFG);
517 /* Diagnostics */
518 sysbus_mmio_map(s, 1, base + MISC_DIAG);
519 /* Modem control */
520 sysbus_mmio_map(s, 2, base + MISC_MDM);
521 /* 16 bit registers */
522 /* ss600mp diag LEDs */
523 sysbus_mmio_map(s, 3, base + MISC_LEDS);
524 /* 32 bit registers */
525 /* System control */
526 sysbus_mmio_map(s, 4, base + MISC_SYS);
527 }
528 if (aux1_base) {
529 /* AUX 1 (Misc System Functions) */
530 sysbus_mmio_map(s, 5, aux1_base);
531 }
532 if (aux2_base) {
533 /* AUX 2 (Software Powerdown Control) */
534 sysbus_mmio_map(s, 6, aux2_base);
535 }
536 sysbus_connect_irq(s, 0, irq);
537 sysbus_connect_irq(s, 1, fdc_tc);
538 slavio_system_powerdown = qdev_get_gpio_in(dev, 0);
539 qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier);
540 }
541
542 static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version)
543 {
544 DeviceState *dev;
545 SysBusDevice *s;
546
547 dev = qdev_create(NULL, "eccmemctl");
548 qdev_prop_set_uint32(dev, "version", version);
549 qdev_init_nofail(dev);
550 s = SYS_BUS_DEVICE(dev);
551 sysbus_connect_irq(s, 0, irq);
552 sysbus_mmio_map(s, 0, base);
553 if (version == 0) { // SS-600MP only
554 sysbus_mmio_map(s, 1, base + 0x1000);
555 }
556 }
557
558 static void apc_init(hwaddr power_base, qemu_irq cpu_halt)
559 {
560 DeviceState *dev;
561 SysBusDevice *s;
562
563 dev = qdev_create(NULL, "apc");
564 qdev_init_nofail(dev);
565 s = SYS_BUS_DEVICE(dev);
566 /* Power management (APC) XXX: not a Slavio device */
567 sysbus_mmio_map(s, 0, power_base);
568 sysbus_connect_irq(s, 0, cpu_halt);
569 }
570
571 static void tcx_init(hwaddr addr, int vram_size, int width,
572 int height, int depth)
573 {
574 DeviceState *dev;
575 SysBusDevice *s;
576
577 dev = qdev_create(NULL, "SUNW,tcx");
578 qdev_prop_set_taddr(dev, "addr", addr);
579 qdev_prop_set_uint32(dev, "vram_size", vram_size);
580 qdev_prop_set_uint16(dev, "width", width);
581 qdev_prop_set_uint16(dev, "height", height);
582 qdev_prop_set_uint16(dev, "depth", depth);
583 qdev_init_nofail(dev);
584 s = SYS_BUS_DEVICE(dev);
585 /* 8-bit plane */
586 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
587 /* DAC */
588 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
589 /* TEC (dummy) */
590 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
591 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
592 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
593 if (depth == 24) {
594 /* 24-bit plane */
595 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
596 /* Control plane */
597 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
598 } else {
599 /* THC 8 bit (dummy) */
600 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
601 }
602 }
603
604 /* NCR89C100/MACIO Internal ID register */
605 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
606
607 static void idreg_init(hwaddr addr)
608 {
609 DeviceState *dev;
610 SysBusDevice *s;
611
612 dev = qdev_create(NULL, "macio_idreg");
613 qdev_init_nofail(dev);
614 s = SYS_BUS_DEVICE(dev);
615
616 sysbus_mmio_map(s, 0, addr);
617 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
618 }
619
620 typedef struct IDRegState {
621 SysBusDevice busdev;
622 MemoryRegion mem;
623 } IDRegState;
624
625 static int idreg_init1(SysBusDevice *dev)
626 {
627 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
628
629 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
630 vmstate_register_ram_global(&s->mem);
631 memory_region_set_readonly(&s->mem, true);
632 sysbus_init_mmio(dev, &s->mem);
633 return 0;
634 }
635
636 static void idreg_class_init(ObjectClass *klass, void *data)
637 {
638 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
639
640 k->init = idreg_init1;
641 }
642
643 static const TypeInfo idreg_info = {
644 .name = "macio_idreg",
645 .parent = TYPE_SYS_BUS_DEVICE,
646 .instance_size = sizeof(IDRegState),
647 .class_init = idreg_class_init,
648 };
649
650 typedef struct AFXState {
651 SysBusDevice busdev;
652 MemoryRegion mem;
653 } AFXState;
654
655 /* SS-5 TCX AFX register */
656 static void afx_init(hwaddr addr)
657 {
658 DeviceState *dev;
659 SysBusDevice *s;
660
661 dev = qdev_create(NULL, "tcx_afx");
662 qdev_init_nofail(dev);
663 s = SYS_BUS_DEVICE(dev);
664
665 sysbus_mmio_map(s, 0, addr);
666 }
667
668 static int afx_init1(SysBusDevice *dev)
669 {
670 AFXState *s = FROM_SYSBUS(AFXState, dev);
671
672 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
673 vmstate_register_ram_global(&s->mem);
674 sysbus_init_mmio(dev, &s->mem);
675 return 0;
676 }
677
678 static void afx_class_init(ObjectClass *klass, void *data)
679 {
680 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
681
682 k->init = afx_init1;
683 }
684
685 static const TypeInfo afx_info = {
686 .name = "tcx_afx",
687 .parent = TYPE_SYS_BUS_DEVICE,
688 .instance_size = sizeof(AFXState),
689 .class_init = afx_class_init,
690 };
691
692 typedef struct PROMState {
693 SysBusDevice busdev;
694 MemoryRegion prom;
695 } PROMState;
696
697 /* Boot PROM (OpenBIOS) */
698 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
699 {
700 hwaddr *base_addr = (hwaddr *)opaque;
701 return addr + *base_addr - PROM_VADDR;
702 }
703
704 static void prom_init(hwaddr addr, const char *bios_name)
705 {
706 DeviceState *dev;
707 SysBusDevice *s;
708 char *filename;
709 int ret;
710
711 dev = qdev_create(NULL, "openprom");
712 qdev_init_nofail(dev);
713 s = SYS_BUS_DEVICE(dev);
714
715 sysbus_mmio_map(s, 0, addr);
716
717 /* load boot prom */
718 if (bios_name == NULL) {
719 bios_name = PROM_FILENAME;
720 }
721 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
722 if (filename) {
723 ret = load_elf(filename, translate_prom_address, &addr, NULL,
724 NULL, NULL, 1, ELF_MACHINE, 0);
725 if (ret < 0 || ret > PROM_SIZE_MAX) {
726 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
727 }
728 g_free(filename);
729 } else {
730 ret = -1;
731 }
732 if (ret < 0 || ret > PROM_SIZE_MAX) {
733 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
734 exit(1);
735 }
736 }
737
738 static int prom_init1(SysBusDevice *dev)
739 {
740 PROMState *s = FROM_SYSBUS(PROMState, dev);
741
742 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
743 vmstate_register_ram_global(&s->prom);
744 memory_region_set_readonly(&s->prom, true);
745 sysbus_init_mmio(dev, &s->prom);
746 return 0;
747 }
748
749 static Property prom_properties[] = {
750 {/* end of property list */},
751 };
752
753 static void prom_class_init(ObjectClass *klass, void *data)
754 {
755 DeviceClass *dc = DEVICE_CLASS(klass);
756 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
757
758 k->init = prom_init1;
759 dc->props = prom_properties;
760 }
761
762 static const TypeInfo prom_info = {
763 .name = "openprom",
764 .parent = TYPE_SYS_BUS_DEVICE,
765 .instance_size = sizeof(PROMState),
766 .class_init = prom_class_init,
767 };
768
769 typedef struct RamDevice
770 {
771 SysBusDevice busdev;
772 MemoryRegion ram;
773 uint64_t size;
774 } RamDevice;
775
776 /* System RAM */
777 static int ram_init1(SysBusDevice *dev)
778 {
779 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
780
781 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
782 vmstate_register_ram_global(&d->ram);
783 sysbus_init_mmio(dev, &d->ram);
784 return 0;
785 }
786
787 static void ram_init(hwaddr addr, ram_addr_t RAM_size,
788 uint64_t max_mem)
789 {
790 DeviceState *dev;
791 SysBusDevice *s;
792 RamDevice *d;
793
794 /* allocate RAM */
795 if ((uint64_t)RAM_size > max_mem) {
796 fprintf(stderr,
797 "qemu: Too much memory for this machine: %d, maximum %d\n",
798 (unsigned int)(RAM_size / (1024 * 1024)),
799 (unsigned int)(max_mem / (1024 * 1024)));
800 exit(1);
801 }
802 dev = qdev_create(NULL, "memory");
803 s = SYS_BUS_DEVICE(dev);
804
805 d = FROM_SYSBUS(RamDevice, s);
806 d->size = RAM_size;
807 qdev_init_nofail(dev);
808
809 sysbus_mmio_map(s, 0, addr);
810 }
811
812 static Property ram_properties[] = {
813 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
814 DEFINE_PROP_END_OF_LIST(),
815 };
816
817 static void ram_class_init(ObjectClass *klass, void *data)
818 {
819 DeviceClass *dc = DEVICE_CLASS(klass);
820 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
821
822 k->init = ram_init1;
823 dc->props = ram_properties;
824 }
825
826 static const TypeInfo ram_info = {
827 .name = "memory",
828 .parent = TYPE_SYS_BUS_DEVICE,
829 .instance_size = sizeof(RamDevice),
830 .class_init = ram_class_init,
831 };
832
833 static void cpu_devinit(const char *cpu_model, unsigned int id,
834 uint64_t prom_addr, qemu_irq **cpu_irqs)
835 {
836 CPUState *cs;
837 SPARCCPU *cpu;
838 CPUSPARCState *env;
839
840 cpu = cpu_sparc_init(cpu_model);
841 if (cpu == NULL) {
842 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
843 exit(1);
844 }
845 env = &cpu->env;
846
847 cpu_sparc_set_id(env, id);
848 if (id == 0) {
849 qemu_register_reset(main_cpu_reset, cpu);
850 } else {
851 qemu_register_reset(secondary_cpu_reset, cpu);
852 cs = CPU(cpu);
853 cs->halted = 1;
854 }
855 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS);
856 env->prom_addr = prom_addr;
857 }
858
859 static void dummy_fdc_tc(void *opaque, int irq, int level)
860 {
861 }
862
863 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
864 const char *boot_device,
865 const char *kernel_filename,
866 const char *kernel_cmdline,
867 const char *initrd_filename, const char *cpu_model)
868 {
869 unsigned int i;
870 void *iommu, *espdma, *ledma, *nvram;
871 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
872 espdma_irq, ledma_irq;
873 qemu_irq esp_reset, dma_enable;
874 qemu_irq fdc_tc;
875 qemu_irq *cpu_halt;
876 unsigned long kernel_size;
877 DriveInfo *fd[MAX_FD];
878 void *fw_cfg;
879 unsigned int num_vsimms;
880
881 /* init CPUs */
882 if (!cpu_model)
883 cpu_model = hwdef->default_cpu_model;
884
885 for(i = 0; i < smp_cpus; i++) {
886 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
887 }
888
889 for (i = smp_cpus; i < MAX_CPUS; i++)
890 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
891
892
893 /* set up devices */
894 ram_init(0, RAM_size, hwdef->max_mem);
895 /* models without ECC don't trap when missing ram is accessed */
896 if (!hwdef->ecc_base) {
897 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
898 }
899
900 prom_init(hwdef->slavio_base, bios_name);
901
902 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
903 hwdef->intctl_base + 0x10000ULL,
904 cpu_irqs);
905
906 for (i = 0; i < 32; i++) {
907 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
908 }
909 for (i = 0; i < MAX_CPUS; i++) {
910 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
911 }
912
913 if (hwdef->idreg_base) {
914 idreg_init(hwdef->idreg_base);
915 }
916
917 if (hwdef->afx_base) {
918 afx_init(hwdef->afx_base);
919 }
920
921 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
922 slavio_irq[30]);
923
924 if (hwdef->iommu_pad_base) {
925 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
926 Software shouldn't use aliased addresses, neither should it crash
927 when does. Using empty_slot instead of aliasing can help with
928 debugging such accesses */
929 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
930 }
931
932 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
933 iommu, &espdma_irq, 0);
934
935 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
936 slavio_irq[16], iommu, &ledma_irq, 1);
937
938 if (graphic_depth != 8 && graphic_depth != 24) {
939 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
940 exit (1);
941 }
942 num_vsimms = 0;
943 if (num_vsimms == 0) {
944 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
945 graphic_depth);
946 }
947
948 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
949 /* vsimm registers probed by OBP */
950 if (hwdef->vsimm[i].reg_base) {
951 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
952 }
953 }
954
955 if (hwdef->sx_base) {
956 empty_slot_init(hwdef->sx_base, 0x2000);
957 }
958
959 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
960
961 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
962
963 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
964
965 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
966 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
967 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
968 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
969 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
970 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
971
972 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
973 if (hwdef->apc_base) {
974 apc_init(hwdef->apc_base, cpu_halt[0]);
975 }
976
977 if (hwdef->fd_base) {
978 /* there is zero or one floppy drive */
979 memset(fd, 0, sizeof(fd));
980 fd[0] = drive_get(IF_FLOPPY, 0, 0);
981 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
982 &fdc_tc);
983 } else {
984 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
985 }
986
987 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
988 slavio_irq[30], fdc_tc);
989
990 if (drive_get_max_bus(IF_SCSI) > 0) {
991 fprintf(stderr, "qemu: too many SCSI bus\n");
992 exit(1);
993 }
994
995 esp_init(hwdef->esp_base, 2,
996 espdma_memory_read, espdma_memory_write,
997 espdma, espdma_irq, &esp_reset, &dma_enable);
998
999 qdev_connect_gpio_out(espdma, 0, esp_reset);
1000 qdev_connect_gpio_out(espdma, 1, dma_enable);
1001
1002 if (hwdef->cs_base) {
1003 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
1004 slavio_irq[5]);
1005 }
1006
1007 if (hwdef->dbri_base) {
1008 /* ISDN chip with attached CS4215 audio codec */
1009 /* prom space */
1010 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1011 /* reg space */
1012 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1013 }
1014
1015 if (hwdef->bpp_base) {
1016 /* parallel port */
1017 empty_slot_init(hwdef->bpp_base, 0x20);
1018 }
1019
1020 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1021 RAM_size);
1022
1023 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1024 boot_device, RAM_size, kernel_size, graphic_width,
1025 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1026 "Sun4m");
1027
1028 if (hwdef->ecc_base)
1029 ecc_init(hwdef->ecc_base, slavio_irq[28],
1030 hwdef->ecc_version);
1031
1032 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1033 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1034 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1035 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1036 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1037 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1038 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1040 if (kernel_cmdline) {
1041 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1042 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1043 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1044 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1045 strlen(kernel_cmdline) + 1);
1046 } else {
1047 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1048 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1049 }
1050 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1051 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1052 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1053 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1054 }
1055
1056 enum {
1057 ss2_id = 0,
1058 ss5_id = 32,
1059 vger_id,
1060 lx_id,
1061 ss4_id,
1062 scls_id,
1063 sbook_id,
1064 ss10_id = 64,
1065 ss20_id,
1066 ss600mp_id,
1067 ss1000_id = 96,
1068 ss2000_id,
1069 };
1070
1071 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1072 /* SS-5 */
1073 {
1074 .iommu_base = 0x10000000,
1075 .iommu_pad_base = 0x10004000,
1076 .iommu_pad_len = 0x0fffb000,
1077 .tcx_base = 0x50000000,
1078 .cs_base = 0x6c000000,
1079 .slavio_base = 0x70000000,
1080 .ms_kb_base = 0x71000000,
1081 .serial_base = 0x71100000,
1082 .nvram_base = 0x71200000,
1083 .fd_base = 0x71400000,
1084 .counter_base = 0x71d00000,
1085 .intctl_base = 0x71e00000,
1086 .idreg_base = 0x78000000,
1087 .dma_base = 0x78400000,
1088 .esp_base = 0x78800000,
1089 .le_base = 0x78c00000,
1090 .apc_base = 0x6a000000,
1091 .afx_base = 0x6e000000,
1092 .aux1_base = 0x71900000,
1093 .aux2_base = 0x71910000,
1094 .nvram_machine_id = 0x80,
1095 .machine_id = ss5_id,
1096 .iommu_version = 0x05000000,
1097 .max_mem = 0x10000000,
1098 .default_cpu_model = "Fujitsu MB86904",
1099 },
1100 /* SS-10 */
1101 {
1102 .iommu_base = 0xfe0000000ULL,
1103 .tcx_base = 0xe20000000ULL,
1104 .slavio_base = 0xff0000000ULL,
1105 .ms_kb_base = 0xff1000000ULL,
1106 .serial_base = 0xff1100000ULL,
1107 .nvram_base = 0xff1200000ULL,
1108 .fd_base = 0xff1700000ULL,
1109 .counter_base = 0xff1300000ULL,
1110 .intctl_base = 0xff1400000ULL,
1111 .idreg_base = 0xef0000000ULL,
1112 .dma_base = 0xef0400000ULL,
1113 .esp_base = 0xef0800000ULL,
1114 .le_base = 0xef0c00000ULL,
1115 .apc_base = 0xefa000000ULL, // XXX should not exist
1116 .aux1_base = 0xff1800000ULL,
1117 .aux2_base = 0xff1a01000ULL,
1118 .ecc_base = 0xf00000000ULL,
1119 .ecc_version = 0x10000000, // version 0, implementation 1
1120 .nvram_machine_id = 0x72,
1121 .machine_id = ss10_id,
1122 .iommu_version = 0x03000000,
1123 .max_mem = 0xf00000000ULL,
1124 .default_cpu_model = "TI SuperSparc II",
1125 },
1126 /* SS-600MP */
1127 {
1128 .iommu_base = 0xfe0000000ULL,
1129 .tcx_base = 0xe20000000ULL,
1130 .slavio_base = 0xff0000000ULL,
1131 .ms_kb_base = 0xff1000000ULL,
1132 .serial_base = 0xff1100000ULL,
1133 .nvram_base = 0xff1200000ULL,
1134 .counter_base = 0xff1300000ULL,
1135 .intctl_base = 0xff1400000ULL,
1136 .dma_base = 0xef0081000ULL,
1137 .esp_base = 0xef0080000ULL,
1138 .le_base = 0xef0060000ULL,
1139 .apc_base = 0xefa000000ULL, // XXX should not exist
1140 .aux1_base = 0xff1800000ULL,
1141 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1142 .ecc_base = 0xf00000000ULL,
1143 .ecc_version = 0x00000000, // version 0, implementation 0
1144 .nvram_machine_id = 0x71,
1145 .machine_id = ss600mp_id,
1146 .iommu_version = 0x01000000,
1147 .max_mem = 0xf00000000ULL,
1148 .default_cpu_model = "TI SuperSparc II",
1149 },
1150 /* SS-20 */
1151 {
1152 .iommu_base = 0xfe0000000ULL,
1153 .tcx_base = 0xe20000000ULL,
1154 .slavio_base = 0xff0000000ULL,
1155 .ms_kb_base = 0xff1000000ULL,
1156 .serial_base = 0xff1100000ULL,
1157 .nvram_base = 0xff1200000ULL,
1158 .fd_base = 0xff1700000ULL,
1159 .counter_base = 0xff1300000ULL,
1160 .intctl_base = 0xff1400000ULL,
1161 .idreg_base = 0xef0000000ULL,
1162 .dma_base = 0xef0400000ULL,
1163 .esp_base = 0xef0800000ULL,
1164 .le_base = 0xef0c00000ULL,
1165 .bpp_base = 0xef4800000ULL,
1166 .apc_base = 0xefa000000ULL, // XXX should not exist
1167 .aux1_base = 0xff1800000ULL,
1168 .aux2_base = 0xff1a01000ULL,
1169 .dbri_base = 0xee0000000ULL,
1170 .sx_base = 0xf80000000ULL,
1171 .vsimm = {
1172 {
1173 .reg_base = 0x9c000000ULL,
1174 .vram_base = 0xfc000000ULL
1175 }, {
1176 .reg_base = 0x90000000ULL,
1177 .vram_base = 0xf0000000ULL
1178 }, {
1179 .reg_base = 0x94000000ULL
1180 }, {
1181 .reg_base = 0x98000000ULL
1182 }
1183 },
1184 .ecc_base = 0xf00000000ULL,
1185 .ecc_version = 0x20000000, // version 0, implementation 2
1186 .nvram_machine_id = 0x72,
1187 .machine_id = ss20_id,
1188 .iommu_version = 0x13000000,
1189 .max_mem = 0xf00000000ULL,
1190 .default_cpu_model = "TI SuperSparc II",
1191 },
1192 /* Voyager */
1193 {
1194 .iommu_base = 0x10000000,
1195 .tcx_base = 0x50000000,
1196 .slavio_base = 0x70000000,
1197 .ms_kb_base = 0x71000000,
1198 .serial_base = 0x71100000,
1199 .nvram_base = 0x71200000,
1200 .fd_base = 0x71400000,
1201 .counter_base = 0x71d00000,
1202 .intctl_base = 0x71e00000,
1203 .idreg_base = 0x78000000,
1204 .dma_base = 0x78400000,
1205 .esp_base = 0x78800000,
1206 .le_base = 0x78c00000,
1207 .apc_base = 0x71300000, // pmc
1208 .aux1_base = 0x71900000,
1209 .aux2_base = 0x71910000,
1210 .nvram_machine_id = 0x80,
1211 .machine_id = vger_id,
1212 .iommu_version = 0x05000000,
1213 .max_mem = 0x10000000,
1214 .default_cpu_model = "Fujitsu MB86904",
1215 },
1216 /* LX */
1217 {
1218 .iommu_base = 0x10000000,
1219 .iommu_pad_base = 0x10004000,
1220 .iommu_pad_len = 0x0fffb000,
1221 .tcx_base = 0x50000000,
1222 .slavio_base = 0x70000000,
1223 .ms_kb_base = 0x71000000,
1224 .serial_base = 0x71100000,
1225 .nvram_base = 0x71200000,
1226 .fd_base = 0x71400000,
1227 .counter_base = 0x71d00000,
1228 .intctl_base = 0x71e00000,
1229 .idreg_base = 0x78000000,
1230 .dma_base = 0x78400000,
1231 .esp_base = 0x78800000,
1232 .le_base = 0x78c00000,
1233 .aux1_base = 0x71900000,
1234 .aux2_base = 0x71910000,
1235 .nvram_machine_id = 0x80,
1236 .machine_id = lx_id,
1237 .iommu_version = 0x04000000,
1238 .max_mem = 0x10000000,
1239 .default_cpu_model = "TI MicroSparc I",
1240 },
1241 /* SS-4 */
1242 {
1243 .iommu_base = 0x10000000,
1244 .tcx_base = 0x50000000,
1245 .cs_base = 0x6c000000,
1246 .slavio_base = 0x70000000,
1247 .ms_kb_base = 0x71000000,
1248 .serial_base = 0x71100000,
1249 .nvram_base = 0x71200000,
1250 .fd_base = 0x71400000,
1251 .counter_base = 0x71d00000,
1252 .intctl_base = 0x71e00000,
1253 .idreg_base = 0x78000000,
1254 .dma_base = 0x78400000,
1255 .esp_base = 0x78800000,
1256 .le_base = 0x78c00000,
1257 .apc_base = 0x6a000000,
1258 .aux1_base = 0x71900000,
1259 .aux2_base = 0x71910000,
1260 .nvram_machine_id = 0x80,
1261 .machine_id = ss4_id,
1262 .iommu_version = 0x05000000,
1263 .max_mem = 0x10000000,
1264 .default_cpu_model = "Fujitsu MB86904",
1265 },
1266 /* SPARCClassic */
1267 {
1268 .iommu_base = 0x10000000,
1269 .tcx_base = 0x50000000,
1270 .slavio_base = 0x70000000,
1271 .ms_kb_base = 0x71000000,
1272 .serial_base = 0x71100000,
1273 .nvram_base = 0x71200000,
1274 .fd_base = 0x71400000,
1275 .counter_base = 0x71d00000,
1276 .intctl_base = 0x71e00000,
1277 .idreg_base = 0x78000000,
1278 .dma_base = 0x78400000,
1279 .esp_base = 0x78800000,
1280 .le_base = 0x78c00000,
1281 .apc_base = 0x6a000000,
1282 .aux1_base = 0x71900000,
1283 .aux2_base = 0x71910000,
1284 .nvram_machine_id = 0x80,
1285 .machine_id = scls_id,
1286 .iommu_version = 0x05000000,
1287 .max_mem = 0x10000000,
1288 .default_cpu_model = "TI MicroSparc I",
1289 },
1290 /* SPARCbook */
1291 {
1292 .iommu_base = 0x10000000,
1293 .tcx_base = 0x50000000, // XXX
1294 .slavio_base = 0x70000000,
1295 .ms_kb_base = 0x71000000,
1296 .serial_base = 0x71100000,
1297 .nvram_base = 0x71200000,
1298 .fd_base = 0x71400000,
1299 .counter_base = 0x71d00000,
1300 .intctl_base = 0x71e00000,
1301 .idreg_base = 0x78000000,
1302 .dma_base = 0x78400000,
1303 .esp_base = 0x78800000,
1304 .le_base = 0x78c00000,
1305 .apc_base = 0x6a000000,
1306 .aux1_base = 0x71900000,
1307 .aux2_base = 0x71910000,
1308 .nvram_machine_id = 0x80,
1309 .machine_id = sbook_id,
1310 .iommu_version = 0x05000000,
1311 .max_mem = 0x10000000,
1312 .default_cpu_model = "TI MicroSparc I",
1313 },
1314 };
1315
1316 /* SPARCstation 5 hardware initialisation */
1317 static void ss5_init(QEMUMachineInitArgs *args)
1318 {
1319 ram_addr_t RAM_size = args->ram_size;
1320 const char *cpu_model = args->cpu_model;
1321 const char *kernel_filename = args->kernel_filename;
1322 const char *kernel_cmdline = args->kernel_cmdline;
1323 const char *initrd_filename = args->initrd_filename;
1324 const char *boot_device = args->boot_device;
1325 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1326 kernel_cmdline, initrd_filename, cpu_model);
1327 }
1328
1329 /* SPARCstation 10 hardware initialisation */
1330 static void ss10_init(QEMUMachineInitArgs *args)
1331 {
1332 ram_addr_t RAM_size = args->ram_size;
1333 const char *cpu_model = args->cpu_model;
1334 const char *kernel_filename = args->kernel_filename;
1335 const char *kernel_cmdline = args->kernel_cmdline;
1336 const char *initrd_filename = args->initrd_filename;
1337 const char *boot_device = args->boot_device;
1338 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1339 kernel_cmdline, initrd_filename, cpu_model);
1340 }
1341
1342 /* SPARCserver 600MP hardware initialisation */
1343 static void ss600mp_init(QEMUMachineInitArgs *args)
1344 {
1345 ram_addr_t RAM_size = args->ram_size;
1346 const char *cpu_model = args->cpu_model;
1347 const char *kernel_filename = args->kernel_filename;
1348 const char *kernel_cmdline = args->kernel_cmdline;
1349 const char *initrd_filename = args->initrd_filename;
1350 const char *boot_device = args->boot_device;
1351 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1352 kernel_cmdline, initrd_filename, cpu_model);
1353 }
1354
1355 /* SPARCstation 20 hardware initialisation */
1356 static void ss20_init(QEMUMachineInitArgs *args)
1357 {
1358 ram_addr_t RAM_size = args->ram_size;
1359 const char *cpu_model = args->cpu_model;
1360 const char *kernel_filename = args->kernel_filename;
1361 const char *kernel_cmdline = args->kernel_cmdline;
1362 const char *initrd_filename = args->initrd_filename;
1363 const char *boot_device = args->boot_device;
1364 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1365 kernel_cmdline, initrd_filename, cpu_model);
1366 }
1367
1368 /* SPARCstation Voyager hardware initialisation */
1369 static void vger_init(QEMUMachineInitArgs *args)
1370 {
1371 ram_addr_t RAM_size = args->ram_size;
1372 const char *cpu_model = args->cpu_model;
1373 const char *kernel_filename = args->kernel_filename;
1374 const char *kernel_cmdline = args->kernel_cmdline;
1375 const char *initrd_filename = args->initrd_filename;
1376 const char *boot_device = args->boot_device;
1377 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1378 kernel_cmdline, initrd_filename, cpu_model);
1379 }
1380
1381 /* SPARCstation LX hardware initialisation */
1382 static void ss_lx_init(QEMUMachineInitArgs *args)
1383 {
1384 ram_addr_t RAM_size = args->ram_size;
1385 const char *cpu_model = args->cpu_model;
1386 const char *kernel_filename = args->kernel_filename;
1387 const char *kernel_cmdline = args->kernel_cmdline;
1388 const char *initrd_filename = args->initrd_filename;
1389 const char *boot_device = args->boot_device;
1390 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1391 kernel_cmdline, initrd_filename, cpu_model);
1392 }
1393
1394 /* SPARCstation 4 hardware initialisation */
1395 static void ss4_init(QEMUMachineInitArgs *args)
1396 {
1397 ram_addr_t RAM_size = args->ram_size;
1398 const char *cpu_model = args->cpu_model;
1399 const char *kernel_filename = args->kernel_filename;
1400 const char *kernel_cmdline = args->kernel_cmdline;
1401 const char *initrd_filename = args->initrd_filename;
1402 const char *boot_device = args->boot_device;
1403 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1404 kernel_cmdline, initrd_filename, cpu_model);
1405 }
1406
1407 /* SPARCClassic hardware initialisation */
1408 static void scls_init(QEMUMachineInitArgs *args)
1409 {
1410 ram_addr_t RAM_size = args->ram_size;
1411 const char *cpu_model = args->cpu_model;
1412 const char *kernel_filename = args->kernel_filename;
1413 const char *kernel_cmdline = args->kernel_cmdline;
1414 const char *initrd_filename = args->initrd_filename;
1415 const char *boot_device = args->boot_device;
1416 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1417 kernel_cmdline, initrd_filename, cpu_model);
1418 }
1419
1420 /* SPARCbook hardware initialisation */
1421 static void sbook_init(QEMUMachineInitArgs *args)
1422 {
1423 ram_addr_t RAM_size = args->ram_size;
1424 const char *cpu_model = args->cpu_model;
1425 const char *kernel_filename = args->kernel_filename;
1426 const char *kernel_cmdline = args->kernel_cmdline;
1427 const char *initrd_filename = args->initrd_filename;
1428 const char *boot_device = args->boot_device;
1429 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1430 kernel_cmdline, initrd_filename, cpu_model);
1431 }
1432
1433 static QEMUMachine ss5_machine = {
1434 .name = "SS-5",
1435 .desc = "Sun4m platform, SPARCstation 5",
1436 .init = ss5_init,
1437 .block_default_type = IF_SCSI,
1438 .is_default = 1,
1439 DEFAULT_MACHINE_OPTIONS,
1440 };
1441
1442 static QEMUMachine ss10_machine = {
1443 .name = "SS-10",
1444 .desc = "Sun4m platform, SPARCstation 10",
1445 .init = ss10_init,
1446 .block_default_type = IF_SCSI,
1447 .max_cpus = 4,
1448 DEFAULT_MACHINE_OPTIONS,
1449 };
1450
1451 static QEMUMachine ss600mp_machine = {
1452 .name = "SS-600MP",
1453 .desc = "Sun4m platform, SPARCserver 600MP",
1454 .init = ss600mp_init,
1455 .block_default_type = IF_SCSI,
1456 .max_cpus = 4,
1457 DEFAULT_MACHINE_OPTIONS,
1458 };
1459
1460 static QEMUMachine ss20_machine = {
1461 .name = "SS-20",
1462 .desc = "Sun4m platform, SPARCstation 20",
1463 .init = ss20_init,
1464 .block_default_type = IF_SCSI,
1465 .max_cpus = 4,
1466 DEFAULT_MACHINE_OPTIONS,
1467 };
1468
1469 static QEMUMachine voyager_machine = {
1470 .name = "Voyager",
1471 .desc = "Sun4m platform, SPARCstation Voyager",
1472 .init = vger_init,
1473 .block_default_type = IF_SCSI,
1474 DEFAULT_MACHINE_OPTIONS,
1475 };
1476
1477 static QEMUMachine ss_lx_machine = {
1478 .name = "LX",
1479 .desc = "Sun4m platform, SPARCstation LX",
1480 .init = ss_lx_init,
1481 .block_default_type = IF_SCSI,
1482 DEFAULT_MACHINE_OPTIONS,
1483 };
1484
1485 static QEMUMachine ss4_machine = {
1486 .name = "SS-4",
1487 .desc = "Sun4m platform, SPARCstation 4",
1488 .init = ss4_init,
1489 .block_default_type = IF_SCSI,
1490 DEFAULT_MACHINE_OPTIONS,
1491 };
1492
1493 static QEMUMachine scls_machine = {
1494 .name = "SPARCClassic",
1495 .desc = "Sun4m platform, SPARCClassic",
1496 .init = scls_init,
1497 .block_default_type = IF_SCSI,
1498 DEFAULT_MACHINE_OPTIONS,
1499 };
1500
1501 static QEMUMachine sbook_machine = {
1502 .name = "SPARCbook",
1503 .desc = "Sun4m platform, SPARCbook",
1504 .init = sbook_init,
1505 .block_default_type = IF_SCSI,
1506 DEFAULT_MACHINE_OPTIONS,
1507 };
1508
1509 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1510 /* SS-1000 */
1511 {
1512 .iounit_bases = {
1513 0xfe0200000ULL,
1514 0xfe1200000ULL,
1515 0xfe2200000ULL,
1516 0xfe3200000ULL,
1517 -1,
1518 },
1519 .tcx_base = 0x820000000ULL,
1520 .slavio_base = 0xf00000000ULL,
1521 .ms_kb_base = 0xf00240000ULL,
1522 .serial_base = 0xf00200000ULL,
1523 .nvram_base = 0xf00280000ULL,
1524 .counter_base = 0xf00300000ULL,
1525 .espdma_base = 0x800081000ULL,
1526 .esp_base = 0x800080000ULL,
1527 .ledma_base = 0x800040000ULL,
1528 .le_base = 0x800060000ULL,
1529 .sbi_base = 0xf02800000ULL,
1530 .nvram_machine_id = 0x80,
1531 .machine_id = ss1000_id,
1532 .iounit_version = 0x03000000,
1533 .max_mem = 0xf00000000ULL,
1534 .default_cpu_model = "TI SuperSparc II",
1535 },
1536 /* SS-2000 */
1537 {
1538 .iounit_bases = {
1539 0xfe0200000ULL,
1540 0xfe1200000ULL,
1541 0xfe2200000ULL,
1542 0xfe3200000ULL,
1543 0xfe4200000ULL,
1544 },
1545 .tcx_base = 0x820000000ULL,
1546 .slavio_base = 0xf00000000ULL,
1547 .ms_kb_base = 0xf00240000ULL,
1548 .serial_base = 0xf00200000ULL,
1549 .nvram_base = 0xf00280000ULL,
1550 .counter_base = 0xf00300000ULL,
1551 .espdma_base = 0x800081000ULL,
1552 .esp_base = 0x800080000ULL,
1553 .ledma_base = 0x800040000ULL,
1554 .le_base = 0x800060000ULL,
1555 .sbi_base = 0xf02800000ULL,
1556 .nvram_machine_id = 0x80,
1557 .machine_id = ss2000_id,
1558 .iounit_version = 0x03000000,
1559 .max_mem = 0xf00000000ULL,
1560 .default_cpu_model = "TI SuperSparc II",
1561 },
1562 };
1563
1564 static DeviceState *sbi_init(hwaddr addr, qemu_irq **parent_irq)
1565 {
1566 DeviceState *dev;
1567 SysBusDevice *s;
1568 unsigned int i;
1569
1570 dev = qdev_create(NULL, "sbi");
1571 qdev_init_nofail(dev);
1572
1573 s = SYS_BUS_DEVICE(dev);
1574
1575 for (i = 0; i < MAX_CPUS; i++) {
1576 sysbus_connect_irq(s, i, *parent_irq[i]);
1577 }
1578
1579 sysbus_mmio_map(s, 0, addr);
1580
1581 return dev;
1582 }
1583
1584 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1585 const char *boot_device,
1586 const char *kernel_filename,
1587 const char *kernel_cmdline,
1588 const char *initrd_filename, const char *cpu_model)
1589 {
1590 unsigned int i;
1591 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1592 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1593 espdma_irq, ledma_irq;
1594 qemu_irq esp_reset, dma_enable;
1595 unsigned long kernel_size;
1596 void *fw_cfg;
1597 DeviceState *dev;
1598
1599 /* init CPUs */
1600 if (!cpu_model)
1601 cpu_model = hwdef->default_cpu_model;
1602
1603 for(i = 0; i < smp_cpus; i++) {
1604 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1605 }
1606
1607 for (i = smp_cpus; i < MAX_CPUS; i++)
1608 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1609
1610 /* set up devices */
1611 ram_init(0, RAM_size, hwdef->max_mem);
1612
1613 prom_init(hwdef->slavio_base, bios_name);
1614
1615 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1616
1617 for (i = 0; i < 32; i++) {
1618 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1619 }
1620 for (i = 0; i < MAX_CPUS; i++) {
1621 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1622 }
1623
1624 for (i = 0; i < MAX_IOUNITS; i++)
1625 if (hwdef->iounit_bases[i] != (hwaddr)-1)
1626 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1627 hwdef->iounit_version,
1628 sbi_irq[0]);
1629
1630 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1631 iounits[0], &espdma_irq, 0);
1632
1633 /* should be lebuffer instead */
1634 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1635 iounits[0], &ledma_irq, 0);
1636
1637 if (graphic_depth != 8 && graphic_depth != 24) {
1638 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1639 exit (1);
1640 }
1641 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1642 graphic_depth);
1643
1644 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1645
1646 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1647
1648 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1649
1650 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1651 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1652 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1653 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1654 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1655 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1656
1657 if (drive_get_max_bus(IF_SCSI) > 0) {
1658 fprintf(stderr, "qemu: too many SCSI bus\n");
1659 exit(1);
1660 }
1661
1662 esp_init(hwdef->esp_base, 2,
1663 espdma_memory_read, espdma_memory_write,
1664 espdma, espdma_irq, &esp_reset, &dma_enable);
1665
1666 qdev_connect_gpio_out(espdma, 0, esp_reset);
1667 qdev_connect_gpio_out(espdma, 1, dma_enable);
1668
1669 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1670 RAM_size);
1671
1672 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1673 boot_device, RAM_size, kernel_size, graphic_width,
1674 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1675 "Sun4d");
1676
1677 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1678 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1679 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1680 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1681 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1682 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1683 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1684 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1685 if (kernel_cmdline) {
1686 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1687 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1688 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1689 } else {
1690 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1691 }
1692 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1693 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1694 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1695 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1696 }
1697
1698 /* SPARCserver 1000 hardware initialisation */
1699 static void ss1000_init(QEMUMachineInitArgs *args)
1700 {
1701 ram_addr_t RAM_size = args->ram_size;
1702 const char *cpu_model = args->cpu_model;
1703 const char *kernel_filename = args->kernel_filename;
1704 const char *kernel_cmdline = args->kernel_cmdline;
1705 const char *initrd_filename = args->initrd_filename;
1706 const char *boot_device = args->boot_device;
1707 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1708 kernel_cmdline, initrd_filename, cpu_model);
1709 }
1710
1711 /* SPARCcenter 2000 hardware initialisation */
1712 static void ss2000_init(QEMUMachineInitArgs *args)
1713 {
1714 ram_addr_t RAM_size = args->ram_size;
1715 const char *cpu_model = args->cpu_model;
1716 const char *kernel_filename = args->kernel_filename;
1717 const char *kernel_cmdline = args->kernel_cmdline;
1718 const char *initrd_filename = args->initrd_filename;
1719 const char *boot_device = args->boot_device;
1720 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1721 kernel_cmdline, initrd_filename, cpu_model);
1722 }
1723
1724 static QEMUMachine ss1000_machine = {
1725 .name = "SS-1000",
1726 .desc = "Sun4d platform, SPARCserver 1000",
1727 .init = ss1000_init,
1728 .block_default_type = IF_SCSI,
1729 .max_cpus = 8,
1730 DEFAULT_MACHINE_OPTIONS,
1731 };
1732
1733 static QEMUMachine ss2000_machine = {
1734 .name = "SS-2000",
1735 .desc = "Sun4d platform, SPARCcenter 2000",
1736 .init = ss2000_init,
1737 .block_default_type = IF_SCSI,
1738 .max_cpus = 20,
1739 DEFAULT_MACHINE_OPTIONS,
1740 };
1741
1742 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1743 /* SS-2 */
1744 {
1745 .iommu_base = 0xf8000000,
1746 .tcx_base = 0xfe000000,
1747 .slavio_base = 0xf6000000,
1748 .intctl_base = 0xf5000000,
1749 .counter_base = 0xf3000000,
1750 .ms_kb_base = 0xf0000000,
1751 .serial_base = 0xf1000000,
1752 .nvram_base = 0xf2000000,
1753 .fd_base = 0xf7200000,
1754 .dma_base = 0xf8400000,
1755 .esp_base = 0xf8800000,
1756 .le_base = 0xf8c00000,
1757 .aux1_base = 0xf7400003,
1758 .nvram_machine_id = 0x55,
1759 .machine_id = ss2_id,
1760 .max_mem = 0x10000000,
1761 .default_cpu_model = "Cypress CY7C601",
1762 },
1763 };
1764
1765 static DeviceState *sun4c_intctl_init(hwaddr addr,
1766 qemu_irq *parent_irq)
1767 {
1768 DeviceState *dev;
1769 SysBusDevice *s;
1770 unsigned int i;
1771
1772 dev = qdev_create(NULL, "sun4c_intctl");
1773 qdev_init_nofail(dev);
1774
1775 s = SYS_BUS_DEVICE(dev);
1776
1777 for (i = 0; i < MAX_PILS; i++) {
1778 sysbus_connect_irq(s, i, parent_irq[i]);
1779 }
1780 sysbus_mmio_map(s, 0, addr);
1781
1782 return dev;
1783 }
1784
1785 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1786 const char *boot_device,
1787 const char *kernel_filename,
1788 const char *kernel_cmdline,
1789 const char *initrd_filename, const char *cpu_model)
1790 {
1791 void *iommu, *espdma, *ledma, *nvram;
1792 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1793 qemu_irq esp_reset, dma_enable;
1794 qemu_irq fdc_tc;
1795 unsigned long kernel_size;
1796 DriveInfo *fd[MAX_FD];
1797 void *fw_cfg;
1798 DeviceState *dev;
1799 unsigned int i;
1800
1801 /* init CPU */
1802 if (!cpu_model)
1803 cpu_model = hwdef->default_cpu_model;
1804
1805 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1806
1807 /* set up devices */
1808 ram_init(0, RAM_size, hwdef->max_mem);
1809
1810 prom_init(hwdef->slavio_base, bios_name);
1811
1812 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1813
1814 for (i = 0; i < 8; i++) {
1815 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1816 }
1817
1818 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1819 slavio_irq[1]);
1820
1821 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1822 iommu, &espdma_irq, 0);
1823
1824 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1825 slavio_irq[3], iommu, &ledma_irq, 1);
1826
1827 if (graphic_depth != 8 && graphic_depth != 24) {
1828 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1829 exit (1);
1830 }
1831 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1832 graphic_depth);
1833
1834 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1835
1836 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1837
1838 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1839 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1840 /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device
1841 Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */
1842 escc_init(hwdef->serial_base, slavio_irq[1],
1843 slavio_irq[1], serial_hds[0], serial_hds[1],
1844 ESCC_CLOCK, 1);
1845
1846 if (hwdef->fd_base != (hwaddr)-1) {
1847 /* there is zero or one floppy drive */
1848 memset(fd, 0, sizeof(fd));
1849 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1850 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1851 &fdc_tc);
1852 } else {
1853 fdc_tc = *qemu_allocate_irqs(dummy_fdc_tc, NULL, 1);
1854 }
1855
1856 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1857
1858 if (drive_get_max_bus(IF_SCSI) > 0) {
1859 fprintf(stderr, "qemu: too many SCSI bus\n");
1860 exit(1);
1861 }
1862
1863 esp_init(hwdef->esp_base, 2,
1864 espdma_memory_read, espdma_memory_write,
1865 espdma, espdma_irq, &esp_reset, &dma_enable);
1866
1867 qdev_connect_gpio_out(espdma, 0, esp_reset);
1868 qdev_connect_gpio_out(espdma, 1, dma_enable);
1869
1870 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1871 RAM_size);
1872
1873 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1874 boot_device, RAM_size, kernel_size, graphic_width,
1875 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1876 "Sun4c");
1877
1878 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1879 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus);
1880 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1881 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1882 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1883 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1884 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1885 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1886 if (kernel_cmdline) {
1887 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1888 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1889 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, kernel_cmdline);
1890 } else {
1891 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1892 }
1893 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1894 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1895 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1896 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1897 }
1898
1899 /* SPARCstation 2 hardware initialisation */
1900 static void ss2_init(QEMUMachineInitArgs *args)
1901 {
1902 ram_addr_t RAM_size = args->ram_size;
1903 const char *cpu_model = args->cpu_model;
1904 const char *kernel_filename = args->kernel_filename;
1905 const char *kernel_cmdline = args->kernel_cmdline;
1906 const char *initrd_filename = args->initrd_filename;
1907 const char *boot_device = args->boot_device;
1908 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1909 kernel_cmdline, initrd_filename, cpu_model);
1910 }
1911
1912 static QEMUMachine ss2_machine = {
1913 .name = "SS-2",
1914 .desc = "Sun4c platform, SPARCstation 2",
1915 .init = ss2_init,
1916 .block_default_type = IF_SCSI,
1917 DEFAULT_MACHINE_OPTIONS,
1918 };
1919
1920 static void sun4m_register_types(void)
1921 {
1922 type_register_static(&idreg_info);
1923 type_register_static(&afx_info);
1924 type_register_static(&prom_info);
1925 type_register_static(&ram_info);
1926 }
1927
1928 static void ss2_machine_init(void)
1929 {
1930 qemu_register_machine(&ss5_machine);
1931 qemu_register_machine(&ss10_machine);
1932 qemu_register_machine(&ss600mp_machine);
1933 qemu_register_machine(&ss20_machine);
1934 qemu_register_machine(&voyager_machine);
1935 qemu_register_machine(&ss_lx_machine);
1936 qemu_register_machine(&ss4_machine);
1937 qemu_register_machine(&scls_machine);
1938 qemu_register_machine(&sbook_machine);
1939 qemu_register_machine(&ss1000_machine);
1940 qemu_register_machine(&ss2000_machine);
1941 qemu_register_machine(&ss2_machine);
1942 }
1943
1944 type_init(sun4m_register_types)
1945 machine_init(ss2_machine_init);
Qemu copy for testing