hw/sparc32_dma.c

   1 /*
   2  * QEMU Sparc32 DMA controller emulation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 /* debug DMA */
  27 //#define DEBUG_DMA
  28
  29 /*
  30  * This is the DMA controller part of chip STP2000 (Master I/O), also
  31  * produced as NCR89C100. See
  32  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C100.txt
  33  * and
  34  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/DMA2.txt
  35  */
  36
  37 #ifdef DEBUG_DMA
  38 #define DPRINTF(fmt, args...) \
  39 do { printf("DMA: " fmt , ##args); } while (0)
  40 #else
  41 #define DPRINTF(fmt, args...)
  42 #endif
  43
  44 #define DMA_REGS 4
  45 #define DMA_SIZE (4 * sizeof(uint32_t))
  46 #define DMA_MAXADDR (DMA_SIZE - 1)
  47
  48 #define DMA_VER 0xa0000000
  49 #define DMA_INTR 1
  50 #define DMA_INTREN 0x10
  51 #define DMA_WRITE_MEM 0x100
  52 #define DMA_LOADED 0x04000000
  53 #define DMA_DRAIN_FIFO 0x40
  54 #define DMA_RESET 0x80
  55
  56 typedef struct DMAState DMAState;
  57
  58 struct DMAState {
  59     uint32_t dmaregs[DMA_REGS];
  60     qemu_irq irq;
  61     void *iommu;
  62     qemu_irq dev_reset;
  63 };
  64
  65 /* Note: on sparc, the lance 16 bit bus is swapped */
  66 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  67                        uint8_t *buf, int len, int do_bswap)
  68 {
  69     DMAState *s = opaque;
  70     int i;
  71
  72     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
  73             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  74     addr |= s->dmaregs[3];
  75     if (do_bswap) {
  76         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  77     } else {
  78         addr &= ~1;
  79         len &= ~1;
  80         sparc_iommu_memory_read(s->iommu, addr, buf, len);
  81         for(i = 0; i < len; i += 2) {
  82             bswap16s((uint16_t *)(buf + i));
  83         }
  84     }
  85 }
  86
  87 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
  88                         uint8_t *buf, int len, int do_bswap)
  89 {
  90     DMAState *s = opaque;
  91     int l, i;
  92     uint16_t tmp_buf[32];
  93
  94     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
  95             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
  96     addr |= s->dmaregs[3];
  97     if (do_bswap) {
  98         sparc_iommu_memory_write(s->iommu, addr, buf, len);
  99     } else {
 100         addr &= ~1;
 101         len &= ~1;
 102         while (len > 0) {
 103             l = len;
 104             if (l > sizeof(tmp_buf))
 105                 l = sizeof(tmp_buf);
 106             for(i = 0; i < l; i += 2) {
 107                 tmp_buf[i >> 1] = bswap16(*(uint16_t *)(buf + i));
 108             }
 109             sparc_iommu_memory_write(s->iommu, addr, (uint8_t *)tmp_buf, l);
 110             len -= l;
 111             buf += l;
 112             addr += l;
 113         }
 114     }
 115 }
 116
 117 static void dma_set_irq(void *opaque, int irq, int level)
 118 {
 119     DMAState *s = opaque;
 120     if (level) {
 121         DPRINTF("Raise IRQ\n");
 122         s->dmaregs[0] |= DMA_INTR;
 123         qemu_irq_raise(s->irq);
 124     } else {
 125         s->dmaregs[0] &= ~DMA_INTR;
 126         DPRINTF("Lower IRQ\n");
 127         qemu_irq_lower(s->irq);
 128     }
 129 }
 130
 131 void espdma_memory_read(void *opaque, uint8_t *buf, int len)
 132 {
 133     DMAState *s = opaque;
 134
 135     DPRINTF("DMA read, direction: %c, addr 0x%8.8x\n",
 136             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 137     sparc_iommu_memory_read(s->iommu, s->dmaregs[1], buf, len);
 138     s->dmaregs[0] |= DMA_INTR;
 139     s->dmaregs[1] += len;
 140 }
 141
 142 void espdma_memory_write(void *opaque, uint8_t *buf, int len)
 143 {
 144     DMAState *s = opaque;
 145
 146     DPRINTF("DMA write, direction: %c, addr 0x%8.8x\n",
 147             s->dmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', s->dmaregs[1]);
 148     sparc_iommu_memory_write(s->iommu, s->dmaregs[1], buf, len);
 149     s->dmaregs[0] |= DMA_INTR;
 150     s->dmaregs[1] += len;
 151 }
 152
 153 static uint32_t dma_mem_readl(void *opaque, target_phys_addr_t addr)
 154 {
 155     DMAState *s = opaque;
 156     uint32_t saddr;
 157
 158     saddr = (addr & DMA_MAXADDR) >> 2;
 159     DPRINTF("read dmareg " TARGET_FMT_plx ": 0x%8.8x\n", addr,
 160             s->dmaregs[saddr]);
 161
 162     return s->dmaregs[saddr];
 163 }
 164
 165 static void dma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 166 {
 167     DMAState *s = opaque;
 168     uint32_t saddr;
 169
 170     saddr = (addr & DMA_MAXADDR) >> 2;
 171     DPRINTF("write dmareg " TARGET_FMT_plx ": 0x%8.8x -> 0x%8.8x\n", addr,
 172             s->dmaregs[saddr], val);
 173     switch (saddr) {
 174     case 0:
 175         if (!(val & DMA_INTREN)) {
 176             DPRINTF("Lower IRQ\n");
 177             qemu_irq_lower(s->irq);
 178         }
 179         if (val & DMA_RESET) {
 180             qemu_irq_raise(s->dev_reset);
 181             qemu_irq_lower(s->dev_reset);
 182         } else if (val & DMA_DRAIN_FIFO) {
 183             val &= ~DMA_DRAIN_FIFO;
 184         } else if (val == 0)
 185             val = DMA_DRAIN_FIFO;
 186         val &= 0x0fffffff;
 187         val |= DMA_VER;
 188         break;
 189     case 1:
 190         s->dmaregs[0] |= DMA_LOADED;
 191         break;
 192     default:
 193         break;
 194     }
 195     s->dmaregs[saddr] = val;
 196 }
 197
 198 static CPUReadMemoryFunc *dma_mem_read[3] = {
 199     dma_mem_readl,
 200     dma_mem_readl,
 201     dma_mem_readl,
 202 };
 203
 204 static CPUWriteMemoryFunc *dma_mem_write[3] = {
 205     dma_mem_writel,
 206     dma_mem_writel,
 207     dma_mem_writel,
 208 };
 209
 210 static void dma_reset(void *opaque)
 211 {
 212     DMAState *s = opaque;
 213
 214     memset(s->dmaregs, 0, DMA_SIZE);
 215     s->dmaregs[0] = DMA_VER;
 216 }
 217
 218 static void dma_save(QEMUFile *f, void *opaque)
 219 {
 220     DMAState *s = opaque;
 221     unsigned int i;
 222
 223     for (i = 0; i < DMA_REGS; i++)
 224         qemu_put_be32s(f, &s->dmaregs[i]);
 225 }
 226
 227 static int dma_load(QEMUFile *f, void *opaque, int version_id)
 228 {
 229     DMAState *s = opaque;
 230     unsigned int i;
 231
 232     if (version_id != 2)
 233         return -EINVAL;
 234     for (i = 0; i < DMA_REGS; i++)
 235         qemu_get_be32s(f, &s->dmaregs[i]);
 236
 237     return 0;
 238 }
 239
 240 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
 241                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset)
 242 {
 243     DMAState *s;
 244     int dma_io_memory;
 245
 246     s = qemu_mallocz(sizeof(DMAState));
 247     if (!s)
 248         return NULL;
 249
 250     s->irq = parent_irq;
 251     s->iommu = iommu;
 252
 253     dma_io_memory = cpu_register_io_memory(0, dma_mem_read, dma_mem_write, s);
 254     cpu_register_physical_memory(daddr, DMA_SIZE, dma_io_memory);
 255
 256     register_savevm("sparc32_dma", daddr, 2, dma_save, dma_load, s);
 257     qemu_register_reset(dma_reset, s);
 258     *dev_irq = qemu_allocate_irqs(dma_set_irq, s, 1);
 259
 260     *reset = &s->dev_reset;
 261
 262     return s;
 263 }