hw/ssi/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59 #define R_CONFIG_RSVD       (0x7bf40000)
  60
  61 /* interrupt mechanism */
  62 #define R_INTR_STATUS       (0x04 / 4)
  63 #define R_INTR_EN           (0x08 / 4)
  64 #define R_INTR_DIS          (0x0C / 4)
  65 #define R_INTR_MASK         (0x10 / 4)
  66 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  67 #define IXR_RX_FIFO_FULL        (1 << 5)
  68 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  69 #define IXR_TX_FIFO_FULL        (1 << 3)
  70 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  71 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  72 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  73 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  74
  75 #define R_EN                (0x14 / 4)
  76 #define R_DELAY             (0x18 / 4)
  77 #define R_TX_DATA           (0x1C / 4)
  78 #define R_RX_DATA           (0x20 / 4)
  79 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  80 #define R_TX_THRES          (0x28 / 4)
  81 #define R_RX_THRES          (0x2C / 4)
  82 #define R_TXD1              (0x80 / 4)
  83 #define R_TXD2              (0x84 / 4)
  84 #define R_TXD3              (0x88 / 4)
  85
  86 #define R_LQSPI_CFG         (0xa0 / 4)
  87 #define R_LQSPI_CFG_RESET       0x03A002EB
  88 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  89 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  90 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  91 #define LQSPI_CFG_U_PAGE        (1 << 28)
  92 #define LQSPI_CFG_MODE_EN       (1 << 25)
  93 #define LQSPI_CFG_MODE_WIDTH    8
  94 #define LQSPI_CFG_MODE_SHIFT    16
  95 #define LQSPI_CFG_DUMMY_WIDTH   3
  96 #define LQSPI_CFG_DUMMY_SHIFT   8
  97 #define LQSPI_CFG_INST_CODE     0xFF
  98
  99 #define R_LQSPI_STS         (0xA4 / 4)
 100 #define LQSPI_STS_WR_RECVD      (1 << 1)
 101
 102 #define R_MOD_ID            (0xFC / 4)
 103
 104 #define R_MAX (R_MOD_ID+1)
 105
 106 /* size of TXRX FIFOs */
 107 #define RXFF_A          32
 108 #define TXFF_A          32
 109
 110 #define RXFF_A_Q          (64 * 4)
 111 #define TXFF_A_Q          (64 * 4)
 112
 113 /* 16MB per linear region */
 114 #define LQSPI_ADDRESS_BITS 24
 115 /* Bite off 4k chunks at a time */
 116 #define LQSPI_CACHE_SIZE 1024
 117
 118 #define SNOOP_CHECKING 0xFF
 119 #define SNOOP_NONE 0xFE
 120 #define SNOOP_STRIPING 0
 121
 122 typedef enum {
 123     READ = 0x3,
 124     FAST_READ = 0xb,
 125     DOR = 0x3b,
 126     QOR = 0x6b,
 127     DIOR = 0xbb,
 128     QIOR = 0xeb,
 129
 130     PP = 0x2,
 131     DPP = 0xa2,
 132     QPP = 0x32,
 133 } FlashCMD;
 134
 135 typedef struct {
 136     SysBusDevice parent_obj;
 137
 138     MemoryRegion iomem;
 139     MemoryRegion mmlqspi;
 140
 141     qemu_irq irq;
 142     int irqline;
 143
 144     uint8_t num_cs;
 145     uint8_t num_busses;
 146
 147     uint8_t snoop_state;
 148     qemu_irq *cs_lines;
 149     SSIBus **spi;
 150
 151     Fifo8 rx_fifo;
 152     Fifo8 tx_fifo;
 153
 154     uint8_t num_txrx_bytes;
 155
 156     uint32_t regs[R_MAX];
 157 } XilinxSPIPS;
 158
 159 typedef struct {
 160     XilinxSPIPS parent_obj;
 161
 162     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 163     hwaddr lqspi_cached_addr;
 164 } XilinxQSPIPS;
 165
 166 typedef struct XilinxSPIPSClass {
 167     SysBusDeviceClass parent_class;
 168
 169     const MemoryRegionOps *reg_ops;
 170
 171     uint32_t rx_fifo_size;
 172     uint32_t tx_fifo_size;
 173 } XilinxSPIPSClass;
 174
 175 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 176 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 177
 178 #define XILINX_SPIPS(obj) \
 179      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 180 #define XILINX_SPIPS_CLASS(klass) \
 181      OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
 182 #define XILINX_SPIPS_GET_CLASS(obj) \
 183      OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
 184
 185 #define XILINX_QSPIPS(obj) \
 186      OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 187
 188 static inline int num_effective_busses(XilinxSPIPS *s)
 189 {
 190     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 191             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 192 }
 193
 194 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
 195 {
 196     return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
 197                     || !fifo8_is_empty(&s->tx_fifo));
 198 }
 199
 200 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 201 {
 202     int i, j;
 203     bool found = false;
 204     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 205
 206     for (i = 0; i < s->num_cs; i++) {
 207         for (j = 0; j < num_effective_busses(s); j++) {
 208             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 209             int cs_to_set = (j * s->num_cs + i + upage) %
 210                                 (s->num_cs * s->num_busses);
 211
 212             if (xilinx_spips_cs_is_set(s, i, field) && !found) {
 213                 DB_PRINT("selecting slave %d\n", i);
 214                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 215             } else {
 216                 DB_PRINT("deselecting slave %d\n", i);
 217                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 218             }
 219         }
 220         if (xilinx_spips_cs_is_set(s, i, field)) {
 221             found = true;
 222         }
 223     }
 224     if (!found) {
 225         s->snoop_state = SNOOP_CHECKING;
 226     }
 227 }
 228
 229 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 230 {
 231     if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
 232         return;
 233     }
 234     /* These are set/cleared as they occur */
 235     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 236                                 IXR_TX_FIFO_MODE_FAIL);
 237     /* these are pure functions of fifo state, set them here */
 238     s->regs[R_INTR_STATUS] |=
 239         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 240         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 241         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 242         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 243     /* drive external interrupt pin */
 244     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 245                                                                 IXR_ALL);
 246     if (new_irqline != s->irqline) {
 247         s->irqline = new_irqline;
 248         qemu_set_irq(s->irq, s->irqline);
 249     }
 250 }
 251
 252 static void xilinx_spips_reset(DeviceState *d)
 253 {
 254     XilinxSPIPS *s = XILINX_SPIPS(d);
 255
 256     int i;
 257     for (i = 0; i < R_MAX; i++) {
 258         s->regs[i] = 0;
 259     }
 260
 261     fifo8_reset(&s->rx_fifo);
 262     fifo8_reset(&s->rx_fifo);
 263     /* non zero resets */
 264     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 265     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 266     s->regs[R_TX_THRES] = 1;
 267     s->regs[R_RX_THRES] = 1;
 268     /* FIXME: move magic number definition somewhere sensible */
 269     s->regs[R_MOD_ID] = 0x01090106;
 270     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 271     s->snoop_state = SNOOP_CHECKING;
 272     xilinx_spips_update_ixr(s);
 273     xilinx_spips_update_cs_lines(s);
 274 }
 275
 276 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 277 {
 278     for (;;) {
 279         int i;
 280         uint8_t rx;
 281         uint8_t tx = 0;
 282
 283         for (i = 0; i < num_effective_busses(s); ++i) {
 284             if (!i || s->snoop_state == SNOOP_STRIPING) {
 285                 if (fifo8_is_empty(&s->tx_fifo)) {
 286                     if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
 287                         s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 288                     }
 289                     xilinx_spips_update_ixr(s);
 290                     return;
 291                 } else {
 292                     tx = fifo8_pop(&s->tx_fifo);
 293                 }
 294             }
 295             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 296             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 297             if (!i || s->snoop_state == SNOOP_STRIPING) {
 298                 if (fifo8_is_full(&s->rx_fifo)) {
 299                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 300                     DB_PRINT("rx FIFO overflow");
 301                 } else {
 302                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 303                 }
 304             }
 305         }
 306
 307         switch (s->snoop_state) {
 308         case (SNOOP_CHECKING):
 309             switch (tx) { /* new instruction code */
 310             case READ: /* 3 address bytes, no dummy bytes/cycles */
 311             case PP:
 312             case DPP:
 313             case QPP:
 314                 s->snoop_state = 3;
 315                 break;
 316             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 317             case DOR:
 318             case QOR:
 319             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 320                 s->snoop_state = 4;
 321                 break;
 322             case QIOR: /* 3 address bytes, 2 dummy bytes */
 323                 s->snoop_state = 6;
 324                 break;
 325             default:
 326                 s->snoop_state = SNOOP_NONE;
 327             }
 328             break;
 329         case (SNOOP_STRIPING):
 330         case (SNOOP_NONE):
 331             break;
 332         default:
 333             s->snoop_state--;
 334         }
 335     }
 336 }
 337
 338 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 339 {
 340     int i;
 341
 342     *value = 0;
 343     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 344         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 345         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 346     }
 347 }
 348
 349 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 350                                                         unsigned size)
 351 {
 352     XilinxSPIPS *s = opaque;
 353     uint32_t mask = ~0;
 354     uint32_t ret;
 355
 356     addr >>= 2;
 357     switch (addr) {
 358     case R_CONFIG:
 359         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 360         break;
 361     case R_INTR_STATUS:
 362         ret = s->regs[addr] & IXR_ALL;
 363         s->regs[addr] = 0;
 364         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 365         return ret;
 366     case R_INTR_MASK:
 367         mask = IXR_ALL;
 368         break;
 369     case  R_EN:
 370         mask = 0x1;
 371         break;
 372     case R_SLAVE_IDLE_COUNT:
 373         mask = 0xFF;
 374         break;
 375     case R_MOD_ID:
 376         mask = 0x01FFFFFF;
 377         break;
 378     case R_INTR_EN:
 379     case R_INTR_DIS:
 380     case R_TX_DATA:
 381         mask = 0;
 382         break;
 383     case R_RX_DATA:
 384         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 385         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 386         xilinx_spips_update_ixr(s);
 387         return ret;
 388     }
 389     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 390     return s->regs[addr] & mask;
 391
 392 }
 393
 394 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 395 {
 396     int i;
 397     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 398         if (s->regs[R_CONFIG] & ENDIAN) {
 399             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 400             value <<= 8;
 401         } else {
 402             fifo8_push(&s->tx_fifo, (uint8_t)value);
 403             value >>= 8;
 404         }
 405     }
 406 }
 407
 408 static void xilinx_spips_write(void *opaque, hwaddr addr,
 409                                         uint64_t value, unsigned size)
 410 {
 411     int mask = ~0;
 412     int man_start_com = 0;
 413     XilinxSPIPS *s = opaque;
 414
 415     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 416     addr >>= 2;
 417     switch (addr) {
 418     case R_CONFIG:
 419         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 420         if (value & MAN_START_COM) {
 421             man_start_com = 1;
 422         }
 423         break;
 424     case R_INTR_STATUS:
 425         mask = IXR_ALL;
 426         s->regs[R_INTR_STATUS] &= ~(mask & value);
 427         goto no_reg_update;
 428     case R_INTR_DIS:
 429         mask = IXR_ALL;
 430         s->regs[R_INTR_MASK] &= ~(mask & value);
 431         goto no_reg_update;
 432     case R_INTR_EN:
 433         mask = IXR_ALL;
 434         s->regs[R_INTR_MASK] |= mask & value;
 435         goto no_reg_update;
 436     case R_EN:
 437         mask = 0x1;
 438         break;
 439     case R_SLAVE_IDLE_COUNT:
 440         mask = 0xFF;
 441         break;
 442     case R_RX_DATA:
 443     case R_INTR_MASK:
 444     case R_MOD_ID:
 445         mask = 0;
 446         break;
 447     case R_TX_DATA:
 448         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 449         goto no_reg_update;
 450     case R_TXD1:
 451         tx_data_bytes(s, (uint32_t)value, 1);
 452         goto no_reg_update;
 453     case R_TXD2:
 454         tx_data_bytes(s, (uint32_t)value, 2);
 455         goto no_reg_update;
 456     case R_TXD3:
 457         tx_data_bytes(s, (uint32_t)value, 3);
 458         goto no_reg_update;
 459     }
 460     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 461 no_reg_update:
 462     xilinx_spips_update_cs_lines(s);
 463     if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
 464             (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
 465         xilinx_spips_flush_txfifo(s);
 466     }
 467     xilinx_spips_update_cs_lines(s);
 468     xilinx_spips_update_ixr(s);
 469 }
 470
 471 static const MemoryRegionOps spips_ops = {
 472     .read = xilinx_spips_read,
 473     .write = xilinx_spips_write,
 474     .endianness = DEVICE_LITTLE_ENDIAN,
 475 };
 476
 477 static void xilinx_qspips_write(void *opaque, hwaddr addr,
 478                                 uint64_t value, unsigned size)
 479 {
 480     XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
 481
 482     xilinx_spips_write(opaque, addr, value, size);
 483     addr >>= 2;
 484
 485     if (addr == R_LQSPI_CFG) {
 486         q->lqspi_cached_addr = ~0ULL;
 487     }
 488 }
 489
 490 static const MemoryRegionOps qspips_ops = {
 491     .read = xilinx_spips_read,
 492     .write = xilinx_qspips_write,
 493     .endianness = DEVICE_LITTLE_ENDIAN,
 494 };
 495
 496 #define LQSPI_CACHE_SIZE 1024
 497
 498 static uint64_t
 499 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 500 {
 501     int i;
 502     XilinxQSPIPS *q = opaque;
 503     XilinxSPIPS *s = opaque;
 504     uint32_t ret;
 505
 506     if (addr >= q->lqspi_cached_addr &&
 507             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 508         ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
 509         DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret);
 510         return ret;
 511     } else {
 512         int flash_addr = (addr / num_effective_busses(s));
 513         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 514         int cache_entry = 0;
 515         uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
 516
 517         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
 518         s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
 519
 520         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 521
 522         fifo8_reset(&s->tx_fifo);
 523         fifo8_reset(&s->rx_fifo);
 524
 525         /* instruction */
 526         DB_PRINT("pushing read instruction: %02x\n",
 527                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 528         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 529         /* read address */
 530         DB_PRINT("pushing read address %06x\n", flash_addr);
 531         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 532         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 533         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 534         /* mode bits */
 535         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 536             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 537                                               LQSPI_CFG_MODE_SHIFT,
 538                                               LQSPI_CFG_MODE_WIDTH));
 539         }
 540         /* dummy bytes */
 541         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 542                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 543             DB_PRINT("pushing dummy byte\n");
 544             fifo8_push(&s->tx_fifo, 0);
 545         }
 546         xilinx_spips_update_cs_lines(s);
 547         xilinx_spips_flush_txfifo(s);
 548         fifo8_reset(&s->rx_fifo);
 549
 550         DB_PRINT("starting QSPI data read\n");
 551
 552         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 553             tx_data_bytes(s, 0, 4);
 554             xilinx_spips_flush_txfifo(s);
 555             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
 556             cache_entry++;
 557         }
 558
 559         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
 560         s->regs[R_LQSPI_STS] |= u_page_save;
 561         xilinx_spips_update_cs_lines(s);
 562
 563         q->lqspi_cached_addr = addr;
 564         return lqspi_read(opaque, addr, size);
 565     }
 566 }
 567
 568 static const MemoryRegionOps lqspi_ops = {
 569     .read = lqspi_read,
 570     .endianness = DEVICE_NATIVE_ENDIAN,
 571     .valid = {
 572         .min_access_size = 4,
 573         .max_access_size = 4
 574     }
 575 };
 576
 577 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 578 {
 579     XilinxSPIPS *s = XILINX_SPIPS(dev);
 580     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 581     XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
 582     int i;
 583
 584     DB_PRINT("realized spips\n");
 585
 586     s->spi = g_new(SSIBus *, s->num_busses);
 587     for (i = 0; i < s->num_busses; ++i) {
 588         char bus_name[16];
 589         snprintf(bus_name, 16, "spi%d", i);
 590         s->spi[i] = ssi_create_bus(dev, bus_name);
 591     }
 592
 593     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 594     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 595     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 596     sysbus_init_irq(sbd, &s->irq);
 597     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 598         sysbus_init_irq(sbd, &s->cs_lines[i]);
 599     }
 600
 601     memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4);
 602     sysbus_init_mmio(sbd, &s->iomem);
 603
 604     s->irqline = -1;
 605
 606     fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
 607     fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
 608 }
 609
 610 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
 611 {
 612     XilinxSPIPS *s = XILINX_SPIPS(dev);
 613     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
 614     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 615
 616     DB_PRINT("realized qspips\n");
 617
 618     s->num_busses = 2;
 619     s->num_cs = 2;
 620     s->num_txrx_bytes = 4;
 621
 622     xilinx_spips_realize(dev, errp);
 623     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 624                           (1 << LQSPI_ADDRESS_BITS) * 2);
 625     sysbus_init_mmio(sbd, &s->mmlqspi);
 626
 627     q->lqspi_cached_addr = ~0ULL;
 628 }
 629
 630 static int xilinx_spips_post_load(void *opaque, int version_id)
 631 {
 632     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 633     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 634     return 0;
 635 }
 636
 637 static const VMStateDescription vmstate_xilinx_spips = {
 638     .name = "xilinx_spips",
 639     .version_id = 2,
 640     .minimum_version_id = 2,
 641     .minimum_version_id_old = 2,
 642     .post_load = xilinx_spips_post_load,
 643     .fields = (VMStateField[]) {
 644         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 645         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 646         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 647         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 648         VMSTATE_END_OF_LIST()
 649     }
 650 };
 651
 652 static Property xilinx_spips_properties[] = {
 653     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 654     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 655     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 656     DEFINE_PROP_END_OF_LIST(),
 657 };
 658
 659 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
 660 {
 661     DeviceClass *dc = DEVICE_CLASS(klass);
 662     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
 663
 664     dc->realize = xilinx_qspips_realize;
 665     xsc->reg_ops = &qspips_ops;
 666     xsc->rx_fifo_size = RXFF_A_Q;
 667     xsc->tx_fifo_size = TXFF_A_Q;
 668 }
 669
 670 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 671 {
 672     DeviceClass *dc = DEVICE_CLASS(klass);
 673     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
 674
 675     dc->realize = xilinx_spips_realize;
 676     dc->reset = xilinx_spips_reset;
 677     dc->props = xilinx_spips_properties;
 678     dc->vmsd = &vmstate_xilinx_spips;
 679
 680     xsc->reg_ops = &spips_ops;
 681     xsc->rx_fifo_size = RXFF_A;
 682     xsc->tx_fifo_size = TXFF_A;
 683 }
 684
 685 static const TypeInfo xilinx_spips_info = {
 686     .name  = TYPE_XILINX_SPIPS,
 687     .parent = TYPE_SYS_BUS_DEVICE,
 688     .instance_size  = sizeof(XilinxSPIPS),
 689     .class_init = xilinx_spips_class_init,
 690     .class_size = sizeof(XilinxSPIPSClass),
 691 };
 692
 693 static const TypeInfo xilinx_qspips_info = {
 694     .name  = TYPE_XILINX_QSPIPS,
 695     .parent = TYPE_XILINX_SPIPS,
 696     .instance_size  = sizeof(XilinxQSPIPS),
 697     .class_init = xilinx_qspips_class_init,
 698 };
 699
 700 static void xilinx_spips_register_types(void)
 701 {
 702     type_register_static(&xilinx_spips_info);
 703     type_register_static(&xilinx_qspips_info);
 704 }
 705
 706 type_init(xilinx_spips_register_types)