hw/ssi/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59
  60 /* interrupt mechanism */
  61 #define R_INTR_STATUS       (0x04 / 4)
  62 #define R_INTR_EN           (0x08 / 4)
  63 #define R_INTR_DIS          (0x0C / 4)
  64 #define R_INTR_MASK         (0x10 / 4)
  65 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  66 #define IXR_RX_FIFO_FULL        (1 << 5)
  67 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  68 #define IXR_TX_FIFO_FULL        (1 << 3)
  69 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  70 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  71 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  72 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  73
  74 #define R_EN                (0x14 / 4)
  75 #define R_DELAY             (0x18 / 4)
  76 #define R_TX_DATA           (0x1C / 4)
  77 #define R_RX_DATA           (0x20 / 4)
  78 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  79 #define R_TX_THRES          (0x28 / 4)
  80 #define R_RX_THRES          (0x2C / 4)
  81 #define R_TXD1              (0x80 / 4)
  82 #define R_TXD2              (0x84 / 4)
  83 #define R_TXD3              (0x88 / 4)
  84
  85 #define R_LQSPI_CFG         (0xa0 / 4)
  86 #define R_LQSPI_CFG_RESET       0x03A002EB
  87 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  88 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  89 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  90 #define LQSPI_CFG_U_PAGE        (1 << 28)
  91 #define LQSPI_CFG_MODE_EN       (1 << 25)
  92 #define LQSPI_CFG_MODE_WIDTH    8
  93 #define LQSPI_CFG_MODE_SHIFT    16
  94 #define LQSPI_CFG_DUMMY_WIDTH   3
  95 #define LQSPI_CFG_DUMMY_SHIFT   8
  96 #define LQSPI_CFG_INST_CODE     0xFF
  97
  98 #define R_LQSPI_STS         (0xA4 / 4)
  99 #define LQSPI_STS_WR_RECVD      (1 << 1)
 100
 101 #define R_MOD_ID            (0xFC / 4)
 102
 103 #define R_MAX (R_MOD_ID+1)
 104
 105 /* size of TXRX FIFOs */
 106 #define RXFF_A          32
 107 #define TXFF_A          32
 108
 109 /* 16MB per linear region */
 110 #define LQSPI_ADDRESS_BITS 24
 111 /* Bite off 4k chunks at a time */
 112 #define LQSPI_CACHE_SIZE 1024
 113
 114 #define SNOOP_CHECKING 0xFF
 115 #define SNOOP_NONE 0xFE
 116 #define SNOOP_STRIPING 0
 117
 118 typedef enum {
 119     READ = 0x3,
 120     FAST_READ = 0xb,
 121     DOR = 0x3b,
 122     QOR = 0x6b,
 123     DIOR = 0xbb,
 124     QIOR = 0xeb,
 125
 126     PP = 0x2,
 127     DPP = 0xa2,
 128     QPP = 0x32,
 129 } FlashCMD;
 130
 131 typedef struct {
 132     SysBusDevice parent_obj;
 133
 134     MemoryRegion iomem;
 135     MemoryRegion mmlqspi;
 136
 137     qemu_irq irq;
 138     int irqline;
 139
 140     uint8_t num_cs;
 141     uint8_t num_busses;
 142
 143     uint8_t snoop_state;
 144     qemu_irq *cs_lines;
 145     SSIBus **spi;
 146
 147     Fifo8 rx_fifo;
 148     Fifo8 tx_fifo;
 149
 150     uint8_t num_txrx_bytes;
 151
 152     uint32_t regs[R_MAX];
 153 } XilinxSPIPS;
 154
 155 typedef struct {
 156     XilinxSPIPS parent_obj;
 157
 158     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 159     hwaddr lqspi_cached_addr;
 160 } XilinxQSPIPS;
 161
 162
 163 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 164 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 165
 166 #define XILINX_SPIPS(obj) \
 167      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 168 #define XILINX_QSPIPS(obj) \
 169      OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 170
 171 static inline int num_effective_busses(XilinxSPIPS *s)
 172 {
 173     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 174             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 175 }
 176
 177 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 178 {
 179     int i, j;
 180     bool found = false;
 181     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 182
 183     for (i = 0; i < s->num_cs; i++) {
 184         for (j = 0; j < num_effective_busses(s); j++) {
 185             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 186             int cs_to_set = (j * s->num_cs + i + upage) %
 187                                 (s->num_cs * s->num_busses);
 188
 189             if (~field & (1 << i) && !found) {
 190                 DB_PRINT("selecting slave %d\n", i);
 191                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 192             } else {
 193                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 194             }
 195         }
 196         if (~field & (1 << i)) {
 197             found = true;
 198         }
 199     }
 200     if (!found) {
 201         s->snoop_state = SNOOP_CHECKING;
 202     }
 203 }
 204
 205 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 206 {
 207     /* These are set/cleared as they occur */
 208     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 209                                 IXR_TX_FIFO_MODE_FAIL);
 210     /* these are pure functions of fifo state, set them here */
 211     s->regs[R_INTR_STATUS] |=
 212         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 213         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 214         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 215         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 216     /* drive external interrupt pin */
 217     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 218                                                                 IXR_ALL);
 219     if (new_irqline != s->irqline) {
 220         s->irqline = new_irqline;
 221         qemu_set_irq(s->irq, s->irqline);
 222     }
 223 }
 224
 225 static void xilinx_spips_reset(DeviceState *d)
 226 {
 227     XilinxSPIPS *s = XILINX_SPIPS(d);
 228
 229     int i;
 230     for (i = 0; i < R_MAX; i++) {
 231         s->regs[i] = 0;
 232     }
 233
 234     fifo8_reset(&s->rx_fifo);
 235     fifo8_reset(&s->rx_fifo);
 236     /* non zero resets */
 237     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 238     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 239     s->regs[R_TX_THRES] = 1;
 240     s->regs[R_RX_THRES] = 1;
 241     /* FIXME: move magic number definition somewhere sensible */
 242     s->regs[R_MOD_ID] = 0x01090106;
 243     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 244     s->snoop_state = SNOOP_CHECKING;
 245     xilinx_spips_update_ixr(s);
 246     xilinx_spips_update_cs_lines(s);
 247 }
 248
 249 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 250 {
 251     for (;;) {
 252         int i;
 253         uint8_t rx;
 254         uint8_t tx = 0;
 255
 256         for (i = 0; i < num_effective_busses(s); ++i) {
 257             if (!i || s->snoop_state == SNOOP_STRIPING) {
 258                 if (fifo8_is_empty(&s->tx_fifo)) {
 259                     s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 260                     xilinx_spips_update_ixr(s);
 261                     return;
 262                 } else {
 263                     tx = fifo8_pop(&s->tx_fifo);
 264                 }
 265             }
 266             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 267             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 268             if (!i || s->snoop_state == SNOOP_STRIPING) {
 269                 if (fifo8_is_full(&s->rx_fifo)) {
 270                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 271                     DB_PRINT("rx FIFO overflow");
 272                 } else {
 273                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 274                 }
 275             }
 276         }
 277
 278         switch (s->snoop_state) {
 279         case (SNOOP_CHECKING):
 280             switch (tx) { /* new instruction code */
 281             case READ: /* 3 address bytes, no dummy bytes/cycles */
 282             case PP:
 283             case DPP:
 284             case QPP:
 285                 s->snoop_state = 3;
 286                 break;
 287             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 288             case DOR:
 289             case QOR:
 290             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 291                 s->snoop_state = 4;
 292                 break;
 293             case QIOR: /* 3 address bytes, 2 dummy bytes */
 294                 s->snoop_state = 6;
 295                 break;
 296             default:
 297                 s->snoop_state = SNOOP_NONE;
 298             }
 299             break;
 300         case (SNOOP_STRIPING):
 301         case (SNOOP_NONE):
 302             break;
 303         default:
 304             s->snoop_state--;
 305         }
 306     }
 307 }
 308
 309 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 310 {
 311     int i;
 312
 313     *value = 0;
 314     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 315         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 316         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 317     }
 318 }
 319
 320 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 321                                                         unsigned size)
 322 {
 323     XilinxSPIPS *s = opaque;
 324     uint32_t mask = ~0;
 325     uint32_t ret;
 326
 327     addr >>= 2;
 328     switch (addr) {
 329     case R_CONFIG:
 330         mask = 0x0002FFFF;
 331         break;
 332     case R_INTR_STATUS:
 333     case R_INTR_MASK:
 334         mask = IXR_ALL;
 335         break;
 336     case  R_EN:
 337         mask = 0x1;
 338         break;
 339     case R_SLAVE_IDLE_COUNT:
 340         mask = 0xFF;
 341         break;
 342     case R_MOD_ID:
 343         mask = 0x01FFFFFF;
 344         break;
 345     case R_INTR_EN:
 346     case R_INTR_DIS:
 347     case R_TX_DATA:
 348         mask = 0;
 349         break;
 350     case R_RX_DATA:
 351         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 352         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 353         xilinx_spips_update_ixr(s);
 354         return ret;
 355     }
 356     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 357     return s->regs[addr] & mask;
 358
 359 }
 360
 361 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 362 {
 363     int i;
 364     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 365         if (s->regs[R_CONFIG] & ENDIAN) {
 366             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 367             value <<= 8;
 368         } else {
 369             fifo8_push(&s->tx_fifo, (uint8_t)value);
 370             value >>= 8;
 371         }
 372     }
 373 }
 374
 375 static void xilinx_spips_write(void *opaque, hwaddr addr,
 376                                         uint64_t value, unsigned size)
 377 {
 378     int mask = ~0;
 379     int man_start_com = 0;
 380     XilinxSPIPS *s = opaque;
 381
 382     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 383     addr >>= 2;
 384     switch (addr) {
 385     case R_CONFIG:
 386         mask = 0x0002FFFF;
 387         if (value & MAN_START_COM) {
 388             man_start_com = 1;
 389         }
 390         break;
 391     case R_INTR_STATUS:
 392         mask = IXR_ALL;
 393         s->regs[R_INTR_STATUS] &= ~(mask & value);
 394         goto no_reg_update;
 395     case R_INTR_DIS:
 396         mask = IXR_ALL;
 397         s->regs[R_INTR_MASK] &= ~(mask & value);
 398         goto no_reg_update;
 399     case R_INTR_EN:
 400         mask = IXR_ALL;
 401         s->regs[R_INTR_MASK] |= mask & value;
 402         goto no_reg_update;
 403     case R_EN:
 404         mask = 0x1;
 405         break;
 406     case R_SLAVE_IDLE_COUNT:
 407         mask = 0xFF;
 408         break;
 409     case R_RX_DATA:
 410     case R_INTR_MASK:
 411     case R_MOD_ID:
 412         mask = 0;
 413         break;
 414     case R_TX_DATA:
 415         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 416         goto no_reg_update;
 417     case R_TXD1:
 418         tx_data_bytes(s, (uint32_t)value, 1);
 419         goto no_reg_update;
 420     case R_TXD2:
 421         tx_data_bytes(s, (uint32_t)value, 2);
 422         goto no_reg_update;
 423     case R_TXD3:
 424         tx_data_bytes(s, (uint32_t)value, 3);
 425         goto no_reg_update;
 426     }
 427     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 428 no_reg_update:
 429     if (man_start_com) {
 430         xilinx_spips_flush_txfifo(s);
 431     }
 432     xilinx_spips_update_ixr(s);
 433     xilinx_spips_update_cs_lines(s);
 434 }
 435
 436 static const MemoryRegionOps spips_ops = {
 437     .read = xilinx_spips_read,
 438     .write = xilinx_spips_write,
 439     .endianness = DEVICE_LITTLE_ENDIAN,
 440 };
 441
 442 #define LQSPI_CACHE_SIZE 1024
 443
 444 static uint64_t
 445 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 446 {
 447     int i;
 448     XilinxQSPIPS *q = opaque;
 449     XilinxSPIPS *s = opaque;
 450
 451     if (addr >= q->lqspi_cached_addr &&
 452             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 453         return q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
 454     } else {
 455         int flash_addr = (addr / num_effective_busses(s));
 456         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 457         int cache_entry = 0;
 458
 459         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 460
 461         fifo8_reset(&s->tx_fifo);
 462         fifo8_reset(&s->rx_fifo);
 463
 464         s->regs[R_CONFIG] &= ~CS;
 465         s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
 466         xilinx_spips_update_cs_lines(s);
 467
 468         /* instruction */
 469         DB_PRINT("pushing read instruction: %02x\n",
 470                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 471         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 472         /* read address */
 473         DB_PRINT("pushing read address %06x\n", flash_addr);
 474         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 475         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 476         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 477         /* mode bits */
 478         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 479             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 480                                               LQSPI_CFG_MODE_SHIFT,
 481                                               LQSPI_CFG_MODE_WIDTH));
 482         }
 483         /* dummy bytes */
 484         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 485                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 486             DB_PRINT("pushing dummy byte\n");
 487             fifo8_push(&s->tx_fifo, 0);
 488         }
 489         xilinx_spips_flush_txfifo(s);
 490         fifo8_reset(&s->rx_fifo);
 491
 492         DB_PRINT("starting QSPI data read\n");
 493
 494         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 495             tx_data_bytes(s, 0, 4);
 496             xilinx_spips_flush_txfifo(s);
 497             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
 498             cache_entry++;
 499         }
 500
 501         s->regs[R_CONFIG] |= CS;
 502         xilinx_spips_update_cs_lines(s);
 503
 504         q->lqspi_cached_addr = addr;
 505         return lqspi_read(opaque, addr, size);
 506     }
 507 }
 508
 509 static const MemoryRegionOps lqspi_ops = {
 510     .read = lqspi_read,
 511     .endianness = DEVICE_NATIVE_ENDIAN,
 512     .valid = {
 513         .min_access_size = 4,
 514         .max_access_size = 4
 515     }
 516 };
 517
 518 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 519 {
 520     XilinxSPIPS *s = XILINX_SPIPS(dev);
 521     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 522     int i;
 523
 524     DB_PRINT("realized spips\n");
 525
 526     s->spi = g_new(SSIBus *, s->num_busses);
 527     for (i = 0; i < s->num_busses; ++i) {
 528         char bus_name[16];
 529         snprintf(bus_name, 16, "spi%d", i);
 530         s->spi[i] = ssi_create_bus(dev, bus_name);
 531     }
 532
 533     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 534     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 535     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 536     sysbus_init_irq(sbd, &s->irq);
 537     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 538         sysbus_init_irq(sbd, &s->cs_lines[i]);
 539     }
 540
 541     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 542     sysbus_init_mmio(sbd, &s->iomem);
 543
 544     s->irqline = -1;
 545
 546     fifo8_create(&s->rx_fifo, RXFF_A);
 547     fifo8_create(&s->tx_fifo, TXFF_A);
 548 }
 549
 550 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
 551 {
 552     XilinxSPIPS *s = XILINX_SPIPS(dev);
 553     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
 554     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 555
 556     DB_PRINT("realized qspips\n");
 557
 558     s->num_busses = 2;
 559     s->num_cs = 2;
 560     s->num_txrx_bytes = 4;
 561
 562     xilinx_spips_realize(dev, errp);
 563     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 564                           (1 << LQSPI_ADDRESS_BITS) * 2);
 565     sysbus_init_mmio(sbd, &s->mmlqspi);
 566
 567     q->lqspi_cached_addr = ~0ULL;
 568 }
 569
 570 static int xilinx_spips_post_load(void *opaque, int version_id)
 571 {
 572     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 573     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 574     return 0;
 575 }
 576
 577 static const VMStateDescription vmstate_xilinx_spips = {
 578     .name = "xilinx_spips",
 579     .version_id = 2,
 580     .minimum_version_id = 2,
 581     .minimum_version_id_old = 2,
 582     .post_load = xilinx_spips_post_load,
 583     .fields = (VMStateField[]) {
 584         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 585         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 586         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 587         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 588         VMSTATE_END_OF_LIST()
 589     }
 590 };
 591
 592 static Property xilinx_spips_properties[] = {
 593     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 594     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 595     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 596     DEFINE_PROP_END_OF_LIST(),
 597 };
 598
 599 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
 600 {
 601     DeviceClass *dc = DEVICE_CLASS(klass);
 602
 603     dc->realize = xilinx_qspips_realize;
 604 }
 605
 606 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 607 {
 608     DeviceClass *dc = DEVICE_CLASS(klass);
 609
 610     dc->realize = xilinx_spips_realize;
 611     dc->reset = xilinx_spips_reset;
 612     dc->props = xilinx_spips_properties;
 613     dc->vmsd = &vmstate_xilinx_spips;
 614 }
 615
 616 static const TypeInfo xilinx_spips_info = {
 617     .name  = TYPE_XILINX_SPIPS,
 618     .parent = TYPE_SYS_BUS_DEVICE,
 619     .instance_size  = sizeof(XilinxSPIPS),
 620     .class_init = xilinx_spips_class_init,
 621 };
 622
 623 static const TypeInfo xilinx_qspips_info = {
 624     .name  = TYPE_XILINX_QSPIPS,
 625     .parent = TYPE_XILINX_SPIPS,
 626     .instance_size  = sizeof(XilinxQSPIPS),
 627     .class_init = xilinx_qspips_class_init,
 628 };
 629
 630 static void xilinx_spips_register_types(void)
 631 {
 632     type_register_static(&xilinx_spips_info);
 633     type_register_static(&xilinx_qspips_info);
 634 }
 635
 636 type_init(xilinx_spips_register_types)