hw/ssi/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59 #define R_CONFIG_RSVD       (0x7bf40000)
  60
  61 /* interrupt mechanism */
  62 #define R_INTR_STATUS       (0x04 / 4)
  63 #define R_INTR_EN           (0x08 / 4)
  64 #define R_INTR_DIS          (0x0C / 4)
  65 #define R_INTR_MASK         (0x10 / 4)
  66 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  67 #define IXR_RX_FIFO_FULL        (1 << 5)
  68 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  69 #define IXR_TX_FIFO_FULL        (1 << 3)
  70 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  71 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  72 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  73 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  74
  75 #define R_EN                (0x14 / 4)
  76 #define R_DELAY             (0x18 / 4)
  77 #define R_TX_DATA           (0x1C / 4)
  78 #define R_RX_DATA           (0x20 / 4)
  79 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  80 #define R_TX_THRES          (0x28 / 4)
  81 #define R_RX_THRES          (0x2C / 4)
  82 #define R_TXD1              (0x80 / 4)
  83 #define R_TXD2              (0x84 / 4)
  84 #define R_TXD3              (0x88 / 4)
  85
  86 #define R_LQSPI_CFG         (0xa0 / 4)
  87 #define R_LQSPI_CFG_RESET       0x03A002EB
  88 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  89 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  90 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  91 #define LQSPI_CFG_U_PAGE        (1 << 28)
  92 #define LQSPI_CFG_MODE_EN       (1 << 25)
  93 #define LQSPI_CFG_MODE_WIDTH    8
  94 #define LQSPI_CFG_MODE_SHIFT    16
  95 #define LQSPI_CFG_DUMMY_WIDTH   3
  96 #define LQSPI_CFG_DUMMY_SHIFT   8
  97 #define LQSPI_CFG_INST_CODE     0xFF
  98
  99 #define R_LQSPI_STS         (0xA4 / 4)
 100 #define LQSPI_STS_WR_RECVD      (1 << 1)
 101
 102 #define R_MOD_ID            (0xFC / 4)
 103
 104 #define R_MAX (R_MOD_ID+1)
 105
 106 /* size of TXRX FIFOs */
 107 #define RXFF_A          32
 108 #define TXFF_A          32
 109
 110 #define RXFF_A_Q          (64 * 4)
 111 #define TXFF_A_Q          (64 * 4)
 112
 113 /* 16MB per linear region */
 114 #define LQSPI_ADDRESS_BITS 24
 115 /* Bite off 4k chunks at a time */
 116 #define LQSPI_CACHE_SIZE 1024
 117
 118 #define SNOOP_CHECKING 0xFF
 119 #define SNOOP_NONE 0xFE
 120 #define SNOOP_STRIPING 0
 121
 122 typedef enum {
 123     READ = 0x3,
 124     FAST_READ = 0xb,
 125     DOR = 0x3b,
 126     QOR = 0x6b,
 127     DIOR = 0xbb,
 128     QIOR = 0xeb,
 129
 130     PP = 0x2,
 131     DPP = 0xa2,
 132     QPP = 0x32,
 133 } FlashCMD;
 134
 135 typedef struct {
 136     SysBusDevice parent_obj;
 137
 138     MemoryRegion iomem;
 139     MemoryRegion mmlqspi;
 140
 141     qemu_irq irq;
 142     int irqline;
 143
 144     uint8_t num_cs;
 145     uint8_t num_busses;
 146
 147     uint8_t snoop_state;
 148     qemu_irq *cs_lines;
 149     SSIBus **spi;
 150
 151     Fifo8 rx_fifo;
 152     Fifo8 tx_fifo;
 153
 154     uint8_t num_txrx_bytes;
 155
 156     uint32_t regs[R_MAX];
 157 } XilinxSPIPS;
 158
 159 typedef struct {
 160     XilinxSPIPS parent_obj;
 161
 162     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 163     hwaddr lqspi_cached_addr;
 164 } XilinxQSPIPS;
 165
 166 typedef struct XilinxSPIPSClass {
 167     SysBusDeviceClass parent_class;
 168
 169     const MemoryRegionOps *reg_ops;
 170
 171     uint32_t rx_fifo_size;
 172     uint32_t tx_fifo_size;
 173 } XilinxSPIPSClass;
 174
 175 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 176 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 177
 178 #define XILINX_SPIPS(obj) \
 179      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 180 #define XILINX_SPIPS_CLASS(klass) \
 181      OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
 182 #define XILINX_SPIPS_GET_CLASS(obj) \
 183      OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
 184
 185 #define XILINX_QSPIPS(obj) \
 186      OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 187
 188 static inline int num_effective_busses(XilinxSPIPS *s)
 189 {
 190     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 191             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 192 }
 193
 194 static inline bool xilinx_spips_cs_is_set(XilinxSPIPS *s, int i, int field)
 195 {
 196     return ~field & (1 << i) && (s->regs[R_CONFIG] & MANUAL_CS
 197                     || !fifo8_is_empty(&s->tx_fifo));
 198 }
 199
 200 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 201 {
 202     int i, j;
 203     bool found = false;
 204     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 205
 206     for (i = 0; i < s->num_cs; i++) {
 207         for (j = 0; j < num_effective_busses(s); j++) {
 208             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 209             int cs_to_set = (j * s->num_cs + i + upage) %
 210                                 (s->num_cs * s->num_busses);
 211
 212             if (xilinx_spips_cs_is_set(s, i, field) && !found) {
 213                 DB_PRINT("selecting slave %d\n", i);
 214                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 215             } else {
 216                 DB_PRINT("deselecting slave %d\n", i);
 217                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 218             }
 219         }
 220         if (xilinx_spips_cs_is_set(s, i, field)) {
 221             found = true;
 222         }
 223     }
 224     if (!found) {
 225         s->snoop_state = SNOOP_CHECKING;
 226     }
 227 }
 228
 229 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 230 {
 231     if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
 232         return;
 233     }
 234     /* These are set/cleared as they occur */
 235     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 236                                 IXR_TX_FIFO_MODE_FAIL);
 237     /* these are pure functions of fifo state, set them here */
 238     s->regs[R_INTR_STATUS] |=
 239         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 240         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 241         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 242         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 243     /* drive external interrupt pin */
 244     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 245                                                                 IXR_ALL);
 246     if (new_irqline != s->irqline) {
 247         s->irqline = new_irqline;
 248         qemu_set_irq(s->irq, s->irqline);
 249     }
 250 }
 251
 252 static void xilinx_spips_reset(DeviceState *d)
 253 {
 254     XilinxSPIPS *s = XILINX_SPIPS(d);
 255
 256     int i;
 257     for (i = 0; i < R_MAX; i++) {
 258         s->regs[i] = 0;
 259     }
 260
 261     fifo8_reset(&s->rx_fifo);
 262     fifo8_reset(&s->rx_fifo);
 263     /* non zero resets */
 264     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 265     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 266     s->regs[R_TX_THRES] = 1;
 267     s->regs[R_RX_THRES] = 1;
 268     /* FIXME: move magic number definition somewhere sensible */
 269     s->regs[R_MOD_ID] = 0x01090106;
 270     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 271     s->snoop_state = SNOOP_CHECKING;
 272     xilinx_spips_update_ixr(s);
 273     xilinx_spips_update_cs_lines(s);
 274 }
 275
 276 /* N way (num) in place bit striper. Lay out row wise bits (LSB to MSB)
 277  * column wise (from element 0 to N-1). num is the length of x, and dir
 278  * reverses the direction of the transform. Best illustrated by example:
 279  * Each digit in the below array is a single bit (num == 3):
 280  *
 281  * {{ 76543210, }  ----- stripe (dir == false) -----> {{ FCheb630, }
 282  *  { hgfedcba, }                                      { GDAfc741, }
 283  *  { HGFEDCBA, }} <---- upstripe (dir == true) -----  { HEBgda52, }}
 284  */
 285
 286 static inline void stripe8(uint8_t *x, int num, bool dir)
 287 {
 288     uint8_t r[num];
 289     memset(r, 0, sizeof(uint8_t) * num);
 290     int idx[2] = {0, 0};
 291     int bit[2] = {0, 0};
 292     int d = dir;
 293
 294     for (idx[0] = 0; idx[0] < num; ++idx[0]) {
 295         for (bit[0] = 0; bit[0] < 8; ++bit[0]) {
 296             r[idx[d]] |= x[idx[!d]] & 1 << bit[!d] ? 1 << bit[d] : 0;
 297             idx[1] = (idx[1] + 1) % num;
 298             if (!idx[1]) {
 299                 bit[1]++;
 300             }
 301         }
 302     }
 303     memcpy(x, r, sizeof(uint8_t) * num);
 304 }
 305
 306 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 307 {
 308     for (;;) {
 309         int i;
 310         uint8_t tx = 0;
 311         uint8_t tx_rx[num_effective_busses(s)];
 312
 313         if (fifo8_is_empty(&s->tx_fifo)) {
 314             if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
 315                 s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 316             }
 317             xilinx_spips_update_ixr(s);
 318             return;
 319         } else if (s->snoop_state == SNOOP_STRIPING) {
 320             for (i = 0; i < num_effective_busses(s); ++i) {
 321                 tx_rx[i] = fifo8_pop(&s->tx_fifo);
 322             }
 323             stripe8(tx_rx, num_effective_busses(s), false);
 324         } else {
 325             tx = fifo8_pop(&s->tx_fifo);
 326             for (i = 0; i < num_effective_busses(s); ++i) {
 327                 tx_rx[i] = tx;
 328             }
 329         }
 330
 331         for (i = 0; i < num_effective_busses(s); ++i) {
 332             DB_PRINT("tx = %02x\n", tx_rx[i]);
 333             tx_rx[i] = ssi_transfer(s->spi[i], (uint32_t)tx_rx[i]);
 334             DB_PRINT("rx = %02x\n", tx_rx[i]);
 335         }
 336
 337         if (fifo8_is_full(&s->rx_fifo)) {
 338             s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 339             DB_PRINT("rx FIFO overflow");
 340         } else if (s->snoop_state == SNOOP_STRIPING) {
 341             stripe8(tx_rx, num_effective_busses(s), true);
 342             for (i = 0; i < num_effective_busses(s); ++i) {
 343                 fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[i]);
 344             }
 345         } else {
 346            fifo8_push(&s->rx_fifo, (uint8_t)tx_rx[0]);
 347         }
 348
 349         switch (s->snoop_state) {
 350         case (SNOOP_CHECKING):
 351             switch (tx) { /* new instruction code */
 352             case READ: /* 3 address bytes, no dummy bytes/cycles */
 353             case PP:
 354             case DPP:
 355             case QPP:
 356                 s->snoop_state = 3;
 357                 break;
 358             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 359             case DOR:
 360             case QOR:
 361             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 362                 s->snoop_state = 4;
 363                 break;
 364             case QIOR: /* 3 address bytes, 2 dummy bytes */
 365                 s->snoop_state = 6;
 366                 break;
 367             default:
 368                 s->snoop_state = SNOOP_NONE;
 369             }
 370             break;
 371         case (SNOOP_STRIPING):
 372         case (SNOOP_NONE):
 373             break;
 374         default:
 375             s->snoop_state--;
 376         }
 377     }
 378 }
 379
 380 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 381 {
 382     int i;
 383
 384     *value = 0;
 385     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 386         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 387         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 388     }
 389 }
 390
 391 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 392                                                         unsigned size)
 393 {
 394     XilinxSPIPS *s = opaque;
 395     uint32_t mask = ~0;
 396     uint32_t ret;
 397
 398     addr >>= 2;
 399     switch (addr) {
 400     case R_CONFIG:
 401         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 402         break;
 403     case R_INTR_STATUS:
 404         ret = s->regs[addr] & IXR_ALL;
 405         s->regs[addr] = 0;
 406         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 407         return ret;
 408     case R_INTR_MASK:
 409         mask = IXR_ALL;
 410         break;
 411     case  R_EN:
 412         mask = 0x1;
 413         break;
 414     case R_SLAVE_IDLE_COUNT:
 415         mask = 0xFF;
 416         break;
 417     case R_MOD_ID:
 418         mask = 0x01FFFFFF;
 419         break;
 420     case R_INTR_EN:
 421     case R_INTR_DIS:
 422     case R_TX_DATA:
 423         mask = 0;
 424         break;
 425     case R_RX_DATA:
 426         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 427         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 428         xilinx_spips_update_ixr(s);
 429         return ret;
 430     }
 431     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 432     return s->regs[addr] & mask;
 433
 434 }
 435
 436 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 437 {
 438     int i;
 439     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 440         if (s->regs[R_CONFIG] & ENDIAN) {
 441             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 442             value <<= 8;
 443         } else {
 444             fifo8_push(&s->tx_fifo, (uint8_t)value);
 445             value >>= 8;
 446         }
 447     }
 448 }
 449
 450 static void xilinx_spips_write(void *opaque, hwaddr addr,
 451                                         uint64_t value, unsigned size)
 452 {
 453     int mask = ~0;
 454     int man_start_com = 0;
 455     XilinxSPIPS *s = opaque;
 456
 457     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 458     addr >>= 2;
 459     switch (addr) {
 460     case R_CONFIG:
 461         mask = ~(R_CONFIG_RSVD | MAN_START_COM);
 462         if (value & MAN_START_COM) {
 463             man_start_com = 1;
 464         }
 465         break;
 466     case R_INTR_STATUS:
 467         mask = IXR_ALL;
 468         s->regs[R_INTR_STATUS] &= ~(mask & value);
 469         goto no_reg_update;
 470     case R_INTR_DIS:
 471         mask = IXR_ALL;
 472         s->regs[R_INTR_MASK] &= ~(mask & value);
 473         goto no_reg_update;
 474     case R_INTR_EN:
 475         mask = IXR_ALL;
 476         s->regs[R_INTR_MASK] |= mask & value;
 477         goto no_reg_update;
 478     case R_EN:
 479         mask = 0x1;
 480         break;
 481     case R_SLAVE_IDLE_COUNT:
 482         mask = 0xFF;
 483         break;
 484     case R_RX_DATA:
 485     case R_INTR_MASK:
 486     case R_MOD_ID:
 487         mask = 0;
 488         break;
 489     case R_TX_DATA:
 490         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 491         goto no_reg_update;
 492     case R_TXD1:
 493         tx_data_bytes(s, (uint32_t)value, 1);
 494         goto no_reg_update;
 495     case R_TXD2:
 496         tx_data_bytes(s, (uint32_t)value, 2);
 497         goto no_reg_update;
 498     case R_TXD3:
 499         tx_data_bytes(s, (uint32_t)value, 3);
 500         goto no_reg_update;
 501     }
 502     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 503 no_reg_update:
 504     xilinx_spips_update_cs_lines(s);
 505     if ((man_start_com && s->regs[R_CONFIG] & MAN_START_EN) ||
 506             (fifo8_is_empty(&s->tx_fifo) && s->regs[R_CONFIG] & MAN_START_EN)) {
 507         xilinx_spips_flush_txfifo(s);
 508     }
 509     xilinx_spips_update_cs_lines(s);
 510     xilinx_spips_update_ixr(s);
 511 }
 512
 513 static const MemoryRegionOps spips_ops = {
 514     .read = xilinx_spips_read,
 515     .write = xilinx_spips_write,
 516     .endianness = DEVICE_LITTLE_ENDIAN,
 517 };
 518
 519 static void xilinx_qspips_write(void *opaque, hwaddr addr,
 520                                 uint64_t value, unsigned size)
 521 {
 522     XilinxQSPIPS *q = XILINX_QSPIPS(opaque);
 523
 524     xilinx_spips_write(opaque, addr, value, size);
 525     addr >>= 2;
 526
 527     if (addr == R_LQSPI_CFG) {
 528         q->lqspi_cached_addr = ~0ULL;
 529     }
 530 }
 531
 532 static const MemoryRegionOps qspips_ops = {
 533     .read = xilinx_spips_read,
 534     .write = xilinx_qspips_write,
 535     .endianness = DEVICE_LITTLE_ENDIAN,
 536 };
 537
 538 #define LQSPI_CACHE_SIZE 1024
 539
 540 static uint64_t
 541 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 542 {
 543     int i;
 544     XilinxQSPIPS *q = opaque;
 545     XilinxSPIPS *s = opaque;
 546     uint32_t ret;
 547
 548     if (addr >= q->lqspi_cached_addr &&
 549             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 550         ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
 551         DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret);
 552         return ret;
 553     } else {
 554         int flash_addr = (addr / num_effective_busses(s));
 555         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 556         int cache_entry = 0;
 557         uint32_t u_page_save = s->regs[R_LQSPI_STS] & ~LQSPI_CFG_U_PAGE;
 558
 559         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
 560         s->regs[R_LQSPI_STS] |= slave ? LQSPI_CFG_U_PAGE : 0;
 561
 562         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 563
 564         fifo8_reset(&s->tx_fifo);
 565         fifo8_reset(&s->rx_fifo);
 566
 567         /* instruction */
 568         DB_PRINT("pushing read instruction: %02x\n",
 569                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 570         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 571         /* read address */
 572         DB_PRINT("pushing read address %06x\n", flash_addr);
 573         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 574         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 575         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 576         /* mode bits */
 577         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 578             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 579                                               LQSPI_CFG_MODE_SHIFT,
 580                                               LQSPI_CFG_MODE_WIDTH));
 581         }
 582         /* dummy bytes */
 583         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 584                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 585             DB_PRINT("pushing dummy byte\n");
 586             fifo8_push(&s->tx_fifo, 0);
 587         }
 588         xilinx_spips_update_cs_lines(s);
 589         xilinx_spips_flush_txfifo(s);
 590         fifo8_reset(&s->rx_fifo);
 591
 592         DB_PRINT("starting QSPI data read\n");
 593
 594         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 595             tx_data_bytes(s, 0, 4);
 596             xilinx_spips_flush_txfifo(s);
 597             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
 598             cache_entry++;
 599         }
 600
 601         s->regs[R_LQSPI_STS] &= ~LQSPI_CFG_U_PAGE;
 602         s->regs[R_LQSPI_STS] |= u_page_save;
 603         xilinx_spips_update_cs_lines(s);
 604
 605         q->lqspi_cached_addr = addr;
 606         return lqspi_read(opaque, addr, size);
 607     }
 608 }
 609
 610 static const MemoryRegionOps lqspi_ops = {
 611     .read = lqspi_read,
 612     .endianness = DEVICE_NATIVE_ENDIAN,
 613     .valid = {
 614         .min_access_size = 4,
 615         .max_access_size = 4
 616     }
 617 };
 618
 619 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 620 {
 621     XilinxSPIPS *s = XILINX_SPIPS(dev);
 622     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 623     XilinxSPIPSClass *xsc = XILINX_SPIPS_GET_CLASS(s);
 624     int i;
 625
 626     DB_PRINT("realized spips\n");
 627
 628     s->spi = g_new(SSIBus *, s->num_busses);
 629     for (i = 0; i < s->num_busses; ++i) {
 630         char bus_name[16];
 631         snprintf(bus_name, 16, "spi%d", i);
 632         s->spi[i] = ssi_create_bus(dev, bus_name);
 633     }
 634
 635     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 636     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 637     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 638     sysbus_init_irq(sbd, &s->irq);
 639     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 640         sysbus_init_irq(sbd, &s->cs_lines[i]);
 641     }
 642
 643     memory_region_init_io(&s->iomem, xsc->reg_ops, s, "spi", R_MAX*4);
 644     sysbus_init_mmio(sbd, &s->iomem);
 645
 646     s->irqline = -1;
 647
 648     fifo8_create(&s->rx_fifo, xsc->rx_fifo_size);
 649     fifo8_create(&s->tx_fifo, xsc->tx_fifo_size);
 650 }
 651
 652 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
 653 {
 654     XilinxSPIPS *s = XILINX_SPIPS(dev);
 655     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
 656     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 657
 658     DB_PRINT("realized qspips\n");
 659
 660     s->num_busses = 2;
 661     s->num_cs = 2;
 662     s->num_txrx_bytes = 4;
 663
 664     xilinx_spips_realize(dev, errp);
 665     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 666                           (1 << LQSPI_ADDRESS_BITS) * 2);
 667     sysbus_init_mmio(sbd, &s->mmlqspi);
 668
 669     q->lqspi_cached_addr = ~0ULL;
 670 }
 671
 672 static int xilinx_spips_post_load(void *opaque, int version_id)
 673 {
 674     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 675     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 676     return 0;
 677 }
 678
 679 static const VMStateDescription vmstate_xilinx_spips = {
 680     .name = "xilinx_spips",
 681     .version_id = 2,
 682     .minimum_version_id = 2,
 683     .minimum_version_id_old = 2,
 684     .post_load = xilinx_spips_post_load,
 685     .fields = (VMStateField[]) {
 686         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 687         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 688         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 689         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 690         VMSTATE_END_OF_LIST()
 691     }
 692 };
 693
 694 static Property xilinx_spips_properties[] = {
 695     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 696     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 697     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 698     DEFINE_PROP_END_OF_LIST(),
 699 };
 700
 701 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
 702 {
 703     DeviceClass *dc = DEVICE_CLASS(klass);
 704     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
 705
 706     dc->realize = xilinx_qspips_realize;
 707     xsc->reg_ops = &qspips_ops;
 708     xsc->rx_fifo_size = RXFF_A_Q;
 709     xsc->tx_fifo_size = TXFF_A_Q;
 710 }
 711
 712 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 713 {
 714     DeviceClass *dc = DEVICE_CLASS(klass);
 715     XilinxSPIPSClass *xsc = XILINX_SPIPS_CLASS(klass);
 716
 717     dc->realize = xilinx_spips_realize;
 718     dc->reset = xilinx_spips_reset;
 719     dc->props = xilinx_spips_properties;
 720     dc->vmsd = &vmstate_xilinx_spips;
 721
 722     xsc->reg_ops = &spips_ops;
 723     xsc->rx_fifo_size = RXFF_A;
 724     xsc->tx_fifo_size = TXFF_A;
 725 }
 726
 727 static const TypeInfo xilinx_spips_info = {
 728     .name  = TYPE_XILINX_SPIPS,
 729     .parent = TYPE_SYS_BUS_DEVICE,
 730     .instance_size  = sizeof(XilinxSPIPS),
 731     .class_init = xilinx_spips_class_init,
 732     .class_size = sizeof(XilinxSPIPSClass),
 733 };
 734
 735 static const TypeInfo xilinx_qspips_info = {
 736     .name  = TYPE_XILINX_QSPIPS,
 737     .parent = TYPE_XILINX_SPIPS,
 738     .instance_size  = sizeof(XilinxQSPIPS),
 739     .class_init = xilinx_qspips_class_init,
 740 };
 741
 742 static void xilinx_spips_register_types(void)
 743 {
 744     type_register_static(&xilinx_spips_info);
 745     type_register_static(&xilinx_qspips_info);
 746 }
 747
 748 type_init(xilinx_spips_register_types)