hw/ssi/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "sysemu/sysemu.h"
  27 #include "hw/ptimer.h"
  28 #include "qemu/log.h"
  29 #include "qemu/fifo8.h"
  30 #include "hw/ssi.h"
  31 #include "qemu/bitops.h"
  32
  33 #ifdef XILINX_SPIPS_ERR_DEBUG
  34 #define DB_PRINT(...) do { \
  35     fprintf(stderr,  ": %s: ", __func__); \
  36     fprintf(stderr, ## __VA_ARGS__); \
  37     } while (0);
  38 #else
  39     #define DB_PRINT(...)
  40 #endif
  41
  42 /* config register */
  43 #define R_CONFIG            (0x00 / 4)
  44 #define IFMODE              (1 << 31)
  45 #define ENDIAN              (1 << 26)
  46 #define MODEFAIL_GEN_EN     (1 << 17)
  47 #define MAN_START_COM       (1 << 16)
  48 #define MAN_START_EN        (1 << 15)
  49 #define MANUAL_CS           (1 << 14)
  50 #define CS                  (0xF << 10)
  51 #define CS_SHIFT            (10)
  52 #define PERI_SEL            (1 << 9)
  53 #define REF_CLK             (1 << 8)
  54 #define FIFO_WIDTH          (3 << 6)
  55 #define BAUD_RATE_DIV       (7 << 3)
  56 #define CLK_PH              (1 << 2)
  57 #define CLK_POL             (1 << 1)
  58 #define MODE_SEL            (1 << 0)
  59
  60 /* interrupt mechanism */
  61 #define R_INTR_STATUS       (0x04 / 4)
  62 #define R_INTR_EN           (0x08 / 4)
  63 #define R_INTR_DIS          (0x0C / 4)
  64 #define R_INTR_MASK         (0x10 / 4)
  65 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  66 #define IXR_RX_FIFO_FULL        (1 << 5)
  67 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  68 #define IXR_TX_FIFO_FULL        (1 << 3)
  69 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  70 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  71 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  72 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  73
  74 #define R_EN                (0x14 / 4)
  75 #define R_DELAY             (0x18 / 4)
  76 #define R_TX_DATA           (0x1C / 4)
  77 #define R_RX_DATA           (0x20 / 4)
  78 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  79 #define R_TX_THRES          (0x28 / 4)
  80 #define R_RX_THRES          (0x2C / 4)
  81 #define R_TXD1              (0x80 / 4)
  82 #define R_TXD2              (0x84 / 4)
  83 #define R_TXD3              (0x88 / 4)
  84
  85 #define R_LQSPI_CFG         (0xa0 / 4)
  86 #define R_LQSPI_CFG_RESET       0x03A002EB
  87 #define LQSPI_CFG_LQ_MODE       (1 << 31)
  88 #define LQSPI_CFG_TWO_MEM       (1 << 30)
  89 #define LQSPI_CFG_SEP_BUS       (1 << 30)
  90 #define LQSPI_CFG_U_PAGE        (1 << 28)
  91 #define LQSPI_CFG_MODE_EN       (1 << 25)
  92 #define LQSPI_CFG_MODE_WIDTH    8
  93 #define LQSPI_CFG_MODE_SHIFT    16
  94 #define LQSPI_CFG_DUMMY_WIDTH   3
  95 #define LQSPI_CFG_DUMMY_SHIFT   8
  96 #define LQSPI_CFG_INST_CODE     0xFF
  97
  98 #define R_LQSPI_STS         (0xA4 / 4)
  99 #define LQSPI_STS_WR_RECVD      (1 << 1)
 100
 101 #define R_MOD_ID            (0xFC / 4)
 102
 103 #define R_MAX (R_MOD_ID+1)
 104
 105 /* size of TXRX FIFOs */
 106 #define RXFF_A          32
 107 #define TXFF_A          32
 108
 109 /* 16MB per linear region */
 110 #define LQSPI_ADDRESS_BITS 24
 111 /* Bite off 4k chunks at a time */
 112 #define LQSPI_CACHE_SIZE 1024
 113
 114 #define SNOOP_CHECKING 0xFF
 115 #define SNOOP_NONE 0xFE
 116 #define SNOOP_STRIPING 0
 117
 118 typedef enum {
 119     READ = 0x3,
 120     FAST_READ = 0xb,
 121     DOR = 0x3b,
 122     QOR = 0x6b,
 123     DIOR = 0xbb,
 124     QIOR = 0xeb,
 125
 126     PP = 0x2,
 127     DPP = 0xa2,
 128     QPP = 0x32,
 129 } FlashCMD;
 130
 131 typedef struct {
 132     SysBusDevice parent_obj;
 133
 134     MemoryRegion iomem;
 135     MemoryRegion mmlqspi;
 136
 137     qemu_irq irq;
 138     int irqline;
 139
 140     uint8_t num_cs;
 141     uint8_t num_busses;
 142
 143     uint8_t snoop_state;
 144     qemu_irq *cs_lines;
 145     SSIBus **spi;
 146
 147     Fifo8 rx_fifo;
 148     Fifo8 tx_fifo;
 149
 150     uint8_t num_txrx_bytes;
 151
 152     uint32_t regs[R_MAX];
 153 } XilinxSPIPS;
 154
 155 typedef struct {
 156     XilinxSPIPS parent_obj;
 157
 158     uint32_t lqspi_buf[LQSPI_CACHE_SIZE];
 159     hwaddr lqspi_cached_addr;
 160 } XilinxQSPIPS;
 161
 162
 163 #define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 164 #define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 165
 166 #define XILINX_SPIPS(obj) \
 167      OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 168 #define XILINX_QSPIPS(obj) \
 169      OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 170
 171 static inline int num_effective_busses(XilinxSPIPS *s)
 172 {
 173     return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS &&
 174             s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1;
 175 }
 176
 177 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 178 {
 179     int i, j;
 180     bool found = false;
 181     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 182
 183     for (i = 0; i < s->num_cs; i++) {
 184         for (j = 0; j < num_effective_busses(s); j++) {
 185             int upage = !!(s->regs[R_LQSPI_STS] & LQSPI_CFG_U_PAGE);
 186             int cs_to_set = (j * s->num_cs + i + upage) %
 187                                 (s->num_cs * s->num_busses);
 188
 189             if (~field & (1 << i) && !found) {
 190                 DB_PRINT("selecting slave %d\n", i);
 191                 qemu_set_irq(s->cs_lines[cs_to_set], 0);
 192             } else {
 193                 qemu_set_irq(s->cs_lines[cs_to_set], 1);
 194             }
 195         }
 196         if (~field & (1 << i)) {
 197             found = true;
 198         }
 199     }
 200     if (!found) {
 201         s->snoop_state = SNOOP_CHECKING;
 202     }
 203 }
 204
 205 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 206 {
 207     if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE) {
 208         return;
 209     }
 210     /* These are set/cleared as they occur */
 211     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 212                                 IXR_TX_FIFO_MODE_FAIL);
 213     /* these are pure functions of fifo state, set them here */
 214     s->regs[R_INTR_STATUS] |=
 215         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 216         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 217         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 218         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 219     /* drive external interrupt pin */
 220     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 221                                                                 IXR_ALL);
 222     if (new_irqline != s->irqline) {
 223         s->irqline = new_irqline;
 224         qemu_set_irq(s->irq, s->irqline);
 225     }
 226 }
 227
 228 static void xilinx_spips_reset(DeviceState *d)
 229 {
 230     XilinxSPIPS *s = XILINX_SPIPS(d);
 231
 232     int i;
 233     for (i = 0; i < R_MAX; i++) {
 234         s->regs[i] = 0;
 235     }
 236
 237     fifo8_reset(&s->rx_fifo);
 238     fifo8_reset(&s->rx_fifo);
 239     /* non zero resets */
 240     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 241     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 242     s->regs[R_TX_THRES] = 1;
 243     s->regs[R_RX_THRES] = 1;
 244     /* FIXME: move magic number definition somewhere sensible */
 245     s->regs[R_MOD_ID] = 0x01090106;
 246     s->regs[R_LQSPI_CFG] = R_LQSPI_CFG_RESET;
 247     s->snoop_state = SNOOP_CHECKING;
 248     xilinx_spips_update_ixr(s);
 249     xilinx_spips_update_cs_lines(s);
 250 }
 251
 252 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 253 {
 254     for (;;) {
 255         int i;
 256         uint8_t rx;
 257         uint8_t tx = 0;
 258
 259         for (i = 0; i < num_effective_busses(s); ++i) {
 260             if (!i || s->snoop_state == SNOOP_STRIPING) {
 261                 if (fifo8_is_empty(&s->tx_fifo)) {
 262                     if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) {
 263                         s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 264                     }
 265                     xilinx_spips_update_ixr(s);
 266                     return;
 267                 } else {
 268                     tx = fifo8_pop(&s->tx_fifo);
 269                 }
 270             }
 271             rx = ssi_transfer(s->spi[i], (uint32_t)tx);
 272             DB_PRINT("tx = %02x rx = %02x\n", tx, rx);
 273             if (!i || s->snoop_state == SNOOP_STRIPING) {
 274                 if (fifo8_is_full(&s->rx_fifo)) {
 275                     s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 276                     DB_PRINT("rx FIFO overflow");
 277                 } else {
 278                     fifo8_push(&s->rx_fifo, (uint8_t)rx);
 279                 }
 280             }
 281         }
 282
 283         switch (s->snoop_state) {
 284         case (SNOOP_CHECKING):
 285             switch (tx) { /* new instruction code */
 286             case READ: /* 3 address bytes, no dummy bytes/cycles */
 287             case PP:
 288             case DPP:
 289             case QPP:
 290                 s->snoop_state = 3;
 291                 break;
 292             case FAST_READ: /* 3 address bytes, 1 dummy byte */
 293             case DOR:
 294             case QOR:
 295             case DIOR: /* FIXME: these vary between vendor - set to spansion */
 296                 s->snoop_state = 4;
 297                 break;
 298             case QIOR: /* 3 address bytes, 2 dummy bytes */
 299                 s->snoop_state = 6;
 300                 break;
 301             default:
 302                 s->snoop_state = SNOOP_NONE;
 303             }
 304             break;
 305         case (SNOOP_STRIPING):
 306         case (SNOOP_NONE):
 307             break;
 308         default:
 309             s->snoop_state--;
 310         }
 311     }
 312 }
 313
 314 static inline void rx_data_bytes(XilinxSPIPS *s, uint32_t *value, int max)
 315 {
 316     int i;
 317
 318     *value = 0;
 319     for (i = 0; i < max && !fifo8_is_empty(&s->rx_fifo); ++i) {
 320         uint32_t next = fifo8_pop(&s->rx_fifo) & 0xFF;
 321         *value |= next << 8 * (s->regs[R_CONFIG] & ENDIAN ? 3-i : i);
 322     }
 323 }
 324
 325 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 326                                                         unsigned size)
 327 {
 328     XilinxSPIPS *s = opaque;
 329     uint32_t mask = ~0;
 330     uint32_t ret;
 331
 332     addr >>= 2;
 333     switch (addr) {
 334     case R_CONFIG:
 335         mask = 0x0002FFFF;
 336         break;
 337     case R_INTR_STATUS:
 338         ret = s->regs[addr] & IXR_ALL;
 339         s->regs[addr] = 0;
 340         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 341         return ret;
 342     case R_INTR_MASK:
 343         mask = IXR_ALL;
 344         break;
 345     case  R_EN:
 346         mask = 0x1;
 347         break;
 348     case R_SLAVE_IDLE_COUNT:
 349         mask = 0xFF;
 350         break;
 351     case R_MOD_ID:
 352         mask = 0x01FFFFFF;
 353         break;
 354     case R_INTR_EN:
 355     case R_INTR_DIS:
 356     case R_TX_DATA:
 357         mask = 0;
 358         break;
 359     case R_RX_DATA:
 360         rx_data_bytes(s, &ret, s->num_txrx_bytes);
 361         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 362         xilinx_spips_update_ixr(s);
 363         return ret;
 364     }
 365     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 366     return s->regs[addr] & mask;
 367
 368 }
 369
 370 static inline void tx_data_bytes(XilinxSPIPS *s, uint32_t value, int num)
 371 {
 372     int i;
 373     for (i = 0; i < num && !fifo8_is_full(&s->tx_fifo); ++i) {
 374         if (s->regs[R_CONFIG] & ENDIAN) {
 375             fifo8_push(&s->tx_fifo, (uint8_t)(value >> 24));
 376             value <<= 8;
 377         } else {
 378             fifo8_push(&s->tx_fifo, (uint8_t)value);
 379             value >>= 8;
 380         }
 381     }
 382 }
 383
 384 static void xilinx_spips_write(void *opaque, hwaddr addr,
 385                                         uint64_t value, unsigned size)
 386 {
 387     int mask = ~0;
 388     int man_start_com = 0;
 389     XilinxSPIPS *s = opaque;
 390
 391     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 392     addr >>= 2;
 393     switch (addr) {
 394     case R_CONFIG:
 395         mask = 0x0002FFFF;
 396         if (value & MAN_START_COM) {
 397             man_start_com = 1;
 398         }
 399         break;
 400     case R_INTR_STATUS:
 401         mask = IXR_ALL;
 402         s->regs[R_INTR_STATUS] &= ~(mask & value);
 403         goto no_reg_update;
 404     case R_INTR_DIS:
 405         mask = IXR_ALL;
 406         s->regs[R_INTR_MASK] &= ~(mask & value);
 407         goto no_reg_update;
 408     case R_INTR_EN:
 409         mask = IXR_ALL;
 410         s->regs[R_INTR_MASK] |= mask & value;
 411         goto no_reg_update;
 412     case R_EN:
 413         mask = 0x1;
 414         break;
 415     case R_SLAVE_IDLE_COUNT:
 416         mask = 0xFF;
 417         break;
 418     case R_RX_DATA:
 419     case R_INTR_MASK:
 420     case R_MOD_ID:
 421         mask = 0;
 422         break;
 423     case R_TX_DATA:
 424         tx_data_bytes(s, (uint32_t)value, s->num_txrx_bytes);
 425         goto no_reg_update;
 426     case R_TXD1:
 427         tx_data_bytes(s, (uint32_t)value, 1);
 428         goto no_reg_update;
 429     case R_TXD2:
 430         tx_data_bytes(s, (uint32_t)value, 2);
 431         goto no_reg_update;
 432     case R_TXD3:
 433         tx_data_bytes(s, (uint32_t)value, 3);
 434         goto no_reg_update;
 435     }
 436     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 437 no_reg_update:
 438     if (man_start_com) {
 439         xilinx_spips_flush_txfifo(s);
 440     }
 441     xilinx_spips_update_ixr(s);
 442     xilinx_spips_update_cs_lines(s);
 443 }
 444
 445 static const MemoryRegionOps spips_ops = {
 446     .read = xilinx_spips_read,
 447     .write = xilinx_spips_write,
 448     .endianness = DEVICE_LITTLE_ENDIAN,
 449 };
 450
 451 #define LQSPI_CACHE_SIZE 1024
 452
 453 static uint64_t
 454 lqspi_read(void *opaque, hwaddr addr, unsigned int size)
 455 {
 456     int i;
 457     XilinxQSPIPS *q = opaque;
 458     XilinxSPIPS *s = opaque;
 459     uint32_t ret;
 460
 461     if (addr >= q->lqspi_cached_addr &&
 462             addr <= q->lqspi_cached_addr + LQSPI_CACHE_SIZE - 4) {
 463         ret = q->lqspi_buf[(addr - q->lqspi_cached_addr) >> 2];
 464         DB_PRINT("addr: %08x, data: %08x\n", (unsigned)addr, (unsigned)ret);
 465         return ret;
 466     } else {
 467         int flash_addr = (addr / num_effective_busses(s));
 468         int slave = flash_addr >> LQSPI_ADDRESS_BITS;
 469         int cache_entry = 0;
 470
 471         DB_PRINT("config reg status: %08x\n", s->regs[R_LQSPI_CFG]);
 472
 473         fifo8_reset(&s->tx_fifo);
 474         fifo8_reset(&s->rx_fifo);
 475
 476         s->regs[R_CONFIG] &= ~CS;
 477         s->regs[R_CONFIG] |= (~(1 << slave) << CS_SHIFT) & CS;
 478         xilinx_spips_update_cs_lines(s);
 479
 480         /* instruction */
 481         DB_PRINT("pushing read instruction: %02x\n",
 482                  (uint8_t)(s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE));
 483         fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
 484         /* read address */
 485         DB_PRINT("pushing read address %06x\n", flash_addr);
 486         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
 487         fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
 488         fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
 489         /* mode bits */
 490         if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_MODE_EN) {
 491             fifo8_push(&s->tx_fifo, extract32(s->regs[R_LQSPI_CFG],
 492                                               LQSPI_CFG_MODE_SHIFT,
 493                                               LQSPI_CFG_MODE_WIDTH));
 494         }
 495         /* dummy bytes */
 496         for (i = 0; i < (extract32(s->regs[R_LQSPI_CFG], LQSPI_CFG_DUMMY_SHIFT,
 497                                    LQSPI_CFG_DUMMY_WIDTH)); ++i) {
 498             DB_PRINT("pushing dummy byte\n");
 499             fifo8_push(&s->tx_fifo, 0);
 500         }
 501         xilinx_spips_flush_txfifo(s);
 502         fifo8_reset(&s->rx_fifo);
 503
 504         DB_PRINT("starting QSPI data read\n");
 505
 506         for (i = 0; i < LQSPI_CACHE_SIZE / 4; ++i) {
 507             tx_data_bytes(s, 0, 4);
 508             xilinx_spips_flush_txfifo(s);
 509             rx_data_bytes(s, &q->lqspi_buf[cache_entry], 4);
 510             cache_entry++;
 511         }
 512
 513         s->regs[R_CONFIG] |= CS;
 514         xilinx_spips_update_cs_lines(s);
 515
 516         q->lqspi_cached_addr = addr;
 517         return lqspi_read(opaque, addr, size);
 518     }
 519 }
 520
 521 static const MemoryRegionOps lqspi_ops = {
 522     .read = lqspi_read,
 523     .endianness = DEVICE_NATIVE_ENDIAN,
 524     .valid = {
 525         .min_access_size = 4,
 526         .max_access_size = 4
 527     }
 528 };
 529
 530 static void xilinx_spips_realize(DeviceState *dev, Error **errp)
 531 {
 532     XilinxSPIPS *s = XILINX_SPIPS(dev);
 533     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 534     int i;
 535
 536     DB_PRINT("realized spips\n");
 537
 538     s->spi = g_new(SSIBus *, s->num_busses);
 539     for (i = 0; i < s->num_busses; ++i) {
 540         char bus_name[16];
 541         snprintf(bus_name, 16, "spi%d", i);
 542         s->spi[i] = ssi_create_bus(dev, bus_name);
 543     }
 544
 545     s->cs_lines = g_new0(qemu_irq, s->num_cs * s->num_busses);
 546     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[0]);
 547     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi[1]);
 548     sysbus_init_irq(sbd, &s->irq);
 549     for (i = 0; i < s->num_cs * s->num_busses; ++i) {
 550         sysbus_init_irq(sbd, &s->cs_lines[i]);
 551     }
 552
 553     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 554     sysbus_init_mmio(sbd, &s->iomem);
 555
 556     s->irqline = -1;
 557
 558     fifo8_create(&s->rx_fifo, RXFF_A);
 559     fifo8_create(&s->tx_fifo, TXFF_A);
 560 }
 561
 562 static void xilinx_qspips_realize(DeviceState *dev, Error **errp)
 563 {
 564     XilinxSPIPS *s = XILINX_SPIPS(dev);
 565     XilinxQSPIPS *q = XILINX_QSPIPS(dev);
 566     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 567
 568     DB_PRINT("realized qspips\n");
 569
 570     s->num_busses = 2;
 571     s->num_cs = 2;
 572     s->num_txrx_bytes = 4;
 573
 574     xilinx_spips_realize(dev, errp);
 575     memory_region_init_io(&s->mmlqspi, &lqspi_ops, s, "lqspi",
 576                           (1 << LQSPI_ADDRESS_BITS) * 2);
 577     sysbus_init_mmio(sbd, &s->mmlqspi);
 578
 579     q->lqspi_cached_addr = ~0ULL;
 580 }
 581
 582 static int xilinx_spips_post_load(void *opaque, int version_id)
 583 {
 584     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 585     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 586     return 0;
 587 }
 588
 589 static const VMStateDescription vmstate_xilinx_spips = {
 590     .name = "xilinx_spips",
 591     .version_id = 2,
 592     .minimum_version_id = 2,
 593     .minimum_version_id_old = 2,
 594     .post_load = xilinx_spips_post_load,
 595     .fields = (VMStateField[]) {
 596         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 597         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 598         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 599         VMSTATE_UINT8(snoop_state, XilinxSPIPS),
 600         VMSTATE_END_OF_LIST()
 601     }
 602 };
 603
 604 static Property xilinx_spips_properties[] = {
 605     DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1),
 606     DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4),
 607     DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1),
 608     DEFINE_PROP_END_OF_LIST(),
 609 };
 610
 611 static void xilinx_qspips_class_init(ObjectClass *klass, void * data)
 612 {
 613     DeviceClass *dc = DEVICE_CLASS(klass);
 614
 615     dc->realize = xilinx_qspips_realize;
 616 }
 617
 618 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 619 {
 620     DeviceClass *dc = DEVICE_CLASS(klass);
 621
 622     dc->realize = xilinx_spips_realize;
 623     dc->reset = xilinx_spips_reset;
 624     dc->props = xilinx_spips_properties;
 625     dc->vmsd = &vmstate_xilinx_spips;
 626 }
 627
 628 static const TypeInfo xilinx_spips_info = {
 629     .name  = TYPE_XILINX_SPIPS,
 630     .parent = TYPE_SYS_BUS_DEVICE,
 631     .instance_size  = sizeof(XilinxSPIPS),
 632     .class_init = xilinx_spips_class_init,
 633 };
 634
 635 static const TypeInfo xilinx_qspips_info = {
 636     .name  = TYPE_XILINX_QSPIPS,
 637     .parent = TYPE_XILINX_SPIPS,
 638     .instance_size  = sizeof(XilinxQSPIPS),
 639     .class_init = xilinx_qspips_class_init,
 640 };
 641
 642 static void xilinx_spips_register_types(void)
 643 {
 644     type_register_static(&xilinx_spips_info);
 645     type_register_static(&xilinx_qspips_info);
 646 }
 647
 648 type_init(xilinx_spips_register_types)