hw/stellaris.c

   1 /*
   2  * Luminary Micro Stellaris peripherals
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "ssi.h"
  12 #include "arm-misc.h"
  13 #include "devices.h"
  14 #include "qemu-timer.h"
  15 #include "i2c.h"
  16 #include "net.h"
  17 #include "boards.h"
  18
  19 #define GPIO_A 0
  20 #define GPIO_B 1
  21 #define GPIO_C 2
  22 #define GPIO_D 3
  23 #define GPIO_E 4
  24 #define GPIO_F 5
  25 #define GPIO_G 6
  26
  27 #define BP_OLED_I2C  0x01
  28 #define BP_OLED_SSI  0x02
  29 #define BP_GAMEPAD   0x04
  30
  31 typedef const struct {
  32     const char *name;
  33     uint32_t did0;
  34     uint32_t did1;
  35     uint32_t dc0;
  36     uint32_t dc1;
  37     uint32_t dc2;
  38     uint32_t dc3;
  39     uint32_t dc4;
  40     uint32_t peripherals;
  41 } stellaris_board_info;
  42
  43 /* General purpose timer module.  */
  44
  45 typedef struct gptm_state {
  46     SysBusDevice busdev;
  47     uint32_t config;
  48     uint32_t mode[2];
  49     uint32_t control;
  50     uint32_t state;
  51     uint32_t mask;
  52     uint32_t load[2];
  53     uint32_t match[2];
  54     uint32_t prescale[2];
  55     uint32_t match_prescale[2];
  56     uint32_t rtc;
  57     int64_t tick[2];
  58     struct gptm_state *opaque[2];
  59     QEMUTimer *timer[2];
  60     /* The timers have an alternate output used to trigger the ADC.  */
  61     qemu_irq trigger;
  62     qemu_irq irq;
  63 } gptm_state;
  64
  65 static void gptm_update_irq(gptm_state *s)
  66 {
  67     int level;
  68     level = (s->state & s->mask) != 0;
  69     qemu_set_irq(s->irq, level);
  70 }
  71
  72 static void gptm_stop(gptm_state *s, int n)
  73 {
  74     qemu_del_timer(s->timer[n]);
  75 }
  76
  77 static void gptm_reload(gptm_state *s, int n, int reset)
  78 {
  79     int64_t tick;
  80     if (reset)
  81         tick = qemu_get_clock_ns(vm_clock);
  82     else
  83         tick = s->tick[n];
  84
  85     if (s->config == 0) {
  86         /* 32-bit CountDown.  */
  87         uint32_t count;
  88         count = s->load[0] | (s->load[1] << 16);
  89         tick += (int64_t)count * system_clock_scale;
  90     } else if (s->config == 1) {
  91         /* 32-bit RTC.  1Hz tick.  */
  92         tick += get_ticks_per_sec();
  93     } else if (s->mode[n] == 0xa) {
  94         /* PWM mode.  Not implemented.  */
  95     } else {
  96         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
  97     }
  98     s->tick[n] = tick;
  99     qemu_mod_timer(s->timer[n], tick);
 100 }
 101
 102 static void gptm_tick(void *opaque)
 103 {
 104     gptm_state **p = (gptm_state **)opaque;
 105     gptm_state *s;
 106     int n;
 107
 108     s = *p;
 109     n = p - s->opaque;
 110     if (s->config == 0) {
 111         s->state |= 1;
 112         if ((s->control & 0x20)) {
 113             /* Output trigger.  */
 114             qemu_irq_pulse(s->trigger);
 115         }
 116         if (s->mode[0] & 1) {
 117             /* One-shot.  */
 118             s->control &= ~1;
 119         } else {
 120             /* Periodic.  */
 121             gptm_reload(s, 0, 0);
 122         }
 123     } else if (s->config == 1) {
 124         /* RTC.  */
 125         uint32_t match;
 126         s->rtc++;
 127         match = s->match[0] | (s->match[1] << 16);
 128         if (s->rtc > match)
 129             s->rtc = 0;
 130         if (s->rtc == 0) {
 131             s->state |= 8;
 132         }
 133         gptm_reload(s, 0, 0);
 134     } else if (s->mode[n] == 0xa) {
 135         /* PWM mode.  Not implemented.  */
 136     } else {
 137         hw_error("TODO: 16-bit timer mode 0x%x\n", s->mode[n]);
 138     }
 139     gptm_update_irq(s);
 140 }
 141
 142 static uint32_t gptm_read(void *opaque, target_phys_addr_t offset)
 143 {
 144     gptm_state *s = (gptm_state *)opaque;
 145
 146     switch (offset) {
 147     case 0x00: /* CFG */
 148         return s->config;
 149     case 0x04: /* TAMR */
 150         return s->mode[0];
 151     case 0x08: /* TBMR */
 152         return s->mode[1];
 153     case 0x0c: /* CTL */
 154         return s->control;
 155     case 0x18: /* IMR */
 156         return s->mask;
 157     case 0x1c: /* RIS */
 158         return s->state;
 159     case 0x20: /* MIS */
 160         return s->state & s->mask;
 161     case 0x24: /* CR */
 162         return 0;
 163     case 0x28: /* TAILR */
 164         return s->load[0] | ((s->config < 4) ? (s->load[1] << 16) : 0);
 165     case 0x2c: /* TBILR */
 166         return s->load[1];
 167     case 0x30: /* TAMARCHR */
 168         return s->match[0] | ((s->config < 4) ? (s->match[1] << 16) : 0);
 169     case 0x34: /* TBMATCHR */
 170         return s->match[1];
 171     case 0x38: /* TAPR */
 172         return s->prescale[0];
 173     case 0x3c: /* TBPR */
 174         return s->prescale[1];
 175     case 0x40: /* TAPMR */
 176         return s->match_prescale[0];
 177     case 0x44: /* TBPMR */
 178         return s->match_prescale[1];
 179     case 0x48: /* TAR */
 180         if (s->control == 1)
 181             return s->rtc;
 182     case 0x4c: /* TBR */
 183         hw_error("TODO: Timer value read\n");
 184     default:
 185         hw_error("gptm_read: Bad offset 0x%x\n", (int)offset);
 186         return 0;
 187     }
 188 }
 189
 190 static void gptm_write(void *opaque, target_phys_addr_t offset, uint32_t value)
 191 {
 192     gptm_state *s = (gptm_state *)opaque;
 193     uint32_t oldval;
 194
 195     /* The timers should be disabled before changing the configuration.
 196        We take advantage of this and defer everything until the timer
 197        is enabled.  */
 198     switch (offset) {
 199     case 0x00: /* CFG */
 200         s->config = value;
 201         break;
 202     case 0x04: /* TAMR */
 203         s->mode[0] = value;
 204         break;
 205     case 0x08: /* TBMR */
 206         s->mode[1] = value;
 207         break;
 208     case 0x0c: /* CTL */
 209         oldval = s->control;
 210         s->control = value;
 211         /* TODO: Implement pause.  */
 212         if ((oldval ^ value) & 1) {
 213             if (value & 1) {
 214                 gptm_reload(s, 0, 1);
 215             } else {
 216                 gptm_stop(s, 0);
 217             }
 218         }
 219         if (((oldval ^ value) & 0x100) && s->config >= 4) {
 220             if (value & 0x100) {
 221                 gptm_reload(s, 1, 1);
 222             } else {
 223                 gptm_stop(s, 1);
 224             }
 225         }
 226         break;
 227     case 0x18: /* IMR */
 228         s->mask = value & 0x77;
 229         gptm_update_irq(s);
 230         break;
 231     case 0x24: /* CR */
 232         s->state &= ~value;
 233         break;
 234     case 0x28: /* TAILR */
 235         s->load[0] = value & 0xffff;
 236         if (s->config < 4) {
 237             s->load[1] = value >> 16;
 238         }
 239         break;
 240     case 0x2c: /* TBILR */
 241         s->load[1] = value & 0xffff;
 242         break;
 243     case 0x30: /* TAMARCHR */
 244         s->match[0] = value & 0xffff;
 245         if (s->config < 4) {
 246             s->match[1] = value >> 16;
 247         }
 248         break;
 249     case 0x34: /* TBMATCHR */
 250         s->match[1] = value >> 16;
 251         break;
 252     case 0x38: /* TAPR */
 253         s->prescale[0] = value;
 254         break;
 255     case 0x3c: /* TBPR */
 256         s->prescale[1] = value;
 257         break;
 258     case 0x40: /* TAPMR */
 259         s->match_prescale[0] = value;
 260         break;
 261     case 0x44: /* TBPMR */
 262         s->match_prescale[0] = value;
 263         break;
 264     default:
 265         hw_error("gptm_write: Bad offset 0x%x\n", (int)offset);
 266     }
 267     gptm_update_irq(s);
 268 }
 269
 270 static CPUReadMemoryFunc * const gptm_readfn[] = {
 271    gptm_read,
 272    gptm_read,
 273    gptm_read
 274 };
 275
 276 static CPUWriteMemoryFunc * const gptm_writefn[] = {
 277    gptm_write,
 278    gptm_write,
 279    gptm_write
 280 };
 281
 282 static const VMStateDescription vmstate_stellaris_gptm = {
 283     .name = "stellaris_gptm",
 284     .version_id = 1,
 285     .minimum_version_id = 1,
 286     .minimum_version_id_old = 1,
 287     .fields      = (VMStateField[]) {
 288         VMSTATE_UINT32(config, gptm_state),
 289         VMSTATE_UINT32_ARRAY(mode, gptm_state, 2),
 290         VMSTATE_UINT32(control, gptm_state),
 291         VMSTATE_UINT32(state, gptm_state),
 292         VMSTATE_UINT32(mask, gptm_state),
 293         VMSTATE_UNUSED(8),
 294         VMSTATE_UINT32_ARRAY(load, gptm_state, 2),
 295         VMSTATE_UINT32_ARRAY(match, gptm_state, 2),
 296         VMSTATE_UINT32_ARRAY(prescale, gptm_state, 2),
 297         VMSTATE_UINT32_ARRAY(match_prescale, gptm_state, 2),
 298         VMSTATE_UINT32(rtc, gptm_state),
 299         VMSTATE_INT64_ARRAY(tick, gptm_state, 2),
 300         VMSTATE_TIMER_ARRAY(timer, gptm_state, 2),
 301         VMSTATE_END_OF_LIST()
 302     }
 303 };
 304
 305 static int stellaris_gptm_init(SysBusDevice *dev)
 306 {
 307     int iomemtype;
 308     gptm_state *s = FROM_SYSBUS(gptm_state, dev);
 309
 310     sysbus_init_irq(dev, &s->irq);
 311     qdev_init_gpio_out(&dev->qdev, &s->trigger, 1);
 312
 313     iomemtype = cpu_register_io_memory(gptm_readfn,
 314                                        gptm_writefn, s,
 315                                        DEVICE_NATIVE_ENDIAN);
 316     sysbus_init_mmio(dev, 0x1000, iomemtype);
 317
 318     s->opaque[0] = s->opaque[1] = s;
 319     s->timer[0] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[0]);
 320     s->timer[1] = qemu_new_timer_ns(vm_clock, gptm_tick, &s->opaque[1]);
 321     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_gptm, s);
 322     return 0;
 323 }
 324
 325
 326 /* System controller.  */
 327
 328 typedef struct {
 329     uint32_t pborctl;
 330     uint32_t ldopctl;
 331     uint32_t int_status;
 332     uint32_t int_mask;
 333     uint32_t resc;
 334     uint32_t rcc;
 335     uint32_t rcc2;
 336     uint32_t rcgc[3];
 337     uint32_t scgc[3];
 338     uint32_t dcgc[3];
 339     uint32_t clkvclr;
 340     uint32_t ldoarst;
 341     uint32_t user0;
 342     uint32_t user1;
 343     qemu_irq irq;
 344     stellaris_board_info *board;
 345 } ssys_state;
 346
 347 static void ssys_update(ssys_state *s)
 348 {
 349   qemu_set_irq(s->irq, (s->int_status & s->int_mask) != 0);
 350 }
 351
 352 static uint32_t pllcfg_sandstorm[16] = {
 353     0x31c0, /* 1 Mhz */
 354     0x1ae0, /* 1.8432 Mhz */
 355     0x18c0, /* 2 Mhz */
 356     0xd573, /* 2.4576 Mhz */
 357     0x37a6, /* 3.57954 Mhz */
 358     0x1ae2, /* 3.6864 Mhz */
 359     0x0c40, /* 4 Mhz */
 360     0x98bc, /* 4.906 Mhz */
 361     0x935b, /* 4.9152 Mhz */
 362     0x09c0, /* 5 Mhz */
 363     0x4dee, /* 5.12 Mhz */
 364     0x0c41, /* 6 Mhz */
 365     0x75db, /* 6.144 Mhz */
 366     0x1ae6, /* 7.3728 Mhz */
 367     0x0600, /* 8 Mhz */
 368     0x585b /* 8.192 Mhz */
 369 };
 370
 371 static uint32_t pllcfg_fury[16] = {
 372     0x3200, /* 1 Mhz */
 373     0x1b20, /* 1.8432 Mhz */
 374     0x1900, /* 2 Mhz */
 375     0xf42b, /* 2.4576 Mhz */
 376     0x37e3, /* 3.57954 Mhz */
 377     0x1b21, /* 3.6864 Mhz */
 378     0x0c80, /* 4 Mhz */
 379     0x98ee, /* 4.906 Mhz */
 380     0xd5b4, /* 4.9152 Mhz */
 381     0x0a00, /* 5 Mhz */
 382     0x4e27, /* 5.12 Mhz */
 383     0x1902, /* 6 Mhz */
 384     0xec1c, /* 6.144 Mhz */
 385     0x1b23, /* 7.3728 Mhz */
 386     0x0640, /* 8 Mhz */
 387     0xb11c /* 8.192 Mhz */
 388 };
 389
 390 #define DID0_VER_MASK        0x70000000
 391 #define DID0_VER_0           0x00000000
 392 #define DID0_VER_1           0x10000000
 393
 394 #define DID0_CLASS_MASK      0x00FF0000
 395 #define DID0_CLASS_SANDSTORM 0x00000000
 396 #define DID0_CLASS_FURY      0x00010000
 397
 398 static int ssys_board_class(const ssys_state *s)
 399 {
 400     uint32_t did0 = s->board->did0;
 401     switch (did0 & DID0_VER_MASK) {
 402     case DID0_VER_0:
 403         return DID0_CLASS_SANDSTORM;
 404     case DID0_VER_1:
 405         switch (did0 & DID0_CLASS_MASK) {
 406         case DID0_CLASS_SANDSTORM:
 407         case DID0_CLASS_FURY:
 408             return did0 & DID0_CLASS_MASK;
 409         }
 410         /* for unknown classes, fall through */
 411     default:
 412         hw_error("ssys_board_class: Unknown class 0x%08x\n", did0);
 413     }
 414 }
 415
 416 static uint32_t ssys_read(void *opaque, target_phys_addr_t offset)
 417 {
 418     ssys_state *s = (ssys_state *)opaque;
 419
 420     switch (offset) {
 421     case 0x000: /* DID0 */
 422         return s->board->did0;
 423     case 0x004: /* DID1 */
 424         return s->board->did1;
 425     case 0x008: /* DC0 */
 426         return s->board->dc0;
 427     case 0x010: /* DC1 */
 428         return s->board->dc1;
 429     case 0x014: /* DC2 */
 430         return s->board->dc2;
 431     case 0x018: /* DC3 */
 432         return s->board->dc3;
 433     case 0x01c: /* DC4 */
 434         return s->board->dc4;
 435     case 0x030: /* PBORCTL */
 436         return s->pborctl;
 437     case 0x034: /* LDOPCTL */
 438         return s->ldopctl;
 439     case 0x040: /* SRCR0 */
 440         return 0;
 441     case 0x044: /* SRCR1 */
 442         return 0;
 443     case 0x048: /* SRCR2 */
 444         return 0;
 445     case 0x050: /* RIS */
 446         return s->int_status;
 447     case 0x054: /* IMC */
 448         return s->int_mask;
 449     case 0x058: /* MISC */
 450         return s->int_status & s->int_mask;
 451     case 0x05c: /* RESC */
 452         return s->resc;
 453     case 0x060: /* RCC */
 454         return s->rcc;
 455     case 0x064: /* PLLCFG */
 456         {
 457             int xtal;
 458             xtal = (s->rcc >> 6) & 0xf;
 459             switch (ssys_board_class(s)) {
 460             case DID0_CLASS_FURY:
 461                 return pllcfg_fury[xtal];
 462             case DID0_CLASS_SANDSTORM:
 463                 return pllcfg_sandstorm[xtal];
 464             default:
 465                 hw_error("ssys_read: Unhandled class for PLLCFG read.\n");
 466                 return 0;
 467             }
 468         }
 469     case 0x070: /* RCC2 */
 470         return s->rcc2;
 471     case 0x100: /* RCGC0 */
 472         return s->rcgc[0];
 473     case 0x104: /* RCGC1 */
 474         return s->rcgc[1];
 475     case 0x108: /* RCGC2 */
 476         return s->rcgc[2];
 477     case 0x110: /* SCGC0 */
 478         return s->scgc[0];
 479     case 0x114: /* SCGC1 */
 480         return s->scgc[1];
 481     case 0x118: /* SCGC2 */
 482         return s->scgc[2];
 483     case 0x120: /* DCGC0 */
 484         return s->dcgc[0];
 485     case 0x124: /* DCGC1 */
 486         return s->dcgc[1];
 487     case 0x128: /* DCGC2 */
 488         return s->dcgc[2];
 489     case 0x150: /* CLKVCLR */
 490         return s->clkvclr;
 491     case 0x160: /* LDOARST */
 492         return s->ldoarst;
 493     case 0x1e0: /* USER0 */
 494         return s->user0;
 495     case 0x1e4: /* USER1 */
 496         return s->user1;
 497     default:
 498         hw_error("ssys_read: Bad offset 0x%x\n", (int)offset);
 499         return 0;
 500     }
 501 }
 502
 503 static bool ssys_use_rcc2(ssys_state *s)
 504 {
 505     return (s->rcc2 >> 31) & 0x1;
 506 }
 507
 508 /*
 509  * Caculate the sys. clock period in ms.
 510  */
 511 static void ssys_calculate_system_clock(ssys_state *s)
 512 {
 513     if (ssys_use_rcc2(s)) {
 514         system_clock_scale = 5 * (((s->rcc2 >> 23) & 0x3f) + 1);
 515     } else {
 516         system_clock_scale = 5 * (((s->rcc >> 23) & 0xf) + 1);
 517     }
 518 }
 519
 520 static void ssys_write(void *opaque, target_phys_addr_t offset, uint32_t value)
 521 {
 522     ssys_state *s = (ssys_state *)opaque;
 523
 524     switch (offset) {
 525     case 0x030: /* PBORCTL */
 526         s->pborctl = value & 0xffff;
 527         break;
 528     case 0x034: /* LDOPCTL */
 529         s->ldopctl = value & 0x1f;
 530         break;
 531     case 0x040: /* SRCR0 */
 532     case 0x044: /* SRCR1 */
 533     case 0x048: /* SRCR2 */
 534         fprintf(stderr, "Peripheral reset not implemented\n");
 535         break;
 536     case 0x054: /* IMC */
 537         s->int_mask = value & 0x7f;
 538         break;
 539     case 0x058: /* MISC */
 540         s->int_status &= ~value;
 541         break;
 542     case 0x05c: /* RESC */
 543         s->resc = value & 0x3f;
 544         break;
 545     case 0x060: /* RCC */
 546         if ((s->rcc & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 547             /* PLL enable.  */
 548             s->int_status |= (1 << 6);
 549         }
 550         s->rcc = value;
 551         ssys_calculate_system_clock(s);
 552         break;
 553     case 0x070: /* RCC2 */
 554         if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 555             break;
 556         }
 557
 558         if ((s->rcc2 & (1 << 13)) != 0 && (value & (1 << 13)) == 0) {
 559             /* PLL enable.  */
 560             s->int_status |= (1 << 6);
 561         }
 562         s->rcc2 = value;
 563         ssys_calculate_system_clock(s);
 564         break;
 565     case 0x100: /* RCGC0 */
 566         s->rcgc[0] = value;
 567         break;
 568     case 0x104: /* RCGC1 */
 569         s->rcgc[1] = value;
 570         break;
 571     case 0x108: /* RCGC2 */
 572         s->rcgc[2] = value;
 573         break;
 574     case 0x110: /* SCGC0 */
 575         s->scgc[0] = value;
 576         break;
 577     case 0x114: /* SCGC1 */
 578         s->scgc[1] = value;
 579         break;
 580     case 0x118: /* SCGC2 */
 581         s->scgc[2] = value;
 582         break;
 583     case 0x120: /* DCGC0 */
 584         s->dcgc[0] = value;
 585         break;
 586     case 0x124: /* DCGC1 */
 587         s->dcgc[1] = value;
 588         break;
 589     case 0x128: /* DCGC2 */
 590         s->dcgc[2] = value;
 591         break;
 592     case 0x150: /* CLKVCLR */
 593         s->clkvclr = value;
 594         break;
 595     case 0x160: /* LDOARST */
 596         s->ldoarst = value;
 597         break;
 598     default:
 599         hw_error("ssys_write: Bad offset 0x%x\n", (int)offset);
 600     }
 601     ssys_update(s);
 602 }
 603
 604 static CPUReadMemoryFunc * const ssys_readfn[] = {
 605    ssys_read,
 606    ssys_read,
 607    ssys_read
 608 };
 609
 610 static CPUWriteMemoryFunc * const ssys_writefn[] = {
 611    ssys_write,
 612    ssys_write,
 613    ssys_write
 614 };
 615
 616 static void ssys_reset(void *opaque)
 617 {
 618     ssys_state *s = (ssys_state *)opaque;
 619
 620     s->pborctl = 0x7ffd;
 621     s->rcc = 0x078e3ac0;
 622
 623     if (ssys_board_class(s) == DID0_CLASS_SANDSTORM) {
 624         s->rcc2 = 0;
 625     } else {
 626         s->rcc2 = 0x07802810;
 627     }
 628     s->rcgc[0] = 1;
 629     s->scgc[0] = 1;
 630     s->dcgc[0] = 1;
 631 }
 632
 633 static int stellaris_sys_post_load(void *opaque, int version_id)
 634 {
 635     ssys_state *s = opaque;
 636
 637     ssys_calculate_system_clock(s);
 638
 639     return 0;
 640 }
 641
 642 static const VMStateDescription vmstate_stellaris_sys = {
 643     .name = "stellaris_sys",
 644     .version_id = 2,
 645     .minimum_version_id = 1,
 646     .minimum_version_id_old = 1,
 647     .post_load = stellaris_sys_post_load,
 648     .fields      = (VMStateField[]) {
 649         VMSTATE_UINT32(pborctl, ssys_state),
 650         VMSTATE_UINT32(ldopctl, ssys_state),
 651         VMSTATE_UINT32(int_mask, ssys_state),
 652         VMSTATE_UINT32(int_status, ssys_state),
 653         VMSTATE_UINT32(resc, ssys_state),
 654         VMSTATE_UINT32(rcc, ssys_state),
 655         VMSTATE_UINT32_V(rcc2, ssys_state, 2),
 656         VMSTATE_UINT32_ARRAY(rcgc, ssys_state, 3),
 657         VMSTATE_UINT32_ARRAY(scgc, ssys_state, 3),
 658         VMSTATE_UINT32_ARRAY(dcgc, ssys_state, 3),
 659         VMSTATE_UINT32(clkvclr, ssys_state),
 660         VMSTATE_UINT32(ldoarst, ssys_state),
 661         VMSTATE_END_OF_LIST()
 662     }
 663 };
 664
 665 static int stellaris_sys_init(uint32_t base, qemu_irq irq,
 666                               stellaris_board_info * board,
 667                               uint8_t *macaddr)
 668 {
 669     int iomemtype;
 670     ssys_state *s;
 671
 672     s = (ssys_state *)g_malloc0(sizeof(ssys_state));
 673     s->irq = irq;
 674     s->board = board;
 675     /* Most devices come preprogrammed with a MAC address in the user data. */
 676     s->user0 = macaddr[0] | (macaddr[1] << 8) | (macaddr[2] << 16);
 677     s->user1 = macaddr[3] | (macaddr[4] << 8) | (macaddr[5] << 16);
 678
 679     iomemtype = cpu_register_io_memory(ssys_readfn,
 680                                        ssys_writefn, s,
 681                                        DEVICE_NATIVE_ENDIAN);
 682     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 683     ssys_reset(s);
 684     vmstate_register(NULL, -1, &vmstate_stellaris_sys, s);
 685     return 0;
 686 }
 687
 688
 689 /* I2C controller.  */
 690
 691 typedef struct {
 692     SysBusDevice busdev;
 693     i2c_bus *bus;
 694     qemu_irq irq;
 695     uint32_t msa;
 696     uint32_t mcs;
 697     uint32_t mdr;
 698     uint32_t mtpr;
 699     uint32_t mimr;
 700     uint32_t mris;
 701     uint32_t mcr;
 702 } stellaris_i2c_state;
 703
 704 #define STELLARIS_I2C_MCS_BUSY    0x01
 705 #define STELLARIS_I2C_MCS_ERROR   0x02
 706 #define STELLARIS_I2C_MCS_ADRACK  0x04
 707 #define STELLARIS_I2C_MCS_DATACK  0x08
 708 #define STELLARIS_I2C_MCS_ARBLST  0x10
 709 #define STELLARIS_I2C_MCS_IDLE    0x20
 710 #define STELLARIS_I2C_MCS_BUSBSY  0x40
 711
 712 static uint32_t stellaris_i2c_read(void *opaque, target_phys_addr_t offset)
 713 {
 714     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 715
 716     switch (offset) {
 717     case 0x00: /* MSA */
 718         return s->msa;
 719     case 0x04: /* MCS */
 720         /* We don't emulate timing, so the controller is never busy.  */
 721         return s->mcs | STELLARIS_I2C_MCS_IDLE;
 722     case 0x08: /* MDR */
 723         return s->mdr;
 724     case 0x0c: /* MTPR */
 725         return s->mtpr;
 726     case 0x10: /* MIMR */
 727         return s->mimr;
 728     case 0x14: /* MRIS */
 729         return s->mris;
 730     case 0x18: /* MMIS */
 731         return s->mris & s->mimr;
 732     case 0x20: /* MCR */
 733         return s->mcr;
 734     default:
 735         hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset);
 736         return 0;
 737     }
 738 }
 739
 740 static void stellaris_i2c_update(stellaris_i2c_state *s)
 741 {
 742     int level;
 743
 744     level = (s->mris & s->mimr) != 0;
 745     qemu_set_irq(s->irq, level);
 746 }
 747
 748 static void stellaris_i2c_write(void *opaque, target_phys_addr_t offset,
 749                                 uint32_t value)
 750 {
 751     stellaris_i2c_state *s = (stellaris_i2c_state *)opaque;
 752
 753     switch (offset) {
 754     case 0x00: /* MSA */
 755         s->msa = value & 0xff;
 756         break;
 757     case 0x04: /* MCS */
 758         if ((s->mcr & 0x10) == 0) {
 759             /* Disabled.  Do nothing.  */
 760             break;
 761         }
 762         /* Grab the bus if this is starting a transfer.  */
 763         if ((value & 2) && (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 764             if (i2c_start_transfer(s->bus, s->msa >> 1, s->msa & 1)) {
 765                 s->mcs |= STELLARIS_I2C_MCS_ARBLST;
 766             } else {
 767                 s->mcs &= ~STELLARIS_I2C_MCS_ARBLST;
 768                 s->mcs |= STELLARIS_I2C_MCS_BUSBSY;
 769             }
 770         }
 771         /* If we don't have the bus then indicate an error.  */
 772         if (!i2c_bus_busy(s->bus)
 773                 || (s->mcs & STELLARIS_I2C_MCS_BUSBSY) == 0) {
 774             s->mcs |= STELLARIS_I2C_MCS_ERROR;
 775             break;
 776         }
 777         s->mcs &= ~STELLARIS_I2C_MCS_ERROR;
 778         if (value & 1) {
 779             /* Transfer a byte.  */
 780             /* TODO: Handle errors.  */
 781             if (s->msa & 1) {
 782                 /* Recv */
 783                 s->mdr = i2c_recv(s->bus) & 0xff;
 784             } else {
 785                 /* Send */
 786                 i2c_send(s->bus, s->mdr);
 787             }
 788             /* Raise an interrupt.  */
 789             s->mris |= 1;
 790         }
 791         if (value & 4) {
 792             /* Finish transfer.  */
 793             i2c_end_transfer(s->bus);
 794             s->mcs &= ~STELLARIS_I2C_MCS_BUSBSY;
 795         }
 796         break;
 797     case 0x08: /* MDR */
 798         s->mdr = value & 0xff;
 799         break;
 800     case 0x0c: /* MTPR */
 801         s->mtpr = value & 0xff;
 802         break;
 803     case 0x10: /* MIMR */
 804         s->mimr = 1;
 805         break;
 806     case 0x1c: /* MICR */
 807         s->mris &= ~value;
 808         break;
 809     case 0x20: /* MCR */
 810         if (value & 1)
 811             hw_error(
 812                       "stellaris_i2c_write: Loopback not implemented\n");
 813         if (value & 0x20)
 814             hw_error(
 815                       "stellaris_i2c_write: Slave mode not implemented\n");
 816         s->mcr = value & 0x31;
 817         break;
 818     default:
 819         hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
 820                   (int)offset);
 821     }
 822     stellaris_i2c_update(s);
 823 }
 824
 825 static void stellaris_i2c_reset(stellaris_i2c_state *s)
 826 {
 827     if (s->mcs & STELLARIS_I2C_MCS_BUSBSY)
 828         i2c_end_transfer(s->bus);
 829
 830     s->msa = 0;
 831     s->mcs = 0;
 832     s->mdr = 0;
 833     s->mtpr = 1;
 834     s->mimr = 0;
 835     s->mris = 0;
 836     s->mcr = 0;
 837     stellaris_i2c_update(s);
 838 }
 839
 840 static CPUReadMemoryFunc * const stellaris_i2c_readfn[] = {
 841    stellaris_i2c_read,
 842    stellaris_i2c_read,
 843    stellaris_i2c_read
 844 };
 845
 846 static CPUWriteMemoryFunc * const stellaris_i2c_writefn[] = {
 847    stellaris_i2c_write,
 848    stellaris_i2c_write,
 849    stellaris_i2c_write
 850 };
 851
 852 static const VMStateDescription vmstate_stellaris_i2c = {
 853     .name = "stellaris_i2c",
 854     .version_id = 1,
 855     .minimum_version_id = 1,
 856     .minimum_version_id_old = 1,
 857     .fields      = (VMStateField[]) {
 858         VMSTATE_UINT32(msa, stellaris_i2c_state),
 859         VMSTATE_UINT32(mcs, stellaris_i2c_state),
 860         VMSTATE_UINT32(mdr, stellaris_i2c_state),
 861         VMSTATE_UINT32(mtpr, stellaris_i2c_state),
 862         VMSTATE_UINT32(mimr, stellaris_i2c_state),
 863         VMSTATE_UINT32(mris, stellaris_i2c_state),
 864         VMSTATE_UINT32(mcr, stellaris_i2c_state),
 865         VMSTATE_END_OF_LIST()
 866     }
 867 };
 868
 869 static int stellaris_i2c_init(SysBusDevice * dev)
 870 {
 871     stellaris_i2c_state *s = FROM_SYSBUS(stellaris_i2c_state, dev);
 872     i2c_bus *bus;
 873     int iomemtype;
 874
 875     sysbus_init_irq(dev, &s->irq);
 876     bus = i2c_init_bus(&dev->qdev, "i2c");
 877     s->bus = bus;
 878
 879     iomemtype = cpu_register_io_memory(stellaris_i2c_readfn,
 880                                        stellaris_i2c_writefn, s,
 881                                        DEVICE_NATIVE_ENDIAN);
 882     sysbus_init_mmio(dev, 0x1000, iomemtype);
 883     /* ??? For now we only implement the master interface.  */
 884     stellaris_i2c_reset(s);
 885     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_i2c, s);
 886     return 0;
 887 }
 888
 889 /* Analogue to Digital Converter.  This is only partially implemented,
 890    enough for applications that use a combined ADC and timer tick.  */
 891
 892 #define STELLARIS_ADC_EM_CONTROLLER 0
 893 #define STELLARIS_ADC_EM_COMP       1
 894 #define STELLARIS_ADC_EM_EXTERNAL   4
 895 #define STELLARIS_ADC_EM_TIMER      5
 896 #define STELLARIS_ADC_EM_PWM0       6
 897 #define STELLARIS_ADC_EM_PWM1       7
 898 #define STELLARIS_ADC_EM_PWM2       8
 899
 900 #define STELLARIS_ADC_FIFO_EMPTY    0x0100
 901 #define STELLARIS_ADC_FIFO_FULL     0x1000
 902
 903 typedef struct
 904 {
 905     SysBusDevice busdev;
 906     uint32_t actss;
 907     uint32_t ris;
 908     uint32_t im;
 909     uint32_t emux;
 910     uint32_t ostat;
 911     uint32_t ustat;
 912     uint32_t sspri;
 913     uint32_t sac;
 914     struct {
 915         uint32_t state;
 916         uint32_t data[16];
 917     } fifo[4];
 918     uint32_t ssmux[4];
 919     uint32_t ssctl[4];
 920     uint32_t noise;
 921     qemu_irq irq[4];
 922 } stellaris_adc_state;
 923
 924 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state *s, int n)
 925 {
 926     int tail;
 927
 928     tail = s->fifo[n].state & 0xf;
 929     if (s->fifo[n].state & STELLARIS_ADC_FIFO_EMPTY) {
 930         s->ustat |= 1 << n;
 931     } else {
 932         s->fifo[n].state = (s->fifo[n].state & ~0xf) | ((tail + 1) & 0xf);
 933         s->fifo[n].state &= ~STELLARIS_ADC_FIFO_FULL;
 934         if (tail + 1 == ((s->fifo[n].state >> 4) & 0xf))
 935             s->fifo[n].state |= STELLARIS_ADC_FIFO_EMPTY;
 936     }
 937     return s->fifo[n].data[tail];
 938 }
 939
 940 static void stellaris_adc_fifo_write(stellaris_adc_state *s, int n,
 941                                      uint32_t value)
 942 {
 943     int head;
 944
 945     /* TODO: Real hardware has limited size FIFOs.  We have a full 16 entry
 946        FIFO fir each sequencer.  */
 947     head = (s->fifo[n].state >> 4) & 0xf;
 948     if (s->fifo[n].state & STELLARIS_ADC_FIFO_FULL) {
 949         s->ostat |= 1 << n;
 950         return;
 951     }
 952     s->fifo[n].data[head] = value;
 953     head = (head + 1) & 0xf;
 954     s->fifo[n].state &= ~STELLARIS_ADC_FIFO_EMPTY;
 955     s->fifo[n].state = (s->fifo[n].state & ~0xf0) | (head << 4);
 956     if ((s->fifo[n].state & 0xf) == head)
 957         s->fifo[n].state |= STELLARIS_ADC_FIFO_FULL;
 958 }
 959
 960 static void stellaris_adc_update(stellaris_adc_state *s)
 961 {
 962     int level;
 963     int n;
 964
 965     for (n = 0; n < 4; n++) {
 966         level = (s->ris & s->im & (1 << n)) != 0;
 967         qemu_set_irq(s->irq[n], level);
 968     }
 969 }
 970
 971 static void stellaris_adc_trigger(void *opaque, int irq, int level)
 972 {
 973     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
 974     int n;
 975
 976     for (n = 0; n < 4; n++) {
 977         if ((s->actss & (1 << n)) == 0) {
 978             continue;
 979         }
 980
 981         if (((s->emux >> (n * 4)) & 0xff) != 5) {
 982             continue;
 983         }
 984
 985         /* Some applications use the ADC as a random number source, so introduce
 986            some variation into the signal.  */
 987         s->noise = s->noise * 314159 + 1;
 988         /* ??? actual inputs not implemented.  Return an arbitrary value.  */
 989         stellaris_adc_fifo_write(s, n, 0x200 + ((s->noise >> 16) & 7));
 990         s->ris |= (1 << n);
 991         stellaris_adc_update(s);
 992     }
 993 }
 994
 995 static void stellaris_adc_reset(stellaris_adc_state *s)
 996 {
 997     int n;
 998
 999     for (n = 0; n < 4; n++) {
1000         s->ssmux[n] = 0;
1001         s->ssctl[n] = 0;
1002         s->fifo[n].state = STELLARIS_ADC_FIFO_EMPTY;
1003     }
1004 }
1005
1006 static uint32_t stellaris_adc_read(void *opaque, target_phys_addr_t offset)
1007 {
1008     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1009
1010     /* TODO: Implement this.  */
1011     if (offset >= 0x40 && offset < 0xc0) {
1012         int n;
1013         n = (offset - 0x40) >> 5;
1014         switch (offset & 0x1f) {
1015         case 0x00: /* SSMUX */
1016             return s->ssmux[n];
1017         case 0x04: /* SSCTL */
1018             return s->ssctl[n];
1019         case 0x08: /* SSFIFO */
1020             return stellaris_adc_fifo_read(s, n);
1021         case 0x0c: /* SSFSTAT */
1022             return s->fifo[n].state;
1023         default:
1024             break;
1025         }
1026     }
1027     switch (offset) {
1028     case 0x00: /* ACTSS */
1029         return s->actss;
1030     case 0x04: /* RIS */
1031         return s->ris;
1032     case 0x08: /* IM */
1033         return s->im;
1034     case 0x0c: /* ISC */
1035         return s->ris & s->im;
1036     case 0x10: /* OSTAT */
1037         return s->ostat;
1038     case 0x14: /* EMUX */
1039         return s->emux;
1040     case 0x18: /* USTAT */
1041         return s->ustat;
1042     case 0x20: /* SSPRI */
1043         return s->sspri;
1044     case 0x30: /* SAC */
1045         return s->sac;
1046     default:
1047         hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1048                   (int)offset);
1049         return 0;
1050     }
1051 }
1052
1053 static void stellaris_adc_write(void *opaque, target_phys_addr_t offset,
1054                                 uint32_t value)
1055 {
1056     stellaris_adc_state *s = (stellaris_adc_state *)opaque;
1057
1058     /* TODO: Implement this.  */
1059     if (offset >= 0x40 && offset < 0xc0) {
1060         int n;
1061         n = (offset - 0x40) >> 5;
1062         switch (offset & 0x1f) {
1063         case 0x00: /* SSMUX */
1064             s->ssmux[n] = value & 0x33333333;
1065             return;
1066         case 0x04: /* SSCTL */
1067             if (value != 6) {
1068                 hw_error("ADC: Unimplemented sequence %x\n",
1069                           value);
1070             }
1071             s->ssctl[n] = value;
1072             return;
1073         default:
1074             break;
1075         }
1076     }
1077     switch (offset) {
1078     case 0x00: /* ACTSS */
1079         s->actss = value & 0xf;
1080         break;
1081     case 0x08: /* IM */
1082         s->im = value;
1083         break;
1084     case 0x0c: /* ISC */
1085         s->ris &= ~value;
1086         break;
1087     case 0x10: /* OSTAT */
1088         s->ostat &= ~value;
1089         break;
1090     case 0x14: /* EMUX */
1091         s->emux = value;
1092         break;
1093     case 0x18: /* USTAT */
1094         s->ustat &= ~value;
1095         break;
1096     case 0x20: /* SSPRI */
1097         s->sspri = value;
1098         break;
1099     case 0x28: /* PSSI */
1100         hw_error("Not implemented:  ADC sample initiate\n");
1101         break;
1102     case 0x30: /* SAC */
1103         s->sac = value;
1104         break;
1105     default:
1106         hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset);
1107     }
1108     stellaris_adc_update(s);
1109 }
1110
1111 static CPUReadMemoryFunc * const stellaris_adc_readfn[] = {
1112    stellaris_adc_read,
1113    stellaris_adc_read,
1114    stellaris_adc_read
1115 };
1116
1117 static CPUWriteMemoryFunc * const stellaris_adc_writefn[] = {
1118    stellaris_adc_write,
1119    stellaris_adc_write,
1120    stellaris_adc_write
1121 };
1122
1123 static const VMStateDescription vmstate_stellaris_adc = {
1124     .name = "stellaris_adc",
1125     .version_id = 1,
1126     .minimum_version_id = 1,
1127     .minimum_version_id_old = 1,
1128     .fields      = (VMStateField[]) {
1129         VMSTATE_UINT32(actss, stellaris_adc_state),
1130         VMSTATE_UINT32(ris, stellaris_adc_state),
1131         VMSTATE_UINT32(im, stellaris_adc_state),
1132         VMSTATE_UINT32(emux, stellaris_adc_state),
1133         VMSTATE_UINT32(ostat, stellaris_adc_state),
1134         VMSTATE_UINT32(ustat, stellaris_adc_state),
1135         VMSTATE_UINT32(sspri, stellaris_adc_state),
1136         VMSTATE_UINT32(sac, stellaris_adc_state),
1137         VMSTATE_UINT32(fifo[0].state, stellaris_adc_state),
1138         VMSTATE_UINT32_ARRAY(fifo[0].data, stellaris_adc_state, 16),
1139         VMSTATE_UINT32(ssmux[0], stellaris_adc_state),
1140         VMSTATE_UINT32(ssctl[0], stellaris_adc_state),
1141         VMSTATE_UINT32(fifo[1].state, stellaris_adc_state),
1142         VMSTATE_UINT32_ARRAY(fifo[1].data, stellaris_adc_state, 16),
1143         VMSTATE_UINT32(ssmux[1], stellaris_adc_state),
1144         VMSTATE_UINT32(ssctl[1], stellaris_adc_state),
1145         VMSTATE_UINT32(fifo[2].state, stellaris_adc_state),
1146         VMSTATE_UINT32_ARRAY(fifo[2].data, stellaris_adc_state, 16),
1147         VMSTATE_UINT32(ssmux[2], stellaris_adc_state),
1148         VMSTATE_UINT32(ssctl[2], stellaris_adc_state),
1149         VMSTATE_UINT32(fifo[3].state, stellaris_adc_state),
1150         VMSTATE_UINT32_ARRAY(fifo[3].data, stellaris_adc_state, 16),
1151         VMSTATE_UINT32(ssmux[3], stellaris_adc_state),
1152         VMSTATE_UINT32(ssctl[3], stellaris_adc_state),
1153         VMSTATE_UINT32(noise, stellaris_adc_state),
1154         VMSTATE_END_OF_LIST()
1155     }
1156 };
1157
1158 static int stellaris_adc_init(SysBusDevice *dev)
1159 {
1160     stellaris_adc_state *s = FROM_SYSBUS(stellaris_adc_state, dev);
1161     int iomemtype;
1162     int n;
1163
1164     for (n = 0; n < 4; n++) {
1165         sysbus_init_irq(dev, &s->irq[n]);
1166     }
1167
1168     iomemtype = cpu_register_io_memory(stellaris_adc_readfn,
1169                                        stellaris_adc_writefn, s,
1170                                        DEVICE_NATIVE_ENDIAN);
1171     sysbus_init_mmio(dev, 0x1000, iomemtype);
1172     stellaris_adc_reset(s);
1173     qdev_init_gpio_in(&dev->qdev, stellaris_adc_trigger, 1);
1174     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_adc, s);
1175     return 0;
1176 }
1177
1178 /* Some boards have both an OLED controller and SD card connected to
1179    the same SSI port, with the SD card chip select connected to a
1180    GPIO pin.  Technically the OLED chip select is connected to the SSI
1181    Fss pin.  We do not bother emulating that as both devices should
1182    never be selected simultaneously, and our OLED controller ignores stray
1183    0xff commands that occur when deselecting the SD card.  */
1184
1185 typedef struct {
1186     SSISlave ssidev;
1187     qemu_irq irq;
1188     int current_dev;
1189     SSIBus *bus[2];
1190 } stellaris_ssi_bus_state;
1191
1192 static void stellaris_ssi_bus_select(void *opaque, int irq, int level)
1193 {
1194     stellaris_ssi_bus_state *s = (stellaris_ssi_bus_state *)opaque;
1195
1196     s->current_dev = level;
1197 }
1198
1199 static uint32_t stellaris_ssi_bus_transfer(SSISlave *dev, uint32_t val)
1200 {
1201     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1202
1203     return ssi_transfer(s->bus[s->current_dev], val);
1204 }
1205
1206 static const VMStateDescription vmstate_stellaris_ssi_bus = {
1207     .name = "stellaris_ssi_bus",
1208     .version_id = 1,
1209     .minimum_version_id = 1,
1210     .minimum_version_id_old = 1,
1211     .fields      = (VMStateField[]) {
1212         VMSTATE_INT32(current_dev, stellaris_ssi_bus_state),
1213         VMSTATE_END_OF_LIST()
1214     }
1215 };
1216
1217 static int stellaris_ssi_bus_init(SSISlave *dev)
1218 {
1219     stellaris_ssi_bus_state *s = FROM_SSI_SLAVE(stellaris_ssi_bus_state, dev);
1220
1221     s->bus[0] = ssi_create_bus(&dev->qdev, "ssi0");
1222     s->bus[1] = ssi_create_bus(&dev->qdev, "ssi1");
1223     qdev_init_gpio_in(&dev->qdev, stellaris_ssi_bus_select, 1);
1224
1225     vmstate_register(&dev->qdev, -1, &vmstate_stellaris_ssi_bus, s);
1226     return 0;
1227 }
1228
1229 /* Board init.  */
1230 static stellaris_board_info stellaris_boards[] = {
1231   { "LM3S811EVB",
1232     0,
1233     0x0032000e,
1234     0x001f001f, /* dc0 */
1235     0x001132bf,
1236     0x01071013,
1237     0x3f0f01ff,
1238     0x0000001f,
1239     BP_OLED_I2C
1240   },
1241   { "LM3S6965EVB",
1242     0x10010002,
1243     0x1073402e,
1244     0x00ff007f, /* dc0 */
1245     0x001133ff,
1246     0x030f5317,
1247     0x0f0f87ff,
1248     0x5000007f,
1249     BP_OLED_SSI | BP_GAMEPAD
1250   }
1251 };
1252
1253 static void stellaris_init(const char *kernel_filename, const char *cpu_model,
1254                            stellaris_board_info *board)
1255 {
1256     static const int uart_irq[] = {5, 6, 33, 34};
1257     static const int timer_irq[] = {19, 21, 23, 35};
1258     static const uint32_t gpio_addr[7] =
1259       { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1260         0x40024000, 0x40025000, 0x40026000};
1261     static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
1262
1263     qemu_irq *pic;
1264     DeviceState *gpio_dev[7];
1265     qemu_irq gpio_in[7][8];
1266     qemu_irq gpio_out[7][8];
1267     qemu_irq adc;
1268     int sram_size;
1269     int flash_size;
1270     i2c_bus *i2c;
1271     DeviceState *dev;
1272     int i;
1273     int j;
1274
1275     flash_size = ((board->dc0 & 0xffff) + 1) << 1;
1276     sram_size = (board->dc0 >> 18) + 1;
1277     pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
1278
1279     if (board->dc1 & (1 << 16)) {
1280         dev = sysbus_create_varargs("stellaris-adc", 0x40038000,
1281                                     pic[14], pic[15], pic[16], pic[17], NULL);
1282         adc = qdev_get_gpio_in(dev, 0);
1283     } else {
1284         adc = NULL;
1285     }
1286     for (i = 0; i < 4; i++) {
1287         if (board->dc2 & (0x10000 << i)) {
1288             dev = sysbus_create_simple("stellaris-gptm",
1289                                        0x40030000 + i * 0x1000,
1290                                        pic[timer_irq[i]]);
1291             /* TODO: This is incorrect, but we get away with it because
1292                the ADC output is only ever pulsed.  */
1293             qdev_connect_gpio_out(dev, 0, adc);
1294         }
1295     }
1296
1297     stellaris_sys_init(0x400fe000, pic[28], board, nd_table[0].macaddr.a);
1298
1299     for (i = 0; i < 7; i++) {
1300         if (board->dc4 & (1 << i)) {
1301             gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
1302                                                pic[gpio_irq[i]]);
1303             for (j = 0; j < 8; j++) {
1304                 gpio_in[i][j] = qdev_get_gpio_in(gpio_dev[i], j);
1305                 gpio_out[i][j] = NULL;
1306             }
1307         }
1308     }
1309
1310     if (board->dc2 & (1 << 12)) {
1311         dev = sysbus_create_simple("stellaris-i2c", 0x40020000, pic[8]);
1312         i2c = (i2c_bus *)qdev_get_child_bus(dev, "i2c");
1313         if (board->peripherals & BP_OLED_I2C) {
1314             i2c_create_slave(i2c, "ssd0303", 0x3d);
1315         }
1316     }
1317
1318     for (i = 0; i < 4; i++) {
1319         if (board->dc2 & (1 << i)) {
1320             sysbus_create_simple("pl011_luminary", 0x4000c000 + i * 0x1000,
1321                                  pic[uart_irq[i]]);
1322         }
1323     }
1324     if (board->dc2 & (1 << 4)) {
1325         dev = sysbus_create_simple("pl022", 0x40008000, pic[7]);
1326         if (board->peripherals & BP_OLED_SSI) {
1327             DeviceState *mux;
1328             void *bus;
1329
1330             bus = qdev_get_child_bus(dev, "ssi");
1331             mux = ssi_create_slave(bus, "evb6965-ssi");
1332             gpio_out[GPIO_D][0] = qdev_get_gpio_in(mux, 0);
1333
1334             bus = qdev_get_child_bus(mux, "ssi0");
1335             ssi_create_slave(bus, "ssi-sd");
1336
1337             bus = qdev_get_child_bus(mux, "ssi1");
1338             dev = ssi_create_slave(bus, "ssd0323");
1339             gpio_out[GPIO_C][7] = qdev_get_gpio_in(dev, 0);
1340
1341             /* Make sure the select pin is high.  */
1342             qemu_irq_raise(gpio_out[GPIO_D][0]);
1343         }
1344     }
1345     if (board->dc4 & (1 << 28)) {
1346         DeviceState *enet;
1347
1348         qemu_check_nic_model(&nd_table[0], "stellaris");
1349
1350         enet = qdev_create(NULL, "stellaris_enet");
1351         qdev_set_nic_properties(enet, &nd_table[0]);
1352         qdev_init_nofail(enet);
1353         sysbus_mmio_map(sysbus_from_qdev(enet), 0, 0x40048000);
1354         sysbus_connect_irq(sysbus_from_qdev(enet), 0, pic[42]);
1355     }
1356     if (board->peripherals & BP_GAMEPAD) {
1357         qemu_irq gpad_irq[5];
1358         static const int gpad_keycode[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1359
1360         gpad_irq[0] = qemu_irq_invert(gpio_in[GPIO_E][0]); /* up */
1361         gpad_irq[1] = qemu_irq_invert(gpio_in[GPIO_E][1]); /* down */
1362         gpad_irq[2] = qemu_irq_invert(gpio_in[GPIO_E][2]); /* left */
1363         gpad_irq[3] = qemu_irq_invert(gpio_in[GPIO_E][3]); /* right */
1364         gpad_irq[4] = qemu_irq_invert(gpio_in[GPIO_F][1]); /* select */
1365
1366         stellaris_gamepad_init(5, gpad_irq, gpad_keycode);
1367     }
1368     for (i = 0; i < 7; i++) {
1369         if (board->dc4 & (1 << i)) {
1370             for (j = 0; j < 8; j++) {
1371                 if (gpio_out[i][j]) {
1372                     qdev_connect_gpio_out(gpio_dev[i], j, gpio_out[i][j]);
1373                 }
1374             }
1375         }
1376     }
1377 }
1378
1379 /* FIXME: Figure out how to generate these from stellaris_boards.  */
1380 static void lm3s811evb_init(ram_addr_t ram_size,
1381                      const char *boot_device,
1382                      const char *kernel_filename, const char *kernel_cmdline,
1383                      const char *initrd_filename, const char *cpu_model)
1384 {
1385     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[0]);
1386 }
1387
1388 static void lm3s6965evb_init(ram_addr_t ram_size,
1389                      const char *boot_device,
1390                      const char *kernel_filename, const char *kernel_cmdline,
1391                      const char *initrd_filename, const char *cpu_model)
1392 {
1393     stellaris_init(kernel_filename, cpu_model, &stellaris_boards[1]);
1394 }
1395
1396 static QEMUMachine lm3s811evb_machine = {
1397     .name = "lm3s811evb",
1398     .desc = "Stellaris LM3S811EVB",
1399     .init = lm3s811evb_init,
1400 };
1401
1402 static QEMUMachine lm3s6965evb_machine = {
1403     .name = "lm3s6965evb",
1404     .desc = "Stellaris LM3S6965EVB",
1405     .init = lm3s6965evb_init,
1406 };
1407
1408 static void stellaris_machine_init(void)
1409 {
1410     qemu_register_machine(&lm3s811evb_machine);
1411     qemu_register_machine(&lm3s6965evb_machine);
1412 }
1413
1414 machine_init(stellaris_machine_init);
1415
1416 static SSISlaveInfo stellaris_ssi_bus_info = {
1417     .qdev.name = "evb6965-ssi",
1418     .qdev.size = sizeof(stellaris_ssi_bus_state),
1419     .init = stellaris_ssi_bus_init,
1420     .transfer = stellaris_ssi_bus_transfer
1421 };
1422
1423 static void stellaris_register_devices(void)
1424 {
1425     sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state),
1426                         stellaris_i2c_init);
1427     sysbus_register_dev("stellaris-gptm", sizeof(gptm_state),
1428                         stellaris_gptm_init);
1429     sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state),
1430                         stellaris_adc_init);
1431     ssi_register_slave(&stellaris_ssi_bus_info);
1432 }
1433
1434 device_init(stellaris_register_devices)