2 * Luminary Micro Stellaris peripherals
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
14 #include "qemu-timer.h"
27 #define BP_OLED_I2C 0x01
28 #define BP_OLED_SSI 0x02
29 #define BP_GAMEPAD 0x04
31 typedef const struct {
41 } stellaris_board_info
;
43 /* General purpose timer module. */
45 typedef struct gptm_state
{
55 uint32_t match_prescale
[2];
58 struct gptm_state
*opaque
[2];
60 /* The timers have an alternate output used to trigger the ADC. */
65 static void gptm_update_irq(gptm_state
*s
)
68 level
= (s
->state
& s
->mask
) != 0;
69 qemu_set_irq(s
->irq
, level
);
72 static void gptm_stop(gptm_state
*s
, int n
)
74 qemu_del_timer(s
->timer
[n
]);
77 static void gptm_reload(gptm_state
*s
, int n
, int reset
)
81 tick
= qemu_get_clock_ns(vm_clock
);
86 /* 32-bit CountDown. */
88 count
= s
->load
[0] | (s
->load
[1] << 16);
89 tick
+= (int64_t)count
* system_clock_scale
;
90 } else if (s
->config
== 1) {
91 /* 32-bit RTC. 1Hz tick. */
92 tick
+= get_ticks_per_sec();
93 } else if (s
->mode
[n
] == 0xa) {
94 /* PWM mode. Not implemented. */
96 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
99 qemu_mod_timer(s
->timer
[n
], tick
);
102 static void gptm_tick(void *opaque
)
104 gptm_state
**p
= (gptm_state
**)opaque
;
110 if (s
->config
== 0) {
112 if ((s
->control
& 0x20)) {
113 /* Output trigger. */
114 qemu_irq_pulse(s
->trigger
);
116 if (s
->mode
[0] & 1) {
121 gptm_reload(s
, 0, 0);
123 } else if (s
->config
== 1) {
127 match
= s
->match
[0] | (s
->match
[1] << 16);
133 gptm_reload(s
, 0, 0);
134 } else if (s
->mode
[n
] == 0xa) {
135 /* PWM mode. Not implemented. */
137 hw_error("TODO: 16-bit timer mode 0x%x\n", s
->mode
[n
]);
142 static uint32_t gptm_read(void *opaque
, target_phys_addr_t offset
)
144 gptm_state
*s
= (gptm_state
*)opaque
;
149 case 0x04: /* TAMR */
151 case 0x08: /* TBMR */
160 return s
->state
& s
->mask
;
163 case 0x28: /* TAILR */
164 return s
->load
[0] | ((s
->config
< 4) ? (s
->load
[1] << 16) : 0);
165 case 0x2c: /* TBILR */
167 case 0x30: /* TAMARCHR */
168 return s
->match
[0] | ((s
->config
< 4) ? (s
->match
[1] << 16) : 0);
169 case 0x34: /* TBMATCHR */
171 case 0x38: /* TAPR */
172 return s
->prescale
[0];
173 case 0x3c: /* TBPR */
174 return s
->prescale
[1];
175 case 0x40: /* TAPMR */
176 return s
->match_prescale
[0];
177 case 0x44: /* TBPMR */
178 return s
->match_prescale
[1];
183 hw_error("TODO: Timer value read\n");
185 hw_error("gptm_read: Bad offset 0x%x\n", (int)offset
);
190 static void gptm_write(void *opaque
, target_phys_addr_t offset
, uint32_t value
)
192 gptm_state
*s
= (gptm_state
*)opaque
;
195 /* The timers should be disabled before changing the configuration.
196 We take advantage of this and defer everything until the timer
202 case 0x04: /* TAMR */
205 case 0x08: /* TBMR */
211 /* TODO: Implement pause. */
212 if ((oldval
^ value
) & 1) {
214 gptm_reload(s
, 0, 1);
219 if (((oldval
^ value
) & 0x100) && s
->config
>= 4) {
221 gptm_reload(s
, 1, 1);
228 s
->mask
= value
& 0x77;
234 case 0x28: /* TAILR */
235 s
->load
[0] = value
& 0xffff;
237 s
->load
[1] = value
>> 16;
240 case 0x2c: /* TBILR */
241 s
->load
[1] = value
& 0xffff;
243 case 0x30: /* TAMARCHR */
244 s
->match
[0] = value
& 0xffff;
246 s
->match
[1] = value
>> 16;
249 case 0x34: /* TBMATCHR */
250 s
->match
[1] = value
>> 16;
252 case 0x38: /* TAPR */
253 s
->prescale
[0] = value
;
255 case 0x3c: /* TBPR */
256 s
->prescale
[1] = value
;
258 case 0x40: /* TAPMR */
259 s
->match_prescale
[0] = value
;
261 case 0x44: /* TBPMR */
262 s
->match_prescale
[0] = value
;
265 hw_error("gptm_write: Bad offset 0x%x\n", (int)offset
);
270 static CPUReadMemoryFunc
* const gptm_readfn
[] = {
276 static CPUWriteMemoryFunc
* const gptm_writefn
[] = {
282 static void gptm_save(QEMUFile
*f
, void *opaque
)
284 gptm_state
*s
= (gptm_state
*)opaque
;
286 qemu_put_be32(f
, s
->config
);
287 qemu_put_be32(f
, s
->mode
[0]);
288 qemu_put_be32(f
, s
->mode
[1]);
289 qemu_put_be32(f
, s
->control
);
290 qemu_put_be32(f
, s
->state
);
291 qemu_put_be32(f
, s
->mask
);
292 qemu_put_be32(f
, s
->mode
[0]);
293 qemu_put_be32(f
, s
->mode
[0]);
294 qemu_put_be32(f
, s
->load
[0]);
295 qemu_put_be32(f
, s
->load
[1]);
296 qemu_put_be32(f
, s
->match
[0]);
297 qemu_put_be32(f
, s
->match
[1]);
298 qemu_put_be32(f
, s
->prescale
[0]);
299 qemu_put_be32(f
, s
->prescale
[1]);
300 qemu_put_be32(f
, s
->match_prescale
[0]);
301 qemu_put_be32(f
, s
->match_prescale
[1]);
302 qemu_put_be32(f
, s
->rtc
);
303 qemu_put_be64(f
, s
->tick
[0]);
304 qemu_put_be64(f
, s
->tick
[1]);
305 qemu_put_timer(f
, s
->timer
[0]);
306 qemu_put_timer(f
, s
->timer
[1]);
309 static int gptm_load(QEMUFile
*f
, void *opaque
, int version_id
)
311 gptm_state
*s
= (gptm_state
*)opaque
;
316 s
->config
= qemu_get_be32(f
);
317 s
->mode
[0] = qemu_get_be32(f
);
318 s
->mode
[1] = qemu_get_be32(f
);
319 s
->control
= qemu_get_be32(f
);
320 s
->state
= qemu_get_be32(f
);
321 s
->mask
= qemu_get_be32(f
);
322 s
->mode
[0] = qemu_get_be32(f
);
323 s
->mode
[0] = qemu_get_be32(f
);
324 s
->load
[0] = qemu_get_be32(f
);
325 s
->load
[1] = qemu_get_be32(f
);
326 s
->match
[0] = qemu_get_be32(f
);
327 s
->match
[1] = qemu_get_be32(f
);
328 s
->prescale
[0] = qemu_get_be32(f
);
329 s
->prescale
[1] = qemu_get_be32(f
);
330 s
->match_prescale
[0] = qemu_get_be32(f
);
331 s
->match_prescale
[1] = qemu_get_be32(f
);
332 s
->rtc
= qemu_get_be32(f
);
333 s
->tick
[0] = qemu_get_be64(f
);
334 s
->tick
[1] = qemu_get_be64(f
);
335 qemu_get_timer(f
, s
->timer
[0]);
336 qemu_get_timer(f
, s
->timer
[1]);
341 static int stellaris_gptm_init(SysBusDevice
*dev
)
344 gptm_state
*s
= FROM_SYSBUS(gptm_state
, dev
);
346 sysbus_init_irq(dev
, &s
->irq
);
347 qdev_init_gpio_out(&dev
->qdev
, &s
->trigger
, 1);
349 iomemtype
= cpu_register_io_memory(gptm_readfn
,
351 DEVICE_NATIVE_ENDIAN
);
352 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
354 s
->opaque
[0] = s
->opaque
[1] = s
;
355 s
->timer
[0] = qemu_new_timer_ns(vm_clock
, gptm_tick
, &s
->opaque
[0]);
356 s
->timer
[1] = qemu_new_timer_ns(vm_clock
, gptm_tick
, &s
->opaque
[1]);
357 register_savevm(&dev
->qdev
, "stellaris_gptm", -1, 1,
358 gptm_save
, gptm_load
, s
);
363 /* System controller. */
380 stellaris_board_info
*board
;
383 static void ssys_update(ssys_state
*s
)
385 qemu_set_irq(s
->irq
, (s
->int_status
& s
->int_mask
) != 0);
388 static uint32_t pllcfg_sandstorm
[16] = {
390 0x1ae0, /* 1.8432 Mhz */
392 0xd573, /* 2.4576 Mhz */
393 0x37a6, /* 3.57954 Mhz */
394 0x1ae2, /* 3.6864 Mhz */
396 0x98bc, /* 4.906 Mhz */
397 0x935b, /* 4.9152 Mhz */
399 0x4dee, /* 5.12 Mhz */
401 0x75db, /* 6.144 Mhz */
402 0x1ae6, /* 7.3728 Mhz */
404 0x585b /* 8.192 Mhz */
407 static uint32_t pllcfg_fury
[16] = {
409 0x1b20, /* 1.8432 Mhz */
411 0xf42b, /* 2.4576 Mhz */
412 0x37e3, /* 3.57954 Mhz */
413 0x1b21, /* 3.6864 Mhz */
415 0x98ee, /* 4.906 Mhz */
416 0xd5b4, /* 4.9152 Mhz */
418 0x4e27, /* 5.12 Mhz */
420 0xec1c, /* 6.144 Mhz */
421 0x1b23, /* 7.3728 Mhz */
423 0xb11c /* 8.192 Mhz */
426 static uint32_t ssys_read(void *opaque
, target_phys_addr_t offset
)
428 ssys_state
*s
= (ssys_state
*)opaque
;
431 case 0x000: /* DID0 */
432 return s
->board
->did0
;
433 case 0x004: /* DID1 */
434 return s
->board
->did1
;
435 case 0x008: /* DC0 */
436 return s
->board
->dc0
;
437 case 0x010: /* DC1 */
438 return s
->board
->dc1
;
439 case 0x014: /* DC2 */
440 return s
->board
->dc2
;
441 case 0x018: /* DC3 */
442 return s
->board
->dc3
;
443 case 0x01c: /* DC4 */
444 return s
->board
->dc4
;
445 case 0x030: /* PBORCTL */
447 case 0x034: /* LDOPCTL */
449 case 0x040: /* SRCR0 */
451 case 0x044: /* SRCR1 */
453 case 0x048: /* SRCR2 */
455 case 0x050: /* RIS */
456 return s
->int_status
;
457 case 0x054: /* IMC */
459 case 0x058: /* MISC */
460 return s
->int_status
& s
->int_mask
;
461 case 0x05c: /* RESC */
463 case 0x060: /* RCC */
465 case 0x064: /* PLLCFG */
468 xtal
= (s
->rcc
>> 6) & 0xf;
469 if (s
->board
->did0
& (1 << 16)) {
470 return pllcfg_fury
[xtal
];
472 return pllcfg_sandstorm
[xtal
];
475 case 0x100: /* RCGC0 */
477 case 0x104: /* RCGC1 */
479 case 0x108: /* RCGC2 */
481 case 0x110: /* SCGC0 */
483 case 0x114: /* SCGC1 */
485 case 0x118: /* SCGC2 */
487 case 0x120: /* DCGC0 */
489 case 0x124: /* DCGC1 */
491 case 0x128: /* DCGC2 */
493 case 0x150: /* CLKVCLR */
495 case 0x160: /* LDOARST */
497 case 0x1e0: /* USER0 */
499 case 0x1e4: /* USER1 */
502 hw_error("ssys_read: Bad offset 0x%x\n", (int)offset
);
507 static void ssys_calculate_system_clock(ssys_state
*s
)
509 system_clock_scale
= 5 * (((s
->rcc
>> 23) & 0xf) + 1);
512 static void ssys_write(void *opaque
, target_phys_addr_t offset
, uint32_t value
)
514 ssys_state
*s
= (ssys_state
*)opaque
;
517 case 0x030: /* PBORCTL */
518 s
->pborctl
= value
& 0xffff;
520 case 0x034: /* LDOPCTL */
521 s
->ldopctl
= value
& 0x1f;
523 case 0x040: /* SRCR0 */
524 case 0x044: /* SRCR1 */
525 case 0x048: /* SRCR2 */
526 fprintf(stderr
, "Peripheral reset not implemented\n");
528 case 0x054: /* IMC */
529 s
->int_mask
= value
& 0x7f;
531 case 0x058: /* MISC */
532 s
->int_status
&= ~value
;
534 case 0x05c: /* RESC */
535 s
->resc
= value
& 0x3f;
537 case 0x060: /* RCC */
538 if ((s
->rcc
& (1 << 13)) != 0 && (value
& (1 << 13)) == 0) {
540 s
->int_status
|= (1 << 6);
543 ssys_calculate_system_clock(s
);
545 case 0x100: /* RCGC0 */
548 case 0x104: /* RCGC1 */
551 case 0x108: /* RCGC2 */
554 case 0x110: /* SCGC0 */
557 case 0x114: /* SCGC1 */
560 case 0x118: /* SCGC2 */
563 case 0x120: /* DCGC0 */
566 case 0x124: /* DCGC1 */
569 case 0x128: /* DCGC2 */
572 case 0x150: /* CLKVCLR */
575 case 0x160: /* LDOARST */
579 hw_error("ssys_write: Bad offset 0x%x\n", (int)offset
);
584 static CPUReadMemoryFunc
* const ssys_readfn
[] = {
590 static CPUWriteMemoryFunc
* const ssys_writefn
[] = {
596 static void ssys_reset(void *opaque
)
598 ssys_state
*s
= (ssys_state
*)opaque
;
607 static void ssys_save(QEMUFile
*f
, void *opaque
)
609 ssys_state
*s
= (ssys_state
*)opaque
;
611 qemu_put_be32(f
, s
->pborctl
);
612 qemu_put_be32(f
, s
->ldopctl
);
613 qemu_put_be32(f
, s
->int_mask
);
614 qemu_put_be32(f
, s
->int_status
);
615 qemu_put_be32(f
, s
->resc
);
616 qemu_put_be32(f
, s
->rcc
);
617 qemu_put_be32(f
, s
->rcgc
[0]);
618 qemu_put_be32(f
, s
->rcgc
[1]);
619 qemu_put_be32(f
, s
->rcgc
[2]);
620 qemu_put_be32(f
, s
->scgc
[0]);
621 qemu_put_be32(f
, s
->scgc
[1]);
622 qemu_put_be32(f
, s
->scgc
[2]);
623 qemu_put_be32(f
, s
->dcgc
[0]);
624 qemu_put_be32(f
, s
->dcgc
[1]);
625 qemu_put_be32(f
, s
->dcgc
[2]);
626 qemu_put_be32(f
, s
->clkvclr
);
627 qemu_put_be32(f
, s
->ldoarst
);
630 static int ssys_load(QEMUFile
*f
, void *opaque
, int version_id
)
632 ssys_state
*s
= (ssys_state
*)opaque
;
637 s
->pborctl
= qemu_get_be32(f
);
638 s
->ldopctl
= qemu_get_be32(f
);
639 s
->int_mask
= qemu_get_be32(f
);
640 s
->int_status
= qemu_get_be32(f
);
641 s
->resc
= qemu_get_be32(f
);
642 s
->rcc
= qemu_get_be32(f
);
643 s
->rcgc
[0] = qemu_get_be32(f
);
644 s
->rcgc
[1] = qemu_get_be32(f
);
645 s
->rcgc
[2] = qemu_get_be32(f
);
646 s
->scgc
[0] = qemu_get_be32(f
);
647 s
->scgc
[1] = qemu_get_be32(f
);
648 s
->scgc
[2] = qemu_get_be32(f
);
649 s
->dcgc
[0] = qemu_get_be32(f
);
650 s
->dcgc
[1] = qemu_get_be32(f
);
651 s
->dcgc
[2] = qemu_get_be32(f
);
652 s
->clkvclr
= qemu_get_be32(f
);
653 s
->ldoarst
= qemu_get_be32(f
);
654 ssys_calculate_system_clock(s
);
659 static int stellaris_sys_init(uint32_t base
, qemu_irq irq
,
660 stellaris_board_info
* board
,
666 s
= (ssys_state
*)qemu_mallocz(sizeof(ssys_state
));
669 /* Most devices come preprogrammed with a MAC address in the user data. */
670 s
->user0
= macaddr
[0] | (macaddr
[1] << 8) | (macaddr
[2] << 16);
671 s
->user1
= macaddr
[3] | (macaddr
[4] << 8) | (macaddr
[5] << 16);
673 iomemtype
= cpu_register_io_memory(ssys_readfn
,
675 DEVICE_NATIVE_ENDIAN
);
676 cpu_register_physical_memory(base
, 0x00001000, iomemtype
);
678 register_savevm(NULL
, "stellaris_sys", -1, 1, ssys_save
, ssys_load
, s
);
683 /* I2C controller. */
696 } stellaris_i2c_state
;
698 #define STELLARIS_I2C_MCS_BUSY 0x01
699 #define STELLARIS_I2C_MCS_ERROR 0x02
700 #define STELLARIS_I2C_MCS_ADRACK 0x04
701 #define STELLARIS_I2C_MCS_DATACK 0x08
702 #define STELLARIS_I2C_MCS_ARBLST 0x10
703 #define STELLARIS_I2C_MCS_IDLE 0x20
704 #define STELLARIS_I2C_MCS_BUSBSY 0x40
706 static uint32_t stellaris_i2c_read(void *opaque
, target_phys_addr_t offset
)
708 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
714 /* We don't emulate timing, so the controller is never busy. */
715 return s
->mcs
| STELLARIS_I2C_MCS_IDLE
;
718 case 0x0c: /* MTPR */
720 case 0x10: /* MIMR */
722 case 0x14: /* MRIS */
724 case 0x18: /* MMIS */
725 return s
->mris
& s
->mimr
;
729 hw_error("strllaris_i2c_read: Bad offset 0x%x\n", (int)offset
);
734 static void stellaris_i2c_update(stellaris_i2c_state
*s
)
738 level
= (s
->mris
& s
->mimr
) != 0;
739 qemu_set_irq(s
->irq
, level
);
742 static void stellaris_i2c_write(void *opaque
, target_phys_addr_t offset
,
745 stellaris_i2c_state
*s
= (stellaris_i2c_state
*)opaque
;
749 s
->msa
= value
& 0xff;
752 if ((s
->mcr
& 0x10) == 0) {
753 /* Disabled. Do nothing. */
756 /* Grab the bus if this is starting a transfer. */
757 if ((value
& 2) && (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
758 if (i2c_start_transfer(s
->bus
, s
->msa
>> 1, s
->msa
& 1)) {
759 s
->mcs
|= STELLARIS_I2C_MCS_ARBLST
;
761 s
->mcs
&= ~STELLARIS_I2C_MCS_ARBLST
;
762 s
->mcs
|= STELLARIS_I2C_MCS_BUSBSY
;
765 /* If we don't have the bus then indicate an error. */
766 if (!i2c_bus_busy(s
->bus
)
767 || (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
) == 0) {
768 s
->mcs
|= STELLARIS_I2C_MCS_ERROR
;
771 s
->mcs
&= ~STELLARIS_I2C_MCS_ERROR
;
773 /* Transfer a byte. */
774 /* TODO: Handle errors. */
777 s
->mdr
= i2c_recv(s
->bus
) & 0xff;
780 i2c_send(s
->bus
, s
->mdr
);
782 /* Raise an interrupt. */
786 /* Finish transfer. */
787 i2c_end_transfer(s
->bus
);
788 s
->mcs
&= ~STELLARIS_I2C_MCS_BUSBSY
;
792 s
->mdr
= value
& 0xff;
794 case 0x0c: /* MTPR */
795 s
->mtpr
= value
& 0xff;
797 case 0x10: /* MIMR */
800 case 0x1c: /* MICR */
806 "stellaris_i2c_write: Loopback not implemented\n");
809 "stellaris_i2c_write: Slave mode not implemented\n");
810 s
->mcr
= value
& 0x31;
813 hw_error("stellaris_i2c_write: Bad offset 0x%x\n",
816 stellaris_i2c_update(s
);
819 static void stellaris_i2c_reset(stellaris_i2c_state
*s
)
821 if (s
->mcs
& STELLARIS_I2C_MCS_BUSBSY
)
822 i2c_end_transfer(s
->bus
);
831 stellaris_i2c_update(s
);
834 static CPUReadMemoryFunc
* const stellaris_i2c_readfn
[] = {
840 static CPUWriteMemoryFunc
* const stellaris_i2c_writefn
[] = {
846 static const VMStateDescription vmstate_stellaris_i2c
= {
847 .name
= "stellaris_i2c",
849 .minimum_version_id
= 1,
850 .minimum_version_id_old
= 1,
851 .fields
= (VMStateField
[]) {
852 VMSTATE_UINT32(msa
, stellaris_i2c_state
),
853 VMSTATE_UINT32(mcs
, stellaris_i2c_state
),
854 VMSTATE_UINT32(mdr
, stellaris_i2c_state
),
855 VMSTATE_UINT32(mtpr
, stellaris_i2c_state
),
856 VMSTATE_UINT32(mimr
, stellaris_i2c_state
),
857 VMSTATE_UINT32(mris
, stellaris_i2c_state
),
858 VMSTATE_UINT32(mcr
, stellaris_i2c_state
),
859 VMSTATE_END_OF_LIST()
863 static int stellaris_i2c_init(SysBusDevice
* dev
)
865 stellaris_i2c_state
*s
= FROM_SYSBUS(stellaris_i2c_state
, dev
);
869 sysbus_init_irq(dev
, &s
->irq
);
870 bus
= i2c_init_bus(&dev
->qdev
, "i2c");
873 iomemtype
= cpu_register_io_memory(stellaris_i2c_readfn
,
874 stellaris_i2c_writefn
, s
,
875 DEVICE_NATIVE_ENDIAN
);
876 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
877 /* ??? For now we only implement the master interface. */
878 stellaris_i2c_reset(s
);
879 vmstate_register(&dev
->qdev
, -1, &vmstate_stellaris_i2c
, s
);
883 /* Analogue to Digital Converter. This is only partially implemented,
884 enough for applications that use a combined ADC and timer tick. */
886 #define STELLARIS_ADC_EM_CONTROLLER 0
887 #define STELLARIS_ADC_EM_COMP 1
888 #define STELLARIS_ADC_EM_EXTERNAL 4
889 #define STELLARIS_ADC_EM_TIMER 5
890 #define STELLARIS_ADC_EM_PWM0 6
891 #define STELLARIS_ADC_EM_PWM1 7
892 #define STELLARIS_ADC_EM_PWM2 8
894 #define STELLARIS_ADC_FIFO_EMPTY 0x0100
895 #define STELLARIS_ADC_FIFO_FULL 0x1000
916 } stellaris_adc_state
;
918 static uint32_t stellaris_adc_fifo_read(stellaris_adc_state
*s
, int n
)
922 tail
= s
->fifo
[n
].state
& 0xf;
923 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_EMPTY
) {
926 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf) | ((tail
+ 1) & 0xf);
927 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_FULL
;
928 if (tail
+ 1 == ((s
->fifo
[n
].state
>> 4) & 0xf))
929 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_EMPTY
;
931 return s
->fifo
[n
].data
[tail
];
934 static void stellaris_adc_fifo_write(stellaris_adc_state
*s
, int n
,
939 /* TODO: Real hardware has limited size FIFOs. We have a full 16 entry
940 FIFO fir each sequencer. */
941 head
= (s
->fifo
[n
].state
>> 4) & 0xf;
942 if (s
->fifo
[n
].state
& STELLARIS_ADC_FIFO_FULL
) {
946 s
->fifo
[n
].data
[head
] = value
;
947 head
= (head
+ 1) & 0xf;
948 s
->fifo
[n
].state
&= ~STELLARIS_ADC_FIFO_EMPTY
;
949 s
->fifo
[n
].state
= (s
->fifo
[n
].state
& ~0xf0) | (head
<< 4);
950 if ((s
->fifo
[n
].state
& 0xf) == head
)
951 s
->fifo
[n
].state
|= STELLARIS_ADC_FIFO_FULL
;
954 static void stellaris_adc_update(stellaris_adc_state
*s
)
959 for (n
= 0; n
< 4; n
++) {
960 level
= (s
->ris
& s
->im
& (1 << n
)) != 0;
961 qemu_set_irq(s
->irq
[n
], level
);
965 static void stellaris_adc_trigger(void *opaque
, int irq
, int level
)
967 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
970 for (n
= 0; n
< 4; n
++) {
971 if ((s
->actss
& (1 << n
)) == 0) {
975 if (((s
->emux
>> (n
* 4)) & 0xff) != 5) {
979 /* Some applications use the ADC as a random number source, so introduce
980 some variation into the signal. */
981 s
->noise
= s
->noise
* 314159 + 1;
982 /* ??? actual inputs not implemented. Return an arbitrary value. */
983 stellaris_adc_fifo_write(s
, n
, 0x200 + ((s
->noise
>> 16) & 7));
985 stellaris_adc_update(s
);
989 static void stellaris_adc_reset(stellaris_adc_state
*s
)
993 for (n
= 0; n
< 4; n
++) {
996 s
->fifo
[n
].state
= STELLARIS_ADC_FIFO_EMPTY
;
1000 static uint32_t stellaris_adc_read(void *opaque
, target_phys_addr_t offset
)
1002 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1004 /* TODO: Implement this. */
1005 if (offset
>= 0x40 && offset
< 0xc0) {
1007 n
= (offset
- 0x40) >> 5;
1008 switch (offset
& 0x1f) {
1009 case 0x00: /* SSMUX */
1011 case 0x04: /* SSCTL */
1013 case 0x08: /* SSFIFO */
1014 return stellaris_adc_fifo_read(s
, n
);
1015 case 0x0c: /* SSFSTAT */
1016 return s
->fifo
[n
].state
;
1022 case 0x00: /* ACTSS */
1024 case 0x04: /* RIS */
1028 case 0x0c: /* ISC */
1029 return s
->ris
& s
->im
;
1030 case 0x10: /* OSTAT */
1032 case 0x14: /* EMUX */
1034 case 0x18: /* USTAT */
1036 case 0x20: /* SSPRI */
1038 case 0x30: /* SAC */
1041 hw_error("strllaris_adc_read: Bad offset 0x%x\n",
1047 static void stellaris_adc_write(void *opaque
, target_phys_addr_t offset
,
1050 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1052 /* TODO: Implement this. */
1053 if (offset
>= 0x40 && offset
< 0xc0) {
1055 n
= (offset
- 0x40) >> 5;
1056 switch (offset
& 0x1f) {
1057 case 0x00: /* SSMUX */
1058 s
->ssmux
[n
] = value
& 0x33333333;
1060 case 0x04: /* SSCTL */
1062 hw_error("ADC: Unimplemented sequence %x\n",
1065 s
->ssctl
[n
] = value
;
1072 case 0x00: /* ACTSS */
1073 s
->actss
= value
& 0xf;
1078 case 0x0c: /* ISC */
1081 case 0x10: /* OSTAT */
1084 case 0x14: /* EMUX */
1087 case 0x18: /* USTAT */
1090 case 0x20: /* SSPRI */
1093 case 0x28: /* PSSI */
1094 hw_error("Not implemented: ADC sample initiate\n");
1096 case 0x30: /* SAC */
1100 hw_error("stellaris_adc_write: Bad offset 0x%x\n", (int)offset
);
1102 stellaris_adc_update(s
);
1105 static CPUReadMemoryFunc
* const stellaris_adc_readfn
[] = {
1111 static CPUWriteMemoryFunc
* const stellaris_adc_writefn
[] = {
1112 stellaris_adc_write
,
1113 stellaris_adc_write
,
1117 static void stellaris_adc_save(QEMUFile
*f
, void *opaque
)
1119 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1123 qemu_put_be32(f
, s
->actss
);
1124 qemu_put_be32(f
, s
->ris
);
1125 qemu_put_be32(f
, s
->im
);
1126 qemu_put_be32(f
, s
->emux
);
1127 qemu_put_be32(f
, s
->ostat
);
1128 qemu_put_be32(f
, s
->ustat
);
1129 qemu_put_be32(f
, s
->sspri
);
1130 qemu_put_be32(f
, s
->sac
);
1131 for (i
= 0; i
< 4; i
++) {
1132 qemu_put_be32(f
, s
->fifo
[i
].state
);
1133 for (j
= 0; j
< 16; j
++) {
1134 qemu_put_be32(f
, s
->fifo
[i
].data
[j
]);
1136 qemu_put_be32(f
, s
->ssmux
[i
]);
1137 qemu_put_be32(f
, s
->ssctl
[i
]);
1139 qemu_put_be32(f
, s
->noise
);
1142 static int stellaris_adc_load(QEMUFile
*f
, void *opaque
, int version_id
)
1144 stellaris_adc_state
*s
= (stellaris_adc_state
*)opaque
;
1148 if (version_id
!= 1)
1151 s
->actss
= qemu_get_be32(f
);
1152 s
->ris
= qemu_get_be32(f
);
1153 s
->im
= qemu_get_be32(f
);
1154 s
->emux
= qemu_get_be32(f
);
1155 s
->ostat
= qemu_get_be32(f
);
1156 s
->ustat
= qemu_get_be32(f
);
1157 s
->sspri
= qemu_get_be32(f
);
1158 s
->sac
= qemu_get_be32(f
);
1159 for (i
= 0; i
< 4; i
++) {
1160 s
->fifo
[i
].state
= qemu_get_be32(f
);
1161 for (j
= 0; j
< 16; j
++) {
1162 s
->fifo
[i
].data
[j
] = qemu_get_be32(f
);
1164 s
->ssmux
[i
] = qemu_get_be32(f
);
1165 s
->ssctl
[i
] = qemu_get_be32(f
);
1167 s
->noise
= qemu_get_be32(f
);
1172 static int stellaris_adc_init(SysBusDevice
*dev
)
1174 stellaris_adc_state
*s
= FROM_SYSBUS(stellaris_adc_state
, dev
);
1178 for (n
= 0; n
< 4; n
++) {
1179 sysbus_init_irq(dev
, &s
->irq
[n
]);
1182 iomemtype
= cpu_register_io_memory(stellaris_adc_readfn
,
1183 stellaris_adc_writefn
, s
,
1184 DEVICE_NATIVE_ENDIAN
);
1185 sysbus_init_mmio(dev
, 0x1000, iomemtype
);
1186 stellaris_adc_reset(s
);
1187 qdev_init_gpio_in(&dev
->qdev
, stellaris_adc_trigger
, 1);
1188 register_savevm(&dev
->qdev
, "stellaris_adc", -1, 1,
1189 stellaris_adc_save
, stellaris_adc_load
, s
);
1193 /* Some boards have both an OLED controller and SD card connected to
1194 the same SSI port, with the SD card chip select connected to a
1195 GPIO pin. Technically the OLED chip select is connected to the SSI
1196 Fss pin. We do not bother emulating that as both devices should
1197 never be selected simultaneously, and our OLED controller ignores stray
1198 0xff commands that occur when deselecting the SD card. */
1205 } stellaris_ssi_bus_state
;
1207 static void stellaris_ssi_bus_select(void *opaque
, int irq
, int level
)
1209 stellaris_ssi_bus_state
*s
= (stellaris_ssi_bus_state
*)opaque
;
1211 s
->current_dev
= level
;
1214 static uint32_t stellaris_ssi_bus_transfer(SSISlave
*dev
, uint32_t val
)
1216 stellaris_ssi_bus_state
*s
= FROM_SSI_SLAVE(stellaris_ssi_bus_state
, dev
);
1218 return ssi_transfer(s
->bus
[s
->current_dev
], val
);
1221 static void stellaris_ssi_bus_save(QEMUFile
*f
, void *opaque
)
1223 stellaris_ssi_bus_state
*s
= (stellaris_ssi_bus_state
*)opaque
;
1225 qemu_put_be32(f
, s
->current_dev
);
1228 static int stellaris_ssi_bus_load(QEMUFile
*f
, void *opaque
, int version_id
)
1230 stellaris_ssi_bus_state
*s
= (stellaris_ssi_bus_state
*)opaque
;
1232 if (version_id
!= 1)
1235 s
->current_dev
= qemu_get_be32(f
);
1240 static int stellaris_ssi_bus_init(SSISlave
*dev
)
1242 stellaris_ssi_bus_state
*s
= FROM_SSI_SLAVE(stellaris_ssi_bus_state
, dev
);
1244 s
->bus
[0] = ssi_create_bus(&dev
->qdev
, "ssi0");
1245 s
->bus
[1] = ssi_create_bus(&dev
->qdev
, "ssi1");
1246 qdev_init_gpio_in(&dev
->qdev
, stellaris_ssi_bus_select
, 1);
1248 register_savevm(&dev
->qdev
, "stellaris_ssi_bus", -1, 1,
1249 stellaris_ssi_bus_save
, stellaris_ssi_bus_load
, s
);
1254 static stellaris_board_info stellaris_boards
[] = {
1258 0x001f001f, /* dc0 */
1268 0x00ff007f, /* dc0 */
1273 BP_OLED_SSI
| BP_GAMEPAD
1277 static void stellaris_init(const char *kernel_filename
, const char *cpu_model
,
1278 stellaris_board_info
*board
)
1280 static const int uart_irq
[] = {5, 6, 33, 34};
1281 static const int timer_irq
[] = {19, 21, 23, 35};
1282 static const uint32_t gpio_addr
[7] =
1283 { 0x40004000, 0x40005000, 0x40006000, 0x40007000,
1284 0x40024000, 0x40025000, 0x40026000};
1285 static const int gpio_irq
[7] = {0, 1, 2, 3, 4, 30, 31};
1288 DeviceState
*gpio_dev
[7];
1289 qemu_irq gpio_in
[7][8];
1290 qemu_irq gpio_out
[7][8];
1299 flash_size
= ((board
->dc0
& 0xffff) + 1) << 1;
1300 sram_size
= (board
->dc0
>> 18) + 1;
1301 pic
= armv7m_init(flash_size
, sram_size
, kernel_filename
, cpu_model
);
1303 if (board
->dc1
& (1 << 16)) {
1304 dev
= sysbus_create_varargs("stellaris-adc", 0x40038000,
1305 pic
[14], pic
[15], pic
[16], pic
[17], NULL
);
1306 adc
= qdev_get_gpio_in(dev
, 0);
1310 for (i
= 0; i
< 4; i
++) {
1311 if (board
->dc2
& (0x10000 << i
)) {
1312 dev
= sysbus_create_simple("stellaris-gptm",
1313 0x40030000 + i
* 0x1000,
1315 /* TODO: This is incorrect, but we get away with it because
1316 the ADC output is only ever pulsed. */
1317 qdev_connect_gpio_out(dev
, 0, adc
);
1321 stellaris_sys_init(0x400fe000, pic
[28], board
, nd_table
[0].macaddr
);
1323 for (i
= 0; i
< 7; i
++) {
1324 if (board
->dc4
& (1 << i
)) {
1325 gpio_dev
[i
] = sysbus_create_simple("pl061_luminary", gpio_addr
[i
],
1327 for (j
= 0; j
< 8; j
++) {
1328 gpio_in
[i
][j
] = qdev_get_gpio_in(gpio_dev
[i
], j
);
1329 gpio_out
[i
][j
] = NULL
;
1334 if (board
->dc2
& (1 << 12)) {
1335 dev
= sysbus_create_simple("stellaris-i2c", 0x40020000, pic
[8]);
1336 i2c
= (i2c_bus
*)qdev_get_child_bus(dev
, "i2c");
1337 if (board
->peripherals
& BP_OLED_I2C
) {
1338 i2c_create_slave(i2c
, "ssd0303", 0x3d);
1342 for (i
= 0; i
< 4; i
++) {
1343 if (board
->dc2
& (1 << i
)) {
1344 sysbus_create_simple("pl011_luminary", 0x4000c000 + i
* 0x1000,
1348 if (board
->dc2
& (1 << 4)) {
1349 dev
= sysbus_create_simple("pl022", 0x40008000, pic
[7]);
1350 if (board
->peripherals
& BP_OLED_SSI
) {
1354 bus
= qdev_get_child_bus(dev
, "ssi");
1355 mux
= ssi_create_slave(bus
, "evb6965-ssi");
1356 gpio_out
[GPIO_D
][0] = qdev_get_gpio_in(mux
, 0);
1358 bus
= qdev_get_child_bus(mux
, "ssi0");
1359 ssi_create_slave(bus
, "ssi-sd");
1361 bus
= qdev_get_child_bus(mux
, "ssi1");
1362 dev
= ssi_create_slave(bus
, "ssd0323");
1363 gpio_out
[GPIO_C
][7] = qdev_get_gpio_in(dev
, 0);
1365 /* Make sure the select pin is high. */
1366 qemu_irq_raise(gpio_out
[GPIO_D
][0]);
1369 if (board
->dc4
& (1 << 28)) {
1372 qemu_check_nic_model(&nd_table
[0], "stellaris");
1374 enet
= qdev_create(NULL
, "stellaris_enet");
1375 qdev_set_nic_properties(enet
, &nd_table
[0]);
1376 qdev_init_nofail(enet
);
1377 sysbus_mmio_map(sysbus_from_qdev(enet
), 0, 0x40048000);
1378 sysbus_connect_irq(sysbus_from_qdev(enet
), 0, pic
[42]);
1380 if (board
->peripherals
& BP_GAMEPAD
) {
1381 qemu_irq gpad_irq
[5];
1382 static const int gpad_keycode
[5] = { 0xc8, 0xd0, 0xcb, 0xcd, 0x1d };
1384 gpad_irq
[0] = qemu_irq_invert(gpio_in
[GPIO_E
][0]); /* up */
1385 gpad_irq
[1] = qemu_irq_invert(gpio_in
[GPIO_E
][1]); /* down */
1386 gpad_irq
[2] = qemu_irq_invert(gpio_in
[GPIO_E
][2]); /* left */
1387 gpad_irq
[3] = qemu_irq_invert(gpio_in
[GPIO_E
][3]); /* right */
1388 gpad_irq
[4] = qemu_irq_invert(gpio_in
[GPIO_F
][1]); /* select */
1390 stellaris_gamepad_init(5, gpad_irq
, gpad_keycode
);
1392 for (i
= 0; i
< 7; i
++) {
1393 if (board
->dc4
& (1 << i
)) {
1394 for (j
= 0; j
< 8; j
++) {
1395 if (gpio_out
[i
][j
]) {
1396 qdev_connect_gpio_out(gpio_dev
[i
], j
, gpio_out
[i
][j
]);
1403 /* FIXME: Figure out how to generate these from stellaris_boards. */
1404 static void lm3s811evb_init(ram_addr_t ram_size
,
1405 const char *boot_device
,
1406 const char *kernel_filename
, const char *kernel_cmdline
,
1407 const char *initrd_filename
, const char *cpu_model
)
1409 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[0]);
1412 static void lm3s6965evb_init(ram_addr_t ram_size
,
1413 const char *boot_device
,
1414 const char *kernel_filename
, const char *kernel_cmdline
,
1415 const char *initrd_filename
, const char *cpu_model
)
1417 stellaris_init(kernel_filename
, cpu_model
, &stellaris_boards
[1]);
1420 static QEMUMachine lm3s811evb_machine
= {
1421 .name
= "lm3s811evb",
1422 .desc
= "Stellaris LM3S811EVB",
1423 .init
= lm3s811evb_init
,
1426 static QEMUMachine lm3s6965evb_machine
= {
1427 .name
= "lm3s6965evb",
1428 .desc
= "Stellaris LM3S6965EVB",
1429 .init
= lm3s6965evb_init
,
1432 static void stellaris_machine_init(void)
1434 qemu_register_machine(&lm3s811evb_machine
);
1435 qemu_register_machine(&lm3s6965evb_machine
);
1438 machine_init(stellaris_machine_init
);
1440 static SSISlaveInfo stellaris_ssi_bus_info
= {
1441 .qdev
.name
= "evb6965-ssi",
1442 .qdev
.size
= sizeof(stellaris_ssi_bus_state
),
1443 .init
= stellaris_ssi_bus_init
,
1444 .transfer
= stellaris_ssi_bus_transfer
1447 static void stellaris_register_devices(void)
1449 sysbus_register_dev("stellaris-i2c", sizeof(stellaris_i2c_state
),
1450 stellaris_i2c_init
);
1451 sysbus_register_dev("stellaris-gptm", sizeof(gptm_state
),
1452 stellaris_gptm_init
);
1453 sysbus_register_dev("stellaris-adc", sizeof(stellaris_adc_state
),
1454 stellaris_adc_init
);
1455 ssi_register_slave(&stellaris_ssi_bus_info
);
1458 device_init(stellaris_register_devices
)