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vmstate, memory: decouple vmstate from memory API
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(CPUState *env)
257 {
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276 }
277
278 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279 {
280 }
281
282 static void main_cpu_reset(void *opaque)
283 {
284 CPUState *env = opaque;
285
286 cpu_reset(env);
287 env->halted = 0;
288 }
289
290 static void secondary_cpu_reset(void *opaque)
291 {
292 CPUState *env = opaque;
293
294 cpu_reset(env);
295 env->halted = 1;
296 }
297
298 static void cpu_halt_signal(void *opaque, int irq, int level)
299 {
300 if (level && cpu_single_env)
301 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302 }
303
304 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305 {
306 return addr - 0xf0000000ULL;
307 }
308
309 static unsigned long sun4m_load_kernel(const char *kernel_filename,
310 const char *initrd_filename,
311 ram_addr_t RAM_size)
312 {
313 int linux_boot;
314 unsigned int i;
315 long initrd_size, kernel_size;
316 uint8_t *ptr;
317
318 linux_boot = (kernel_filename != NULL);
319
320 kernel_size = 0;
321 if (linux_boot) {
322 int bswap_needed;
323
324 #ifdef BSWAP_NEEDED
325 bswap_needed = 1;
326 #else
327 bswap_needed = 0;
328 #endif
329 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
331 if (kernel_size < 0)
332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
333 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334 TARGET_PAGE_SIZE);
335 if (kernel_size < 0)
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
359 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360 if (ldl_p(ptr) == 0x48647253) { // HdrS
361 stl_p(ptr + 16, INITRD_LOAD_ADDR);
362 stl_p(ptr + 20, initrd_size);
363 break;
364 }
365 }
366 }
367 }
368 return kernel_size;
369 }
370
371 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
372 {
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 dev = qdev_create(NULL, "iommu");
377 qdev_prop_set_uint32(dev, "version", version);
378 qdev_init_nofail(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_connect_irq(s, 0, irq);
381 sysbus_mmio_map(s, 0, addr);
382
383 return s;
384 }
385
386 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
387 void *iommu, qemu_irq *dev_irq, int is_ledma)
388 {
389 DeviceState *dev;
390 SysBusDevice *s;
391
392 dev = qdev_create(NULL, "sparc32_dma");
393 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
394 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
395 qdev_init_nofail(dev);
396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402 }
403
404 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
405 void *dma_opaque, qemu_irq irq)
406 {
407 DeviceState *dev;
408 SysBusDevice *s;
409 qemu_irq reset;
410
411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
414 qdev_set_nic_properties(dev, nd);
415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
416 qdev_init_nofail(dev);
417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
422 }
423
424 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
426 qemu_irq **parent_irq)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
433 qdev_init_nofail(dev);
434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448 }
449
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
453 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462 qdev_init_nofail(dev);
463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471 }
472
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
478
479 static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
482 qemu_irq fdc_tc)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
488 qdev_init_nofail(dev);
489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516 }
517
518 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519 {
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532 }
533
534 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
540 qdev_init_nofail(dev);
541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545 }
546
547 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548 int height, int depth)
549 {
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
559 qdev_init_nofail(dev);
560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578 }
579
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
583 static void idreg_init(target_phys_addr_t addr)
584 {
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
589 qdev_init_nofail(dev);
590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594 }
595
596 typedef struct IDRegState {
597 SysBusDevice busdev;
598 MemoryRegion mem;
599 } IDRegState;
600
601 static int idreg_init1(SysBusDevice *dev)
602 {
603 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
604
605 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
606 vmstate_register_ram_global(&s->mem);
607 memory_region_set_readonly(&s->mem, true);
608 sysbus_init_mmio(dev, &s->mem);
609 return 0;
610 }
611
612 static SysBusDeviceInfo idreg_info = {
613 .init = idreg_init1,
614 .qdev.name = "macio_idreg",
615 .qdev.size = sizeof(IDRegState),
616 };
617
618 static void idreg_register_devices(void)
619 {
620 sysbus_register_withprop(&idreg_info);
621 }
622
623 device_init(idreg_register_devices);
624
625 typedef struct AFXState {
626 SysBusDevice busdev;
627 MemoryRegion mem;
628 } AFXState;
629
630 /* SS-5 TCX AFX register */
631 static void afx_init(target_phys_addr_t addr)
632 {
633 DeviceState *dev;
634 SysBusDevice *s;
635
636 dev = qdev_create(NULL, "tcx_afx");
637 qdev_init_nofail(dev);
638 s = sysbus_from_qdev(dev);
639
640 sysbus_mmio_map(s, 0, addr);
641 }
642
643 static int afx_init1(SysBusDevice *dev)
644 {
645 AFXState *s = FROM_SYSBUS(AFXState, dev);
646
647 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
648 vmstate_register_ram_global(&s->mem);
649 sysbus_init_mmio(dev, &s->mem);
650 return 0;
651 }
652
653 static SysBusDeviceInfo afx_info = {
654 .init = afx_init1,
655 .qdev.name = "tcx_afx",
656 .qdev.size = sizeof(AFXState),
657 };
658
659 static void afx_register_devices(void)
660 {
661 sysbus_register_withprop(&afx_info);
662 }
663
664 device_init(afx_register_devices);
665
666 typedef struct PROMState {
667 SysBusDevice busdev;
668 MemoryRegion prom;
669 } PROMState;
670
671 /* Boot PROM (OpenBIOS) */
672 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
673 {
674 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
675 return addr + *base_addr - PROM_VADDR;
676 }
677
678 static void prom_init(target_phys_addr_t addr, const char *bios_name)
679 {
680 DeviceState *dev;
681 SysBusDevice *s;
682 char *filename;
683 int ret;
684
685 dev = qdev_create(NULL, "openprom");
686 qdev_init_nofail(dev);
687 s = sysbus_from_qdev(dev);
688
689 sysbus_mmio_map(s, 0, addr);
690
691 /* load boot prom */
692 if (bios_name == NULL) {
693 bios_name = PROM_FILENAME;
694 }
695 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
696 if (filename) {
697 ret = load_elf(filename, translate_prom_address, &addr, NULL,
698 NULL, NULL, 1, ELF_MACHINE, 0);
699 if (ret < 0 || ret > PROM_SIZE_MAX) {
700 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
701 }
702 g_free(filename);
703 } else {
704 ret = -1;
705 }
706 if (ret < 0 || ret > PROM_SIZE_MAX) {
707 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
708 exit(1);
709 }
710 }
711
712 static int prom_init1(SysBusDevice *dev)
713 {
714 PROMState *s = FROM_SYSBUS(PROMState, dev);
715
716 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
717 vmstate_register_ram_global(&s->prom);
718 memory_region_set_readonly(&s->prom, true);
719 sysbus_init_mmio(dev, &s->prom);
720 return 0;
721 }
722
723 static SysBusDeviceInfo prom_info = {
724 .init = prom_init1,
725 .qdev.name = "openprom",
726 .qdev.size = sizeof(PROMState),
727 .qdev.props = (Property[]) {
728 {/* end of property list */}
729 }
730 };
731
732 static void prom_register_devices(void)
733 {
734 sysbus_register_withprop(&prom_info);
735 }
736
737 device_init(prom_register_devices);
738
739 typedef struct RamDevice
740 {
741 SysBusDevice busdev;
742 MemoryRegion ram;
743 uint64_t size;
744 } RamDevice;
745
746 /* System RAM */
747 static int ram_init1(SysBusDevice *dev)
748 {
749 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
750
751 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
752 vmstate_register_ram_global(&d->ram);
753 sysbus_init_mmio(dev, &d->ram);
754 return 0;
755 }
756
757 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
758 uint64_t max_mem)
759 {
760 DeviceState *dev;
761 SysBusDevice *s;
762 RamDevice *d;
763
764 /* allocate RAM */
765 if ((uint64_t)RAM_size > max_mem) {
766 fprintf(stderr,
767 "qemu: Too much memory for this machine: %d, maximum %d\n",
768 (unsigned int)(RAM_size / (1024 * 1024)),
769 (unsigned int)(max_mem / (1024 * 1024)));
770 exit(1);
771 }
772 dev = qdev_create(NULL, "memory");
773 s = sysbus_from_qdev(dev);
774
775 d = FROM_SYSBUS(RamDevice, s);
776 d->size = RAM_size;
777 qdev_init_nofail(dev);
778
779 sysbus_mmio_map(s, 0, addr);
780 }
781
782 static SysBusDeviceInfo ram_info = {
783 .init = ram_init1,
784 .qdev.name = "memory",
785 .qdev.size = sizeof(RamDevice),
786 .qdev.props = (Property[]) {
787 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
788 DEFINE_PROP_END_OF_LIST(),
789 }
790 };
791
792 static void ram_register_devices(void)
793 {
794 sysbus_register_withprop(&ram_info);
795 }
796
797 device_init(ram_register_devices);
798
799 static void cpu_devinit(const char *cpu_model, unsigned int id,
800 uint64_t prom_addr, qemu_irq **cpu_irqs)
801 {
802 CPUState *env;
803
804 env = cpu_init(cpu_model);
805 if (!env) {
806 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
807 exit(1);
808 }
809
810 cpu_sparc_set_id(env, id);
811 if (id == 0) {
812 qemu_register_reset(main_cpu_reset, env);
813 } else {
814 qemu_register_reset(secondary_cpu_reset, env);
815 env->halted = 1;
816 }
817 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
818 env->prom_addr = prom_addr;
819 }
820
821 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
822 const char *boot_device,
823 const char *kernel_filename,
824 const char *kernel_cmdline,
825 const char *initrd_filename, const char *cpu_model)
826 {
827 unsigned int i;
828 void *iommu, *espdma, *ledma, *nvram;
829 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
830 espdma_irq, ledma_irq;
831 qemu_irq esp_reset, dma_enable;
832 qemu_irq fdc_tc;
833 qemu_irq *cpu_halt;
834 unsigned long kernel_size;
835 DriveInfo *fd[MAX_FD];
836 void *fw_cfg;
837 unsigned int num_vsimms;
838
839 /* init CPUs */
840 if (!cpu_model)
841 cpu_model = hwdef->default_cpu_model;
842
843 for(i = 0; i < smp_cpus; i++) {
844 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
845 }
846
847 for (i = smp_cpus; i < MAX_CPUS; i++)
848 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
849
850
851 /* set up devices */
852 ram_init(0, RAM_size, hwdef->max_mem);
853 /* models without ECC don't trap when missing ram is accessed */
854 if (!hwdef->ecc_base) {
855 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
856 }
857
858 prom_init(hwdef->slavio_base, bios_name);
859
860 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
861 hwdef->intctl_base + 0x10000ULL,
862 cpu_irqs);
863
864 for (i = 0; i < 32; i++) {
865 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
866 }
867 for (i = 0; i < MAX_CPUS; i++) {
868 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
869 }
870
871 if (hwdef->idreg_base) {
872 idreg_init(hwdef->idreg_base);
873 }
874
875 if (hwdef->afx_base) {
876 afx_init(hwdef->afx_base);
877 }
878
879 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
880 slavio_irq[30]);
881
882 if (hwdef->iommu_pad_base) {
883 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
884 Software shouldn't use aliased addresses, neither should it crash
885 when does. Using empty_slot instead of aliasing can help with
886 debugging such accesses */
887 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
888 }
889
890 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
891 iommu, &espdma_irq, 0);
892
893 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
894 slavio_irq[16], iommu, &ledma_irq, 1);
895
896 if (graphic_depth != 8 && graphic_depth != 24) {
897 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
898 exit (1);
899 }
900 num_vsimms = 0;
901 if (num_vsimms == 0) {
902 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
903 graphic_depth);
904 }
905
906 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
907 /* vsimm registers probed by OBP */
908 if (hwdef->vsimm[i].reg_base) {
909 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
910 }
911 }
912
913 if (hwdef->sx_base) {
914 empty_slot_init(hwdef->sx_base, 0x2000);
915 }
916
917 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
918
919 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
920
921 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
922
923 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
924 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
925 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
926 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
927 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
928 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
929
930 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
931 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
932 slavio_irq[30], fdc_tc);
933
934 if (hwdef->apc_base) {
935 apc_init(hwdef->apc_base, cpu_halt[0]);
936 }
937
938 if (hwdef->fd_base) {
939 /* there is zero or one floppy drive */
940 memset(fd, 0, sizeof(fd));
941 fd[0] = drive_get(IF_FLOPPY, 0, 0);
942 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
943 &fdc_tc);
944 }
945
946 if (drive_get_max_bus(IF_SCSI) > 0) {
947 fprintf(stderr, "qemu: too many SCSI bus\n");
948 exit(1);
949 }
950
951 esp_init(hwdef->esp_base, 2,
952 espdma_memory_read, espdma_memory_write,
953 espdma, espdma_irq, &esp_reset, &dma_enable);
954
955 qdev_connect_gpio_out(espdma, 0, esp_reset);
956 qdev_connect_gpio_out(espdma, 1, dma_enable);
957
958 if (hwdef->cs_base) {
959 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
960 slavio_irq[5]);
961 }
962
963 if (hwdef->dbri_base) {
964 /* ISDN chip with attached CS4215 audio codec */
965 /* prom space */
966 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
967 /* reg space */
968 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
969 }
970
971 if (hwdef->bpp_base) {
972 /* parallel port */
973 empty_slot_init(hwdef->bpp_base, 0x20);
974 }
975
976 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
977 RAM_size);
978
979 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
980 boot_device, RAM_size, kernel_size, graphic_width,
981 graphic_height, graphic_depth, hwdef->nvram_machine_id,
982 "Sun4m");
983
984 if (hwdef->ecc_base)
985 ecc_init(hwdef->ecc_base, slavio_irq[28],
986 hwdef->ecc_version);
987
988 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
989 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
990 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
991 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
992 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
993 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
994 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
995 if (kernel_cmdline) {
996 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
997 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
998 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
999 (uint8_t*)strdup(kernel_cmdline),
1000 strlen(kernel_cmdline) + 1);
1001 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1002 strlen(kernel_cmdline) + 1);
1003 } else {
1004 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1005 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1006 }
1007 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1008 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1009 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1010 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1011 }
1012
1013 enum {
1014 ss2_id = 0,
1015 ss5_id = 32,
1016 vger_id,
1017 lx_id,
1018 ss4_id,
1019 scls_id,
1020 sbook_id,
1021 ss10_id = 64,
1022 ss20_id,
1023 ss600mp_id,
1024 ss1000_id = 96,
1025 ss2000_id,
1026 };
1027
1028 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1029 /* SS-5 */
1030 {
1031 .iommu_base = 0x10000000,
1032 .iommu_pad_base = 0x10004000,
1033 .iommu_pad_len = 0x0fffb000,
1034 .tcx_base = 0x50000000,
1035 .cs_base = 0x6c000000,
1036 .slavio_base = 0x70000000,
1037 .ms_kb_base = 0x71000000,
1038 .serial_base = 0x71100000,
1039 .nvram_base = 0x71200000,
1040 .fd_base = 0x71400000,
1041 .counter_base = 0x71d00000,
1042 .intctl_base = 0x71e00000,
1043 .idreg_base = 0x78000000,
1044 .dma_base = 0x78400000,
1045 .esp_base = 0x78800000,
1046 .le_base = 0x78c00000,
1047 .apc_base = 0x6a000000,
1048 .afx_base = 0x6e000000,
1049 .aux1_base = 0x71900000,
1050 .aux2_base = 0x71910000,
1051 .nvram_machine_id = 0x80,
1052 .machine_id = ss5_id,
1053 .iommu_version = 0x05000000,
1054 .max_mem = 0x10000000,
1055 .default_cpu_model = "Fujitsu MB86904",
1056 },
1057 /* SS-10 */
1058 {
1059 .iommu_base = 0xfe0000000ULL,
1060 .tcx_base = 0xe20000000ULL,
1061 .slavio_base = 0xff0000000ULL,
1062 .ms_kb_base = 0xff1000000ULL,
1063 .serial_base = 0xff1100000ULL,
1064 .nvram_base = 0xff1200000ULL,
1065 .fd_base = 0xff1700000ULL,
1066 .counter_base = 0xff1300000ULL,
1067 .intctl_base = 0xff1400000ULL,
1068 .idreg_base = 0xef0000000ULL,
1069 .dma_base = 0xef0400000ULL,
1070 .esp_base = 0xef0800000ULL,
1071 .le_base = 0xef0c00000ULL,
1072 .apc_base = 0xefa000000ULL, // XXX should not exist
1073 .aux1_base = 0xff1800000ULL,
1074 .aux2_base = 0xff1a01000ULL,
1075 .ecc_base = 0xf00000000ULL,
1076 .ecc_version = 0x10000000, // version 0, implementation 1
1077 .nvram_machine_id = 0x72,
1078 .machine_id = ss10_id,
1079 .iommu_version = 0x03000000,
1080 .max_mem = 0xf00000000ULL,
1081 .default_cpu_model = "TI SuperSparc II",
1082 },
1083 /* SS-600MP */
1084 {
1085 .iommu_base = 0xfe0000000ULL,
1086 .tcx_base = 0xe20000000ULL,
1087 .slavio_base = 0xff0000000ULL,
1088 .ms_kb_base = 0xff1000000ULL,
1089 .serial_base = 0xff1100000ULL,
1090 .nvram_base = 0xff1200000ULL,
1091 .counter_base = 0xff1300000ULL,
1092 .intctl_base = 0xff1400000ULL,
1093 .dma_base = 0xef0081000ULL,
1094 .esp_base = 0xef0080000ULL,
1095 .le_base = 0xef0060000ULL,
1096 .apc_base = 0xefa000000ULL, // XXX should not exist
1097 .aux1_base = 0xff1800000ULL,
1098 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1099 .ecc_base = 0xf00000000ULL,
1100 .ecc_version = 0x00000000, // version 0, implementation 0
1101 .nvram_machine_id = 0x71,
1102 .machine_id = ss600mp_id,
1103 .iommu_version = 0x01000000,
1104 .max_mem = 0xf00000000ULL,
1105 .default_cpu_model = "TI SuperSparc II",
1106 },
1107 /* SS-20 */
1108 {
1109 .iommu_base = 0xfe0000000ULL,
1110 .tcx_base = 0xe20000000ULL,
1111 .slavio_base = 0xff0000000ULL,
1112 .ms_kb_base = 0xff1000000ULL,
1113 .serial_base = 0xff1100000ULL,
1114 .nvram_base = 0xff1200000ULL,
1115 .fd_base = 0xff1700000ULL,
1116 .counter_base = 0xff1300000ULL,
1117 .intctl_base = 0xff1400000ULL,
1118 .idreg_base = 0xef0000000ULL,
1119 .dma_base = 0xef0400000ULL,
1120 .esp_base = 0xef0800000ULL,
1121 .le_base = 0xef0c00000ULL,
1122 .bpp_base = 0xef4800000ULL,
1123 .apc_base = 0xefa000000ULL, // XXX should not exist
1124 .aux1_base = 0xff1800000ULL,
1125 .aux2_base = 0xff1a01000ULL,
1126 .dbri_base = 0xee0000000ULL,
1127 .sx_base = 0xf80000000ULL,
1128 .vsimm = {
1129 {
1130 .reg_base = 0x9c000000ULL,
1131 .vram_base = 0xfc000000ULL
1132 }, {
1133 .reg_base = 0x90000000ULL,
1134 .vram_base = 0xf0000000ULL
1135 }, {
1136 .reg_base = 0x94000000ULL
1137 }, {
1138 .reg_base = 0x98000000ULL
1139 }
1140 },
1141 .ecc_base = 0xf00000000ULL,
1142 .ecc_version = 0x20000000, // version 0, implementation 2
1143 .nvram_machine_id = 0x72,
1144 .machine_id = ss20_id,
1145 .iommu_version = 0x13000000,
1146 .max_mem = 0xf00000000ULL,
1147 .default_cpu_model = "TI SuperSparc II",
1148 },
1149 /* Voyager */
1150 {
1151 .iommu_base = 0x10000000,
1152 .tcx_base = 0x50000000,
1153 .slavio_base = 0x70000000,
1154 .ms_kb_base = 0x71000000,
1155 .serial_base = 0x71100000,
1156 .nvram_base = 0x71200000,
1157 .fd_base = 0x71400000,
1158 .counter_base = 0x71d00000,
1159 .intctl_base = 0x71e00000,
1160 .idreg_base = 0x78000000,
1161 .dma_base = 0x78400000,
1162 .esp_base = 0x78800000,
1163 .le_base = 0x78c00000,
1164 .apc_base = 0x71300000, // pmc
1165 .aux1_base = 0x71900000,
1166 .aux2_base = 0x71910000,
1167 .nvram_machine_id = 0x80,
1168 .machine_id = vger_id,
1169 .iommu_version = 0x05000000,
1170 .max_mem = 0x10000000,
1171 .default_cpu_model = "Fujitsu MB86904",
1172 },
1173 /* LX */
1174 {
1175 .iommu_base = 0x10000000,
1176 .iommu_pad_base = 0x10004000,
1177 .iommu_pad_len = 0x0fffb000,
1178 .tcx_base = 0x50000000,
1179 .slavio_base = 0x70000000,
1180 .ms_kb_base = 0x71000000,
1181 .serial_base = 0x71100000,
1182 .nvram_base = 0x71200000,
1183 .fd_base = 0x71400000,
1184 .counter_base = 0x71d00000,
1185 .intctl_base = 0x71e00000,
1186 .idreg_base = 0x78000000,
1187 .dma_base = 0x78400000,
1188 .esp_base = 0x78800000,
1189 .le_base = 0x78c00000,
1190 .aux1_base = 0x71900000,
1191 .aux2_base = 0x71910000,
1192 .nvram_machine_id = 0x80,
1193 .machine_id = lx_id,
1194 .iommu_version = 0x04000000,
1195 .max_mem = 0x10000000,
1196 .default_cpu_model = "TI MicroSparc I",
1197 },
1198 /* SS-4 */
1199 {
1200 .iommu_base = 0x10000000,
1201 .tcx_base = 0x50000000,
1202 .cs_base = 0x6c000000,
1203 .slavio_base = 0x70000000,
1204 .ms_kb_base = 0x71000000,
1205 .serial_base = 0x71100000,
1206 .nvram_base = 0x71200000,
1207 .fd_base = 0x71400000,
1208 .counter_base = 0x71d00000,
1209 .intctl_base = 0x71e00000,
1210 .idreg_base = 0x78000000,
1211 .dma_base = 0x78400000,
1212 .esp_base = 0x78800000,
1213 .le_base = 0x78c00000,
1214 .apc_base = 0x6a000000,
1215 .aux1_base = 0x71900000,
1216 .aux2_base = 0x71910000,
1217 .nvram_machine_id = 0x80,
1218 .machine_id = ss4_id,
1219 .iommu_version = 0x05000000,
1220 .max_mem = 0x10000000,
1221 .default_cpu_model = "Fujitsu MB86904",
1222 },
1223 /* SPARCClassic */
1224 {
1225 .iommu_base = 0x10000000,
1226 .tcx_base = 0x50000000,
1227 .slavio_base = 0x70000000,
1228 .ms_kb_base = 0x71000000,
1229 .serial_base = 0x71100000,
1230 .nvram_base = 0x71200000,
1231 .fd_base = 0x71400000,
1232 .counter_base = 0x71d00000,
1233 .intctl_base = 0x71e00000,
1234 .idreg_base = 0x78000000,
1235 .dma_base = 0x78400000,
1236 .esp_base = 0x78800000,
1237 .le_base = 0x78c00000,
1238 .apc_base = 0x6a000000,
1239 .aux1_base = 0x71900000,
1240 .aux2_base = 0x71910000,
1241 .nvram_machine_id = 0x80,
1242 .machine_id = scls_id,
1243 .iommu_version = 0x05000000,
1244 .max_mem = 0x10000000,
1245 .default_cpu_model = "TI MicroSparc I",
1246 },
1247 /* SPARCbook */
1248 {
1249 .iommu_base = 0x10000000,
1250 .tcx_base = 0x50000000, // XXX
1251 .slavio_base = 0x70000000,
1252 .ms_kb_base = 0x71000000,
1253 .serial_base = 0x71100000,
1254 .nvram_base = 0x71200000,
1255 .fd_base = 0x71400000,
1256 .counter_base = 0x71d00000,
1257 .intctl_base = 0x71e00000,
1258 .idreg_base = 0x78000000,
1259 .dma_base = 0x78400000,
1260 .esp_base = 0x78800000,
1261 .le_base = 0x78c00000,
1262 .apc_base = 0x6a000000,
1263 .aux1_base = 0x71900000,
1264 .aux2_base = 0x71910000,
1265 .nvram_machine_id = 0x80,
1266 .machine_id = sbook_id,
1267 .iommu_version = 0x05000000,
1268 .max_mem = 0x10000000,
1269 .default_cpu_model = "TI MicroSparc I",
1270 },
1271 };
1272
1273 /* SPARCstation 5 hardware initialisation */
1274 static void ss5_init(ram_addr_t RAM_size,
1275 const char *boot_device,
1276 const char *kernel_filename, const char *kernel_cmdline,
1277 const char *initrd_filename, const char *cpu_model)
1278 {
1279 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1280 kernel_cmdline, initrd_filename, cpu_model);
1281 }
1282
1283 /* SPARCstation 10 hardware initialisation */
1284 static void ss10_init(ram_addr_t RAM_size,
1285 const char *boot_device,
1286 const char *kernel_filename, const char *kernel_cmdline,
1287 const char *initrd_filename, const char *cpu_model)
1288 {
1289 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1290 kernel_cmdline, initrd_filename, cpu_model);
1291 }
1292
1293 /* SPARCserver 600MP hardware initialisation */
1294 static void ss600mp_init(ram_addr_t RAM_size,
1295 const char *boot_device,
1296 const char *kernel_filename,
1297 const char *kernel_cmdline,
1298 const char *initrd_filename, const char *cpu_model)
1299 {
1300 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1301 kernel_cmdline, initrd_filename, cpu_model);
1302 }
1303
1304 /* SPARCstation 20 hardware initialisation */
1305 static void ss20_init(ram_addr_t RAM_size,
1306 const char *boot_device,
1307 const char *kernel_filename, const char *kernel_cmdline,
1308 const char *initrd_filename, const char *cpu_model)
1309 {
1310 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1311 kernel_cmdline, initrd_filename, cpu_model);
1312 }
1313
1314 /* SPARCstation Voyager hardware initialisation */
1315 static void vger_init(ram_addr_t RAM_size,
1316 const char *boot_device,
1317 const char *kernel_filename, const char *kernel_cmdline,
1318 const char *initrd_filename, const char *cpu_model)
1319 {
1320 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1321 kernel_cmdline, initrd_filename, cpu_model);
1322 }
1323
1324 /* SPARCstation LX hardware initialisation */
1325 static void ss_lx_init(ram_addr_t RAM_size,
1326 const char *boot_device,
1327 const char *kernel_filename, const char *kernel_cmdline,
1328 const char *initrd_filename, const char *cpu_model)
1329 {
1330 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1331 kernel_cmdline, initrd_filename, cpu_model);
1332 }
1333
1334 /* SPARCstation 4 hardware initialisation */
1335 static void ss4_init(ram_addr_t RAM_size,
1336 const char *boot_device,
1337 const char *kernel_filename, const char *kernel_cmdline,
1338 const char *initrd_filename, const char *cpu_model)
1339 {
1340 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1341 kernel_cmdline, initrd_filename, cpu_model);
1342 }
1343
1344 /* SPARCClassic hardware initialisation */
1345 static void scls_init(ram_addr_t RAM_size,
1346 const char *boot_device,
1347 const char *kernel_filename, const char *kernel_cmdline,
1348 const char *initrd_filename, const char *cpu_model)
1349 {
1350 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1351 kernel_cmdline, initrd_filename, cpu_model);
1352 }
1353
1354 /* SPARCbook hardware initialisation */
1355 static void sbook_init(ram_addr_t RAM_size,
1356 const char *boot_device,
1357 const char *kernel_filename, const char *kernel_cmdline,
1358 const char *initrd_filename, const char *cpu_model)
1359 {
1360 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1361 kernel_cmdline, initrd_filename, cpu_model);
1362 }
1363
1364 static QEMUMachine ss5_machine = {
1365 .name = "SS-5",
1366 .desc = "Sun4m platform, SPARCstation 5",
1367 .init = ss5_init,
1368 .use_scsi = 1,
1369 .is_default = 1,
1370 };
1371
1372 static QEMUMachine ss10_machine = {
1373 .name = "SS-10",
1374 .desc = "Sun4m platform, SPARCstation 10",
1375 .init = ss10_init,
1376 .use_scsi = 1,
1377 .max_cpus = 4,
1378 };
1379
1380 static QEMUMachine ss600mp_machine = {
1381 .name = "SS-600MP",
1382 .desc = "Sun4m platform, SPARCserver 600MP",
1383 .init = ss600mp_init,
1384 .use_scsi = 1,
1385 .max_cpus = 4,
1386 };
1387
1388 static QEMUMachine ss20_machine = {
1389 .name = "SS-20",
1390 .desc = "Sun4m platform, SPARCstation 20",
1391 .init = ss20_init,
1392 .use_scsi = 1,
1393 .max_cpus = 4,
1394 };
1395
1396 static QEMUMachine voyager_machine = {
1397 .name = "Voyager",
1398 .desc = "Sun4m platform, SPARCstation Voyager",
1399 .init = vger_init,
1400 .use_scsi = 1,
1401 };
1402
1403 static QEMUMachine ss_lx_machine = {
1404 .name = "LX",
1405 .desc = "Sun4m platform, SPARCstation LX",
1406 .init = ss_lx_init,
1407 .use_scsi = 1,
1408 };
1409
1410 static QEMUMachine ss4_machine = {
1411 .name = "SS-4",
1412 .desc = "Sun4m platform, SPARCstation 4",
1413 .init = ss4_init,
1414 .use_scsi = 1,
1415 };
1416
1417 static QEMUMachine scls_machine = {
1418 .name = "SPARCClassic",
1419 .desc = "Sun4m platform, SPARCClassic",
1420 .init = scls_init,
1421 .use_scsi = 1,
1422 };
1423
1424 static QEMUMachine sbook_machine = {
1425 .name = "SPARCbook",
1426 .desc = "Sun4m platform, SPARCbook",
1427 .init = sbook_init,
1428 .use_scsi = 1,
1429 };
1430
1431 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1432 /* SS-1000 */
1433 {
1434 .iounit_bases = {
1435 0xfe0200000ULL,
1436 0xfe1200000ULL,
1437 0xfe2200000ULL,
1438 0xfe3200000ULL,
1439 -1,
1440 },
1441 .tcx_base = 0x820000000ULL,
1442 .slavio_base = 0xf00000000ULL,
1443 .ms_kb_base = 0xf00240000ULL,
1444 .serial_base = 0xf00200000ULL,
1445 .nvram_base = 0xf00280000ULL,
1446 .counter_base = 0xf00300000ULL,
1447 .espdma_base = 0x800081000ULL,
1448 .esp_base = 0x800080000ULL,
1449 .ledma_base = 0x800040000ULL,
1450 .le_base = 0x800060000ULL,
1451 .sbi_base = 0xf02800000ULL,
1452 .nvram_machine_id = 0x80,
1453 .machine_id = ss1000_id,
1454 .iounit_version = 0x03000000,
1455 .max_mem = 0xf00000000ULL,
1456 .default_cpu_model = "TI SuperSparc II",
1457 },
1458 /* SS-2000 */
1459 {
1460 .iounit_bases = {
1461 0xfe0200000ULL,
1462 0xfe1200000ULL,
1463 0xfe2200000ULL,
1464 0xfe3200000ULL,
1465 0xfe4200000ULL,
1466 },
1467 .tcx_base = 0x820000000ULL,
1468 .slavio_base = 0xf00000000ULL,
1469 .ms_kb_base = 0xf00240000ULL,
1470 .serial_base = 0xf00200000ULL,
1471 .nvram_base = 0xf00280000ULL,
1472 .counter_base = 0xf00300000ULL,
1473 .espdma_base = 0x800081000ULL,
1474 .esp_base = 0x800080000ULL,
1475 .ledma_base = 0x800040000ULL,
1476 .le_base = 0x800060000ULL,
1477 .sbi_base = 0xf02800000ULL,
1478 .nvram_machine_id = 0x80,
1479 .machine_id = ss2000_id,
1480 .iounit_version = 0x03000000,
1481 .max_mem = 0xf00000000ULL,
1482 .default_cpu_model = "TI SuperSparc II",
1483 },
1484 };
1485
1486 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1487 {
1488 DeviceState *dev;
1489 SysBusDevice *s;
1490 unsigned int i;
1491
1492 dev = qdev_create(NULL, "sbi");
1493 qdev_init_nofail(dev);
1494
1495 s = sysbus_from_qdev(dev);
1496
1497 for (i = 0; i < MAX_CPUS; i++) {
1498 sysbus_connect_irq(s, i, *parent_irq[i]);
1499 }
1500
1501 sysbus_mmio_map(s, 0, addr);
1502
1503 return dev;
1504 }
1505
1506 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1507 const char *boot_device,
1508 const char *kernel_filename,
1509 const char *kernel_cmdline,
1510 const char *initrd_filename, const char *cpu_model)
1511 {
1512 unsigned int i;
1513 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1514 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1515 espdma_irq, ledma_irq;
1516 qemu_irq esp_reset, dma_enable;
1517 unsigned long kernel_size;
1518 void *fw_cfg;
1519 DeviceState *dev;
1520
1521 /* init CPUs */
1522 if (!cpu_model)
1523 cpu_model = hwdef->default_cpu_model;
1524
1525 for(i = 0; i < smp_cpus; i++) {
1526 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1527 }
1528
1529 for (i = smp_cpus; i < MAX_CPUS; i++)
1530 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1531
1532 /* set up devices */
1533 ram_init(0, RAM_size, hwdef->max_mem);
1534
1535 prom_init(hwdef->slavio_base, bios_name);
1536
1537 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1538
1539 for (i = 0; i < 32; i++) {
1540 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1541 }
1542 for (i = 0; i < MAX_CPUS; i++) {
1543 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1544 }
1545
1546 for (i = 0; i < MAX_IOUNITS; i++)
1547 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1548 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1549 hwdef->iounit_version,
1550 sbi_irq[0]);
1551
1552 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1553 iounits[0], &espdma_irq, 0);
1554
1555 /* should be lebuffer instead */
1556 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1557 iounits[0], &ledma_irq, 0);
1558
1559 if (graphic_depth != 8 && graphic_depth != 24) {
1560 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1561 exit (1);
1562 }
1563 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1564 graphic_depth);
1565
1566 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1567
1568 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1569
1570 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1571
1572 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1573 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1574 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1575 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1576 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1577 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1578
1579 if (drive_get_max_bus(IF_SCSI) > 0) {
1580 fprintf(stderr, "qemu: too many SCSI bus\n");
1581 exit(1);
1582 }
1583
1584 esp_init(hwdef->esp_base, 2,
1585 espdma_memory_read, espdma_memory_write,
1586 espdma, espdma_irq, &esp_reset, &dma_enable);
1587
1588 qdev_connect_gpio_out(espdma, 0, esp_reset);
1589 qdev_connect_gpio_out(espdma, 1, dma_enable);
1590
1591 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1592 RAM_size);
1593
1594 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1595 boot_device, RAM_size, kernel_size, graphic_width,
1596 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1597 "Sun4d");
1598
1599 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1600 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1601 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1602 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1603 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1604 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1605 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1606 if (kernel_cmdline) {
1607 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1608 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1609 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1610 (uint8_t*)strdup(kernel_cmdline),
1611 strlen(kernel_cmdline) + 1);
1612 } else {
1613 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1614 }
1615 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1616 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1617 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1618 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1619 }
1620
1621 /* SPARCserver 1000 hardware initialisation */
1622 static void ss1000_init(ram_addr_t RAM_size,
1623 const char *boot_device,
1624 const char *kernel_filename, const char *kernel_cmdline,
1625 const char *initrd_filename, const char *cpu_model)
1626 {
1627 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1628 kernel_cmdline, initrd_filename, cpu_model);
1629 }
1630
1631 /* SPARCcenter 2000 hardware initialisation */
1632 static void ss2000_init(ram_addr_t RAM_size,
1633 const char *boot_device,
1634 const char *kernel_filename, const char *kernel_cmdline,
1635 const char *initrd_filename, const char *cpu_model)
1636 {
1637 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1638 kernel_cmdline, initrd_filename, cpu_model);
1639 }
1640
1641 static QEMUMachine ss1000_machine = {
1642 .name = "SS-1000",
1643 .desc = "Sun4d platform, SPARCserver 1000",
1644 .init = ss1000_init,
1645 .use_scsi = 1,
1646 .max_cpus = 8,
1647 };
1648
1649 static QEMUMachine ss2000_machine = {
1650 .name = "SS-2000",
1651 .desc = "Sun4d platform, SPARCcenter 2000",
1652 .init = ss2000_init,
1653 .use_scsi = 1,
1654 .max_cpus = 20,
1655 };
1656
1657 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1658 /* SS-2 */
1659 {
1660 .iommu_base = 0xf8000000,
1661 .tcx_base = 0xfe000000,
1662 .slavio_base = 0xf6000000,
1663 .intctl_base = 0xf5000000,
1664 .counter_base = 0xf3000000,
1665 .ms_kb_base = 0xf0000000,
1666 .serial_base = 0xf1000000,
1667 .nvram_base = 0xf2000000,
1668 .fd_base = 0xf7200000,
1669 .dma_base = 0xf8400000,
1670 .esp_base = 0xf8800000,
1671 .le_base = 0xf8c00000,
1672 .aux1_base = 0xf7400003,
1673 .nvram_machine_id = 0x55,
1674 .machine_id = ss2_id,
1675 .max_mem = 0x10000000,
1676 .default_cpu_model = "Cypress CY7C601",
1677 },
1678 };
1679
1680 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1681 qemu_irq *parent_irq)
1682 {
1683 DeviceState *dev;
1684 SysBusDevice *s;
1685 unsigned int i;
1686
1687 dev = qdev_create(NULL, "sun4c_intctl");
1688 qdev_init_nofail(dev);
1689
1690 s = sysbus_from_qdev(dev);
1691
1692 for (i = 0; i < MAX_PILS; i++) {
1693 sysbus_connect_irq(s, i, parent_irq[i]);
1694 }
1695 sysbus_mmio_map(s, 0, addr);
1696
1697 return dev;
1698 }
1699
1700 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1701 const char *boot_device,
1702 const char *kernel_filename,
1703 const char *kernel_cmdline,
1704 const char *initrd_filename, const char *cpu_model)
1705 {
1706 void *iommu, *espdma, *ledma, *nvram;
1707 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1708 qemu_irq esp_reset, dma_enable;
1709 qemu_irq fdc_tc;
1710 unsigned long kernel_size;
1711 DriveInfo *fd[MAX_FD];
1712 void *fw_cfg;
1713 DeviceState *dev;
1714 unsigned int i;
1715
1716 /* init CPU */
1717 if (!cpu_model)
1718 cpu_model = hwdef->default_cpu_model;
1719
1720 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1721
1722 /* set up devices */
1723 ram_init(0, RAM_size, hwdef->max_mem);
1724
1725 prom_init(hwdef->slavio_base, bios_name);
1726
1727 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1728
1729 for (i = 0; i < 8; i++) {
1730 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1731 }
1732
1733 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1734 slavio_irq[1]);
1735
1736 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1737 iommu, &espdma_irq, 0);
1738
1739 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1740 slavio_irq[3], iommu, &ledma_irq, 1);
1741
1742 if (graphic_depth != 8 && graphic_depth != 24) {
1743 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1744 exit (1);
1745 }
1746 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1747 graphic_depth);
1748
1749 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1750
1751 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1752
1753 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1754 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1755 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1756 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1757 escc_init(hwdef->serial_base, slavio_irq[1],
1758 slavio_irq[1], serial_hds[0], serial_hds[1],
1759 ESCC_CLOCK, 1);
1760
1761 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1762
1763 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1764 /* there is zero or one floppy drive */
1765 memset(fd, 0, sizeof(fd));
1766 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1767 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1768 &fdc_tc);
1769 }
1770
1771 if (drive_get_max_bus(IF_SCSI) > 0) {
1772 fprintf(stderr, "qemu: too many SCSI bus\n");
1773 exit(1);
1774 }
1775
1776 esp_init(hwdef->esp_base, 2,
1777 espdma_memory_read, espdma_memory_write,
1778 espdma, espdma_irq, &esp_reset, &dma_enable);
1779
1780 qdev_connect_gpio_out(espdma, 0, esp_reset);
1781 qdev_connect_gpio_out(espdma, 1, dma_enable);
1782
1783 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1784 RAM_size);
1785
1786 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1787 boot_device, RAM_size, kernel_size, graphic_width,
1788 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1789 "Sun4c");
1790
1791 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1792 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1793 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1794 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1795 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1796 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1797 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1798 if (kernel_cmdline) {
1799 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1800 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1801 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1802 (uint8_t*)strdup(kernel_cmdline),
1803 strlen(kernel_cmdline) + 1);
1804 } else {
1805 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1806 }
1807 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1808 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1809 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1810 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1811 }
1812
1813 /* SPARCstation 2 hardware initialisation */
1814 static void ss2_init(ram_addr_t RAM_size,
1815 const char *boot_device,
1816 const char *kernel_filename, const char *kernel_cmdline,
1817 const char *initrd_filename, const char *cpu_model)
1818 {
1819 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1820 kernel_cmdline, initrd_filename, cpu_model);
1821 }
1822
1823 static QEMUMachine ss2_machine = {
1824 .name = "SS-2",
1825 .desc = "Sun4c platform, SPARCstation 2",
1826 .init = ss2_init,
1827 .use_scsi = 1,
1828 };
1829
1830 static void ss2_machine_init(void)
1831 {
1832 qemu_register_machine(&ss5_machine);
1833 qemu_register_machine(&ss10_machine);
1834 qemu_register_machine(&ss600mp_machine);
1835 qemu_register_machine(&ss20_machine);
1836 qemu_register_machine(&voyager_machine);
1837 qemu_register_machine(&ss_lx_machine);
1838 qemu_register_machine(&ss4_machine);
1839 qemu_register_machine(&scls_machine);
1840 qemu_register_machine(&sbook_machine);
1841 qemu_register_machine(&ss1000_machine);
1842 qemu_register_machine(&ss2000_machine);
1843 qemu_register_machine(&ss2_machine);
1844 }
1845
1846 machine_init(ss2_machine_init);
Qemu copy for testing