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Introduce is_default field for QEMUMachine
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_irq_sink(dev, 0);
383 }
384
385 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
386 const char *boot_device,
387 const char *kernel_filename,
388 const char *kernel_cmdline,
389 const char *initrd_filename, const char *cpu_model)
390
391 {
392 CPUState *env, *envs[MAX_CPUS];
393 unsigned int i;
394 void *iommu, *espdma, *ledma, *nvram;
395 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
396 *espdma_irq, *ledma_irq;
397 qemu_irq *esp_reset, *le_reset;
398 qemu_irq *fdc_tc;
399 qemu_irq *cpu_halt;
400 ram_addr_t ram_offset, prom_offset, idreg_offset;
401 unsigned long kernel_size;
402 int ret;
403 char buf[1024];
404 BlockDriverState *fd[MAX_FD];
405 int drive_index;
406 void *fw_cfg;
407
408 /* init CPUs */
409 if (!cpu_model)
410 cpu_model = hwdef->default_cpu_model;
411
412 for(i = 0; i < smp_cpus; i++) {
413 env = cpu_init(cpu_model);
414 if (!env) {
415 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
416 exit(1);
417 }
418 cpu_sparc_set_id(env, i);
419 envs[i] = env;
420 if (i == 0) {
421 qemu_register_reset(main_cpu_reset, env);
422 } else {
423 qemu_register_reset(secondary_cpu_reset, env);
424 env->halted = 1;
425 }
426 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
427 env->prom_addr = hwdef->slavio_base;
428 }
429
430 for (i = smp_cpus; i < MAX_CPUS; i++)
431 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
432
433
434 /* allocate RAM */
435 if ((uint64_t)RAM_size > hwdef->max_mem) {
436 fprintf(stderr,
437 "qemu: Too much memory for this machine: %d, maximum %d\n",
438 (unsigned int)(RAM_size / (1024 * 1024)),
439 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
440 exit(1);
441 }
442 ram_offset = qemu_ram_alloc(RAM_size);
443 cpu_register_physical_memory(0, RAM_size, ram_offset);
444
445 /* load boot prom */
446 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
447 cpu_register_physical_memory(hwdef->slavio_base,
448 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
449 TARGET_PAGE_MASK,
450 prom_offset | IO_MEM_ROM);
451
452 if (bios_name == NULL)
453 bios_name = PROM_FILENAME;
454 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
455 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
456 if (ret < 0 || ret > PROM_SIZE_MAX)
457 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
458 if (ret < 0 || ret > PROM_SIZE_MAX) {
459 fprintf(stderr, "qemu: could not load prom '%s'\n",
460 buf);
461 exit(1);
462 }
463
464 /* set up devices */
465 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
466 hwdef->intctl_base + 0x10000ULL,
467 &hwdef->intbit_to_level[0],
468 &slavio_irq, &slavio_cpu_irq,
469 cpu_irqs,
470 hwdef->clock_irq);
471
472 if (hwdef->idreg_base) {
473 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
474
475 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
476 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
477 idreg_offset | IO_MEM_ROM);
478 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
479 sizeof(idreg_data));
480 }
481
482 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
483 slavio_irq[hwdef->me_irq]);
484
485 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
486 iommu, &espdma_irq, &esp_reset);
487
488 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
489 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
490 &le_reset);
491
492 if (graphic_depth != 8 && graphic_depth != 24) {
493 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
494 exit (1);
495 }
496 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
497 graphic_depth);
498
499 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
500
501 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
502 hwdef->nvram_size, 8);
503
504 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
505 slavio_cpu_irq, smp_cpus);
506
507 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
508 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
509 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
510 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
511 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
512 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
513
514 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
515 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
516 hwdef->aux1_base, hwdef->aux2_base,
517 slavio_irq[hwdef->me_irq], cpu_halt[0],
518 &fdc_tc);
519
520 if (hwdef->fd_base) {
521 /* there is zero or one floppy drive */
522 memset(fd, 0, sizeof(fd));
523 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
524 if (drive_index != -1)
525 fd[0] = drives_table[drive_index].bdrv;
526
527 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
528 fdc_tc);
529 }
530
531 if (drive_get_max_bus(IF_SCSI) > 0) {
532 fprintf(stderr, "qemu: too many SCSI bus\n");
533 exit(1);
534 }
535
536 esp_init(hwdef->esp_base, 2,
537 espdma_memory_read, espdma_memory_write,
538 espdma, *espdma_irq, esp_reset);
539
540 if (hwdef->cs_base)
541 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
542
543 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
544 RAM_size);
545
546 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
547 boot_device, RAM_size, kernel_size, graphic_width,
548 graphic_height, graphic_depth, hwdef->nvram_machine_id,
549 "Sun4m");
550
551 if (hwdef->ecc_base)
552 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
553 hwdef->ecc_version);
554
555 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
556 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
557 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
558 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
559 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
560 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
561 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
562 if (kernel_cmdline) {
563 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
564 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
565 } else {
566 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
567 }
568 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
569 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
570 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
571 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
572 }
573
574 enum {
575 ss2_id = 0,
576 ss5_id = 32,
577 vger_id,
578 lx_id,
579 ss4_id,
580 scls_id,
581 sbook_id,
582 ss10_id = 64,
583 ss20_id,
584 ss600mp_id,
585 ss1000_id = 96,
586 ss2000_id,
587 };
588
589 static const struct sun4m_hwdef sun4m_hwdefs[] = {
590 /* SS-5 */
591 {
592 .iommu_base = 0x10000000,
593 .tcx_base = 0x50000000,
594 .cs_base = 0x6c000000,
595 .slavio_base = 0x70000000,
596 .ms_kb_base = 0x71000000,
597 .serial_base = 0x71100000,
598 .nvram_base = 0x71200000,
599 .fd_base = 0x71400000,
600 .counter_base = 0x71d00000,
601 .intctl_base = 0x71e00000,
602 .idreg_base = 0x78000000,
603 .dma_base = 0x78400000,
604 .esp_base = 0x78800000,
605 .le_base = 0x78c00000,
606 .apc_base = 0x6a000000,
607 .aux1_base = 0x71900000,
608 .aux2_base = 0x71910000,
609 .vram_size = 0x00100000,
610 .nvram_size = 0x2000,
611 .esp_irq = 18,
612 .le_irq = 16,
613 .clock_irq = 7,
614 .clock1_irq = 19,
615 .ms_kb_irq = 14,
616 .ser_irq = 15,
617 .fd_irq = 22,
618 .me_irq = 30,
619 .cs_irq = 5,
620 .nvram_machine_id = 0x80,
621 .machine_id = ss5_id,
622 .iommu_version = 0x05000000,
623 .intbit_to_level = {
624 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
625 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
626 },
627 .max_mem = 0x10000000,
628 .default_cpu_model = "Fujitsu MB86904",
629 },
630 /* SS-10 */
631 {
632 .iommu_base = 0xfe0000000ULL,
633 .tcx_base = 0xe20000000ULL,
634 .slavio_base = 0xff0000000ULL,
635 .ms_kb_base = 0xff1000000ULL,
636 .serial_base = 0xff1100000ULL,
637 .nvram_base = 0xff1200000ULL,
638 .fd_base = 0xff1700000ULL,
639 .counter_base = 0xff1300000ULL,
640 .intctl_base = 0xff1400000ULL,
641 .idreg_base = 0xef0000000ULL,
642 .dma_base = 0xef0400000ULL,
643 .esp_base = 0xef0800000ULL,
644 .le_base = 0xef0c00000ULL,
645 .apc_base = 0xefa000000ULL, // XXX should not exist
646 .aux1_base = 0xff1800000ULL,
647 .aux2_base = 0xff1a01000ULL,
648 .ecc_base = 0xf00000000ULL,
649 .ecc_version = 0x10000000, // version 0, implementation 1
650 .vram_size = 0x00100000,
651 .nvram_size = 0x2000,
652 .esp_irq = 18,
653 .le_irq = 16,
654 .clock_irq = 7,
655 .clock1_irq = 19,
656 .ms_kb_irq = 14,
657 .ser_irq = 15,
658 .fd_irq = 22,
659 .me_irq = 30,
660 .ecc_irq = 28,
661 .nvram_machine_id = 0x72,
662 .machine_id = ss10_id,
663 .iommu_version = 0x03000000,
664 .intbit_to_level = {
665 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
666 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
667 },
668 .max_mem = 0xf00000000ULL,
669 .default_cpu_model = "TI SuperSparc II",
670 },
671 /* SS-600MP */
672 {
673 .iommu_base = 0xfe0000000ULL,
674 .tcx_base = 0xe20000000ULL,
675 .slavio_base = 0xff0000000ULL,
676 .ms_kb_base = 0xff1000000ULL,
677 .serial_base = 0xff1100000ULL,
678 .nvram_base = 0xff1200000ULL,
679 .counter_base = 0xff1300000ULL,
680 .intctl_base = 0xff1400000ULL,
681 .dma_base = 0xef0081000ULL,
682 .esp_base = 0xef0080000ULL,
683 .le_base = 0xef0060000ULL,
684 .apc_base = 0xefa000000ULL, // XXX should not exist
685 .aux1_base = 0xff1800000ULL,
686 .aux2_base = 0xff1a01000ULL, // XXX should not exist
687 .ecc_base = 0xf00000000ULL,
688 .ecc_version = 0x00000000, // version 0, implementation 0
689 .vram_size = 0x00100000,
690 .nvram_size = 0x2000,
691 .esp_irq = 18,
692 .le_irq = 16,
693 .clock_irq = 7,
694 .clock1_irq = 19,
695 .ms_kb_irq = 14,
696 .ser_irq = 15,
697 .fd_irq = 22,
698 .me_irq = 30,
699 .ecc_irq = 28,
700 .nvram_machine_id = 0x71,
701 .machine_id = ss600mp_id,
702 .iommu_version = 0x01000000,
703 .intbit_to_level = {
704 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
705 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
706 },
707 .max_mem = 0xf00000000ULL,
708 .default_cpu_model = "TI SuperSparc II",
709 },
710 /* SS-20 */
711 {
712 .iommu_base = 0xfe0000000ULL,
713 .tcx_base = 0xe20000000ULL,
714 .slavio_base = 0xff0000000ULL,
715 .ms_kb_base = 0xff1000000ULL,
716 .serial_base = 0xff1100000ULL,
717 .nvram_base = 0xff1200000ULL,
718 .fd_base = 0xff1700000ULL,
719 .counter_base = 0xff1300000ULL,
720 .intctl_base = 0xff1400000ULL,
721 .idreg_base = 0xef0000000ULL,
722 .dma_base = 0xef0400000ULL,
723 .esp_base = 0xef0800000ULL,
724 .le_base = 0xef0c00000ULL,
725 .apc_base = 0xefa000000ULL, // XXX should not exist
726 .aux1_base = 0xff1800000ULL,
727 .aux2_base = 0xff1a01000ULL,
728 .ecc_base = 0xf00000000ULL,
729 .ecc_version = 0x20000000, // version 0, implementation 2
730 .vram_size = 0x00100000,
731 .nvram_size = 0x2000,
732 .esp_irq = 18,
733 .le_irq = 16,
734 .clock_irq = 7,
735 .clock1_irq = 19,
736 .ms_kb_irq = 14,
737 .ser_irq = 15,
738 .fd_irq = 22,
739 .me_irq = 30,
740 .ecc_irq = 28,
741 .nvram_machine_id = 0x72,
742 .machine_id = ss20_id,
743 .iommu_version = 0x13000000,
744 .intbit_to_level = {
745 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
746 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
747 },
748 .max_mem = 0xf00000000ULL,
749 .default_cpu_model = "TI SuperSparc II",
750 },
751 /* Voyager */
752 {
753 .iommu_base = 0x10000000,
754 .tcx_base = 0x50000000,
755 .slavio_base = 0x70000000,
756 .ms_kb_base = 0x71000000,
757 .serial_base = 0x71100000,
758 .nvram_base = 0x71200000,
759 .fd_base = 0x71400000,
760 .counter_base = 0x71d00000,
761 .intctl_base = 0x71e00000,
762 .idreg_base = 0x78000000,
763 .dma_base = 0x78400000,
764 .esp_base = 0x78800000,
765 .le_base = 0x78c00000,
766 .apc_base = 0x71300000, // pmc
767 .aux1_base = 0x71900000,
768 .aux2_base = 0x71910000,
769 .vram_size = 0x00100000,
770 .nvram_size = 0x2000,
771 .esp_irq = 18,
772 .le_irq = 16,
773 .clock_irq = 7,
774 .clock1_irq = 19,
775 .ms_kb_irq = 14,
776 .ser_irq = 15,
777 .fd_irq = 22,
778 .me_irq = 30,
779 .nvram_machine_id = 0x80,
780 .machine_id = vger_id,
781 .iommu_version = 0x05000000,
782 .intbit_to_level = {
783 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
784 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
785 },
786 .max_mem = 0x10000000,
787 .default_cpu_model = "Fujitsu MB86904",
788 },
789 /* LX */
790 {
791 .iommu_base = 0x10000000,
792 .tcx_base = 0x50000000,
793 .slavio_base = 0x70000000,
794 .ms_kb_base = 0x71000000,
795 .serial_base = 0x71100000,
796 .nvram_base = 0x71200000,
797 .fd_base = 0x71400000,
798 .counter_base = 0x71d00000,
799 .intctl_base = 0x71e00000,
800 .idreg_base = 0x78000000,
801 .dma_base = 0x78400000,
802 .esp_base = 0x78800000,
803 .le_base = 0x78c00000,
804 .aux1_base = 0x71900000,
805 .aux2_base = 0x71910000,
806 .vram_size = 0x00100000,
807 .nvram_size = 0x2000,
808 .esp_irq = 18,
809 .le_irq = 16,
810 .clock_irq = 7,
811 .clock1_irq = 19,
812 .ms_kb_irq = 14,
813 .ser_irq = 15,
814 .fd_irq = 22,
815 .me_irq = 30,
816 .nvram_machine_id = 0x80,
817 .machine_id = lx_id,
818 .iommu_version = 0x04000000,
819 .intbit_to_level = {
820 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
821 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
822 },
823 .max_mem = 0x10000000,
824 .default_cpu_model = "TI MicroSparc I",
825 },
826 /* SS-4 */
827 {
828 .iommu_base = 0x10000000,
829 .tcx_base = 0x50000000,
830 .cs_base = 0x6c000000,
831 .slavio_base = 0x70000000,
832 .ms_kb_base = 0x71000000,
833 .serial_base = 0x71100000,
834 .nvram_base = 0x71200000,
835 .fd_base = 0x71400000,
836 .counter_base = 0x71d00000,
837 .intctl_base = 0x71e00000,
838 .idreg_base = 0x78000000,
839 .dma_base = 0x78400000,
840 .esp_base = 0x78800000,
841 .le_base = 0x78c00000,
842 .apc_base = 0x6a000000,
843 .aux1_base = 0x71900000,
844 .aux2_base = 0x71910000,
845 .vram_size = 0x00100000,
846 .nvram_size = 0x2000,
847 .esp_irq = 18,
848 .le_irq = 16,
849 .clock_irq = 7,
850 .clock1_irq = 19,
851 .ms_kb_irq = 14,
852 .ser_irq = 15,
853 .fd_irq = 22,
854 .me_irq = 30,
855 .cs_irq = 5,
856 .nvram_machine_id = 0x80,
857 .machine_id = ss4_id,
858 .iommu_version = 0x05000000,
859 .intbit_to_level = {
860 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
861 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
862 },
863 .max_mem = 0x10000000,
864 .default_cpu_model = "Fujitsu MB86904",
865 },
866 /* SPARCClassic */
867 {
868 .iommu_base = 0x10000000,
869 .tcx_base = 0x50000000,
870 .slavio_base = 0x70000000,
871 .ms_kb_base = 0x71000000,
872 .serial_base = 0x71100000,
873 .nvram_base = 0x71200000,
874 .fd_base = 0x71400000,
875 .counter_base = 0x71d00000,
876 .intctl_base = 0x71e00000,
877 .idreg_base = 0x78000000,
878 .dma_base = 0x78400000,
879 .esp_base = 0x78800000,
880 .le_base = 0x78c00000,
881 .apc_base = 0x6a000000,
882 .aux1_base = 0x71900000,
883 .aux2_base = 0x71910000,
884 .vram_size = 0x00100000,
885 .nvram_size = 0x2000,
886 .esp_irq = 18,
887 .le_irq = 16,
888 .clock_irq = 7,
889 .clock1_irq = 19,
890 .ms_kb_irq = 14,
891 .ser_irq = 15,
892 .fd_irq = 22,
893 .me_irq = 30,
894 .nvram_machine_id = 0x80,
895 .machine_id = scls_id,
896 .iommu_version = 0x05000000,
897 .intbit_to_level = {
898 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
899 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
900 },
901 .max_mem = 0x10000000,
902 .default_cpu_model = "TI MicroSparc I",
903 },
904 /* SPARCbook */
905 {
906 .iommu_base = 0x10000000,
907 .tcx_base = 0x50000000, // XXX
908 .slavio_base = 0x70000000,
909 .ms_kb_base = 0x71000000,
910 .serial_base = 0x71100000,
911 .nvram_base = 0x71200000,
912 .fd_base = 0x71400000,
913 .counter_base = 0x71d00000,
914 .intctl_base = 0x71e00000,
915 .idreg_base = 0x78000000,
916 .dma_base = 0x78400000,
917 .esp_base = 0x78800000,
918 .le_base = 0x78c00000,
919 .apc_base = 0x6a000000,
920 .aux1_base = 0x71900000,
921 .aux2_base = 0x71910000,
922 .vram_size = 0x00100000,
923 .nvram_size = 0x2000,
924 .esp_irq = 18,
925 .le_irq = 16,
926 .clock_irq = 7,
927 .clock1_irq = 19,
928 .ms_kb_irq = 14,
929 .ser_irq = 15,
930 .fd_irq = 22,
931 .me_irq = 30,
932 .nvram_machine_id = 0x80,
933 .machine_id = sbook_id,
934 .iommu_version = 0x05000000,
935 .intbit_to_level = {
936 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
937 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
938 },
939 .max_mem = 0x10000000,
940 .default_cpu_model = "TI MicroSparc I",
941 },
942 };
943
944 /* SPARCstation 5 hardware initialisation */
945 static void ss5_init(ram_addr_t RAM_size,
946 const char *boot_device,
947 const char *kernel_filename, const char *kernel_cmdline,
948 const char *initrd_filename, const char *cpu_model)
949 {
950 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
951 kernel_cmdline, initrd_filename, cpu_model);
952 }
953
954 /* SPARCstation 10 hardware initialisation */
955 static void ss10_init(ram_addr_t RAM_size,
956 const char *boot_device,
957 const char *kernel_filename, const char *kernel_cmdline,
958 const char *initrd_filename, const char *cpu_model)
959 {
960 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
961 kernel_cmdline, initrd_filename, cpu_model);
962 }
963
964 /* SPARCserver 600MP hardware initialisation */
965 static void ss600mp_init(ram_addr_t RAM_size,
966 const char *boot_device,
967 const char *kernel_filename,
968 const char *kernel_cmdline,
969 const char *initrd_filename, const char *cpu_model)
970 {
971 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
972 kernel_cmdline, initrd_filename, cpu_model);
973 }
974
975 /* SPARCstation 20 hardware initialisation */
976 static void ss20_init(ram_addr_t RAM_size,
977 const char *boot_device,
978 const char *kernel_filename, const char *kernel_cmdline,
979 const char *initrd_filename, const char *cpu_model)
980 {
981 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
982 kernel_cmdline, initrd_filename, cpu_model);
983 }
984
985 /* SPARCstation Voyager hardware initialisation */
986 static void vger_init(ram_addr_t RAM_size,
987 const char *boot_device,
988 const char *kernel_filename, const char *kernel_cmdline,
989 const char *initrd_filename, const char *cpu_model)
990 {
991 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
992 kernel_cmdline, initrd_filename, cpu_model);
993 }
994
995 /* SPARCstation LX hardware initialisation */
996 static void ss_lx_init(ram_addr_t RAM_size,
997 const char *boot_device,
998 const char *kernel_filename, const char *kernel_cmdline,
999 const char *initrd_filename, const char *cpu_model)
1000 {
1001 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1002 kernel_cmdline, initrd_filename, cpu_model);
1003 }
1004
1005 /* SPARCstation 4 hardware initialisation */
1006 static void ss4_init(ram_addr_t RAM_size,
1007 const char *boot_device,
1008 const char *kernel_filename, const char *kernel_cmdline,
1009 const char *initrd_filename, const char *cpu_model)
1010 {
1011 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1012 kernel_cmdline, initrd_filename, cpu_model);
1013 }
1014
1015 /* SPARCClassic hardware initialisation */
1016 static void scls_init(ram_addr_t RAM_size,
1017 const char *boot_device,
1018 const char *kernel_filename, const char *kernel_cmdline,
1019 const char *initrd_filename, const char *cpu_model)
1020 {
1021 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1022 kernel_cmdline, initrd_filename, cpu_model);
1023 }
1024
1025 /* SPARCbook hardware initialisation */
1026 static void sbook_init(ram_addr_t RAM_size,
1027 const char *boot_device,
1028 const char *kernel_filename, const char *kernel_cmdline,
1029 const char *initrd_filename, const char *cpu_model)
1030 {
1031 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1032 kernel_cmdline, initrd_filename, cpu_model);
1033 }
1034
1035 static QEMUMachine ss5_machine = {
1036 .name = "SS-5",
1037 .desc = "Sun4m platform, SPARCstation 5",
1038 .init = ss5_init,
1039 .use_scsi = 1,
1040 .is_default = 1,
1041 };
1042
1043 static QEMUMachine ss10_machine = {
1044 .name = "SS-10",
1045 .desc = "Sun4m platform, SPARCstation 10",
1046 .init = ss10_init,
1047 .use_scsi = 1,
1048 .max_cpus = 4,
1049 };
1050
1051 static QEMUMachine ss600mp_machine = {
1052 .name = "SS-600MP",
1053 .desc = "Sun4m platform, SPARCserver 600MP",
1054 .init = ss600mp_init,
1055 .use_scsi = 1,
1056 .max_cpus = 4,
1057 };
1058
1059 static QEMUMachine ss20_machine = {
1060 .name = "SS-20",
1061 .desc = "Sun4m platform, SPARCstation 20",
1062 .init = ss20_init,
1063 .use_scsi = 1,
1064 .max_cpus = 4,
1065 };
1066
1067 static QEMUMachine voyager_machine = {
1068 .name = "Voyager",
1069 .desc = "Sun4m platform, SPARCstation Voyager",
1070 .init = vger_init,
1071 .use_scsi = 1,
1072 };
1073
1074 static QEMUMachine ss_lx_machine = {
1075 .name = "LX",
1076 .desc = "Sun4m platform, SPARCstation LX",
1077 .init = ss_lx_init,
1078 .use_scsi = 1,
1079 };
1080
1081 static QEMUMachine ss4_machine = {
1082 .name = "SS-4",
1083 .desc = "Sun4m platform, SPARCstation 4",
1084 .init = ss4_init,
1085 .use_scsi = 1,
1086 };
1087
1088 static QEMUMachine scls_machine = {
1089 .name = "SPARCClassic",
1090 .desc = "Sun4m platform, SPARCClassic",
1091 .init = scls_init,
1092 .use_scsi = 1,
1093 };
1094
1095 static QEMUMachine sbook_machine = {
1096 .name = "SPARCbook",
1097 .desc = "Sun4m platform, SPARCbook",
1098 .init = sbook_init,
1099 .use_scsi = 1,
1100 };
1101
1102 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1103 /* SS-1000 */
1104 {
1105 .iounit_bases = {
1106 0xfe0200000ULL,
1107 0xfe1200000ULL,
1108 0xfe2200000ULL,
1109 0xfe3200000ULL,
1110 -1,
1111 },
1112 .tcx_base = 0x820000000ULL,
1113 .slavio_base = 0xf00000000ULL,
1114 .ms_kb_base = 0xf00240000ULL,
1115 .serial_base = 0xf00200000ULL,
1116 .nvram_base = 0xf00280000ULL,
1117 .counter_base = 0xf00300000ULL,
1118 .espdma_base = 0x800081000ULL,
1119 .esp_base = 0x800080000ULL,
1120 .ledma_base = 0x800040000ULL,
1121 .le_base = 0x800060000ULL,
1122 .sbi_base = 0xf02800000ULL,
1123 .vram_size = 0x00100000,
1124 .nvram_size = 0x2000,
1125 .esp_irq = 3,
1126 .le_irq = 4,
1127 .clock_irq = 14,
1128 .clock1_irq = 10,
1129 .ms_kb_irq = 12,
1130 .ser_irq = 12,
1131 .nvram_machine_id = 0x80,
1132 .machine_id = ss1000_id,
1133 .iounit_version = 0x03000000,
1134 .max_mem = 0xf00000000ULL,
1135 .default_cpu_model = "TI SuperSparc II",
1136 },
1137 /* SS-2000 */
1138 {
1139 .iounit_bases = {
1140 0xfe0200000ULL,
1141 0xfe1200000ULL,
1142 0xfe2200000ULL,
1143 0xfe3200000ULL,
1144 0xfe4200000ULL,
1145 },
1146 .tcx_base = 0x820000000ULL,
1147 .slavio_base = 0xf00000000ULL,
1148 .ms_kb_base = 0xf00240000ULL,
1149 .serial_base = 0xf00200000ULL,
1150 .nvram_base = 0xf00280000ULL,
1151 .counter_base = 0xf00300000ULL,
1152 .espdma_base = 0x800081000ULL,
1153 .esp_base = 0x800080000ULL,
1154 .ledma_base = 0x800040000ULL,
1155 .le_base = 0x800060000ULL,
1156 .sbi_base = 0xf02800000ULL,
1157 .vram_size = 0x00100000,
1158 .nvram_size = 0x2000,
1159 .esp_irq = 3,
1160 .le_irq = 4,
1161 .clock_irq = 14,
1162 .clock1_irq = 10,
1163 .ms_kb_irq = 12,
1164 .ser_irq = 12,
1165 .nvram_machine_id = 0x80,
1166 .machine_id = ss2000_id,
1167 .iounit_version = 0x03000000,
1168 .max_mem = 0xf00000000ULL,
1169 .default_cpu_model = "TI SuperSparc II",
1170 },
1171 };
1172
1173 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1174 const char *boot_device,
1175 const char *kernel_filename,
1176 const char *kernel_cmdline,
1177 const char *initrd_filename, const char *cpu_model)
1178 {
1179 CPUState *env, *envs[MAX_CPUS];
1180 unsigned int i;
1181 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1182 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1183 *espdma_irq, *ledma_irq;
1184 qemu_irq *esp_reset, *le_reset;
1185 ram_addr_t ram_offset, prom_offset;
1186 unsigned long kernel_size;
1187 int ret;
1188 char buf[1024];
1189 void *fw_cfg;
1190
1191 /* init CPUs */
1192 if (!cpu_model)
1193 cpu_model = hwdef->default_cpu_model;
1194
1195 for (i = 0; i < smp_cpus; i++) {
1196 env = cpu_init(cpu_model);
1197 if (!env) {
1198 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1199 exit(1);
1200 }
1201 cpu_sparc_set_id(env, i);
1202 envs[i] = env;
1203 if (i == 0) {
1204 qemu_register_reset(main_cpu_reset, env);
1205 } else {
1206 qemu_register_reset(secondary_cpu_reset, env);
1207 env->halted = 1;
1208 }
1209 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1210 env->prom_addr = hwdef->slavio_base;
1211 }
1212
1213 for (i = smp_cpus; i < MAX_CPUS; i++)
1214 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1215
1216 /* allocate RAM */
1217 if ((uint64_t)RAM_size > hwdef->max_mem) {
1218 fprintf(stderr,
1219 "qemu: Too much memory for this machine: %d, maximum %d\n",
1220 (unsigned int)(RAM_size / (1024 * 1024)),
1221 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1222 exit(1);
1223 }
1224 ram_offset = qemu_ram_alloc(RAM_size);
1225 cpu_register_physical_memory(0, RAM_size, ram_offset);
1226
1227 /* load boot prom */
1228 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1229 cpu_register_physical_memory(hwdef->slavio_base,
1230 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1231 TARGET_PAGE_MASK,
1232 prom_offset | IO_MEM_ROM);
1233
1234 if (bios_name == NULL)
1235 bios_name = PROM_FILENAME;
1236 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1237 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1238 if (ret < 0 || ret > PROM_SIZE_MAX)
1239 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1240 if (ret < 0 || ret > PROM_SIZE_MAX) {
1241 fprintf(stderr, "qemu: could not load prom '%s'\n",
1242 buf);
1243 exit(1);
1244 }
1245
1246 /* set up devices */
1247 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1248
1249 for (i = 0; i < MAX_IOUNITS; i++)
1250 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1251 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1252 hwdef->iounit_version,
1253 sbi_irq[hwdef->me_irq]);
1254
1255 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1256 iounits[0], &espdma_irq, &esp_reset);
1257
1258 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1259 iounits[0], &ledma_irq, &le_reset);
1260
1261 if (graphic_depth != 8 && graphic_depth != 24) {
1262 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1263 exit (1);
1264 }
1265 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1266 graphic_depth);
1267
1268 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1269
1270 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1271 hwdef->nvram_size, 8);
1272
1273 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1274 sbi_cpu_irq, smp_cpus);
1275
1276 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1277 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1278 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1279 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1280 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1281 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1282
1283 if (drive_get_max_bus(IF_SCSI) > 0) {
1284 fprintf(stderr, "qemu: too many SCSI bus\n");
1285 exit(1);
1286 }
1287
1288 esp_init(hwdef->esp_base, 2,
1289 espdma_memory_read, espdma_memory_write,
1290 espdma, *espdma_irq, esp_reset);
1291
1292 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1293 RAM_size);
1294
1295 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1296 boot_device, RAM_size, kernel_size, graphic_width,
1297 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1298 "Sun4d");
1299
1300 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1301 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1302 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1303 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1304 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1305 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1306 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1307 if (kernel_cmdline) {
1308 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1309 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1310 } else {
1311 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1312 }
1313 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1314 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1315 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1316 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1317 }
1318
1319 /* SPARCserver 1000 hardware initialisation */
1320 static void ss1000_init(ram_addr_t RAM_size,
1321 const char *boot_device,
1322 const char *kernel_filename, const char *kernel_cmdline,
1323 const char *initrd_filename, const char *cpu_model)
1324 {
1325 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1326 kernel_cmdline, initrd_filename, cpu_model);
1327 }
1328
1329 /* SPARCcenter 2000 hardware initialisation */
1330 static void ss2000_init(ram_addr_t RAM_size,
1331 const char *boot_device,
1332 const char *kernel_filename, const char *kernel_cmdline,
1333 const char *initrd_filename, const char *cpu_model)
1334 {
1335 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1336 kernel_cmdline, initrd_filename, cpu_model);
1337 }
1338
1339 static QEMUMachine ss1000_machine = {
1340 .name = "SS-1000",
1341 .desc = "Sun4d platform, SPARCserver 1000",
1342 .init = ss1000_init,
1343 .use_scsi = 1,
1344 .max_cpus = 8,
1345 };
1346
1347 static QEMUMachine ss2000_machine = {
1348 .name = "SS-2000",
1349 .desc = "Sun4d platform, SPARCcenter 2000",
1350 .init = ss2000_init,
1351 .use_scsi = 1,
1352 .max_cpus = 20,
1353 };
1354
1355 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1356 /* SS-2 */
1357 {
1358 .iommu_base = 0xf8000000,
1359 .tcx_base = 0xfe000000,
1360 .slavio_base = 0xf6000000,
1361 .intctl_base = 0xf5000000,
1362 .counter_base = 0xf3000000,
1363 .ms_kb_base = 0xf0000000,
1364 .serial_base = 0xf1000000,
1365 .nvram_base = 0xf2000000,
1366 .fd_base = 0xf7200000,
1367 .dma_base = 0xf8400000,
1368 .esp_base = 0xf8800000,
1369 .le_base = 0xf8c00000,
1370 .aux1_base = 0xf7400003,
1371 .vram_size = 0x00100000,
1372 .nvram_size = 0x800,
1373 .esp_irq = 2,
1374 .le_irq = 3,
1375 .clock_irq = 5,
1376 .clock1_irq = 7,
1377 .ms_kb_irq = 1,
1378 .ser_irq = 1,
1379 .fd_irq = 1,
1380 .me_irq = 1,
1381 .nvram_machine_id = 0x55,
1382 .machine_id = ss2_id,
1383 .max_mem = 0x10000000,
1384 .default_cpu_model = "Cypress CY7C601",
1385 },
1386 };
1387
1388 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1389 const char *boot_device,
1390 const char *kernel_filename,
1391 const char *kernel_cmdline,
1392 const char *initrd_filename, const char *cpu_model)
1393 {
1394 CPUState *env;
1395 void *iommu, *espdma, *ledma, *nvram;
1396 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1397 qemu_irq *esp_reset, *le_reset;
1398 qemu_irq *fdc_tc;
1399 ram_addr_t ram_offset, prom_offset;
1400 unsigned long kernel_size;
1401 int ret;
1402 char buf[1024];
1403 BlockDriverState *fd[MAX_FD];
1404 int drive_index;
1405 void *fw_cfg;
1406
1407 /* init CPU */
1408 if (!cpu_model)
1409 cpu_model = hwdef->default_cpu_model;
1410
1411 env = cpu_init(cpu_model);
1412 if (!env) {
1413 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1414 exit(1);
1415 }
1416
1417 cpu_sparc_set_id(env, 0);
1418
1419 qemu_register_reset(main_cpu_reset, env);
1420 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1421 env->prom_addr = hwdef->slavio_base;
1422
1423 /* allocate RAM */
1424 if ((uint64_t)RAM_size > hwdef->max_mem) {
1425 fprintf(stderr,
1426 "qemu: Too much memory for this machine: %d, maximum %d\n",
1427 (unsigned int)(RAM_size / (1024 * 1024)),
1428 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1429 exit(1);
1430 }
1431 ram_offset = qemu_ram_alloc(RAM_size);
1432 cpu_register_physical_memory(0, RAM_size, ram_offset);
1433
1434 /* load boot prom */
1435 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1436 cpu_register_physical_memory(hwdef->slavio_base,
1437 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1438 TARGET_PAGE_MASK,
1439 prom_offset | IO_MEM_ROM);
1440
1441 if (bios_name == NULL)
1442 bios_name = PROM_FILENAME;
1443 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1444 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1445 if (ret < 0 || ret > PROM_SIZE_MAX)
1446 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1447 if (ret < 0 || ret > PROM_SIZE_MAX) {
1448 fprintf(stderr, "qemu: could not load prom '%s'\n",
1449 buf);
1450 exit(1);
1451 }
1452
1453 /* set up devices */
1454 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1455 &slavio_irq, cpu_irqs);
1456
1457 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1458 slavio_irq[hwdef->me_irq]);
1459
1460 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1461 iommu, &espdma_irq, &esp_reset);
1462
1463 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1464 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1465 &le_reset);
1466
1467 if (graphic_depth != 8 && graphic_depth != 24) {
1468 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1469 exit (1);
1470 }
1471 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1472 graphic_depth);
1473
1474 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1475
1476 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1477 hwdef->nvram_size, 2);
1478
1479 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1480 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1481 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1482 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1483 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1484 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1485 ESCC_CLOCK, 1);
1486
1487 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1488 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1489
1490 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1491 /* there is zero or one floppy drive */
1492 memset(fd, 0, sizeof(fd));
1493 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1494 if (drive_index != -1)
1495 fd[0] = drives_table[drive_index].bdrv;
1496
1497 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1498 fdc_tc);
1499 }
1500
1501 if (drive_get_max_bus(IF_SCSI) > 0) {
1502 fprintf(stderr, "qemu: too many SCSI bus\n");
1503 exit(1);
1504 }
1505
1506 esp_init(hwdef->esp_base, 2,
1507 espdma_memory_read, espdma_memory_write,
1508 espdma, *espdma_irq, esp_reset);
1509
1510 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1511 RAM_size);
1512
1513 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1514 boot_device, RAM_size, kernel_size, graphic_width,
1515 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1516 "Sun4c");
1517
1518 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1519 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1520 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1521 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1522 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1523 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1524 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1525 if (kernel_cmdline) {
1526 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1527 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1528 } else {
1529 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1530 }
1531 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1532 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1533 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1534 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1535 }
1536
1537 /* SPARCstation 2 hardware initialisation */
1538 static void ss2_init(ram_addr_t RAM_size,
1539 const char *boot_device,
1540 const char *kernel_filename, const char *kernel_cmdline,
1541 const char *initrd_filename, const char *cpu_model)
1542 {
1543 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1544 kernel_cmdline, initrd_filename, cpu_model);
1545 }
1546
1547 static QEMUMachine ss2_machine = {
1548 .name = "SS-2",
1549 .desc = "Sun4c platform, SPARCstation 2",
1550 .init = ss2_init,
1551 .use_scsi = 1,
1552 };
1553
1554 static void ss2_machine_init(void)
1555 {
1556 qemu_register_machine(&ss5_machine);
1557 qemu_register_machine(&ss10_machine);
1558 qemu_register_machine(&ss600mp_machine);
1559 qemu_register_machine(&ss20_machine);
1560 qemu_register_machine(&voyager_machine);
1561 qemu_register_machine(&ss_lx_machine);
1562 qemu_register_machine(&ss4_machine);
1563 qemu_register_machine(&scls_machine);
1564 qemu_register_machine(&sbook_machine);
1565 qemu_register_machine(&ss1000_machine);
1566 qemu_register_machine(&ss2000_machine);
1567 qemu_register_machine(&ss2_machine);
1568 }
1569
1570 machine_init(ss2_machine_init);
Qemu copy for testing