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Sparc32: convert idreg to qdev
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39
40 //#define DEBUG_IRQ
41
42 /*
43 * Sun4m architecture was used in the following machines:
44 *
45 * SPARCserver 6xxMP/xx
46 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
47 * SPARCclassic X (4/10)
48 * SPARCstation LX/ZX (4/30)
49 * SPARCstation Voyager
50 * SPARCstation 10/xx, SPARCserver 10/xx
51 * SPARCstation 5, SPARCserver 5
52 * SPARCstation 20/xx, SPARCserver 20
53 * SPARCstation 4
54 *
55 * Sun4d architecture was used in the following machines:
56 *
57 * SPARCcenter 2000
58 * SPARCserver 1000
59 *
60 * Sun4c architecture was used in the following machines:
61 * SPARCstation 1/1+, SPARCserver 1/1+
62 * SPARCstation SLC
63 * SPARCstation IPC
64 * SPARCstation ELC
65 * SPARCstation IPX
66 *
67 * See for example: http://www.sunhelp.org/faq/sunref1.html
68 */
69
70 #ifdef DEBUG_IRQ
71 #define DPRINTF(fmt, ...) \
72 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
73 #else
74 #define DPRINTF(fmt, ...)
75 #endif
76
77 #define KERNEL_LOAD_ADDR 0x00004000
78 #define CMDLINE_ADDR 0x007ff000
79 #define INITRD_LOAD_ADDR 0x00800000
80 #define PROM_SIZE_MAX (1024 * 1024)
81 #define PROM_VADDR 0xffd00000
82 #define PROM_FILENAME "openbios-sparc32"
83 #define CFG_ADDR 0xd00000510ULL
84 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
85
86 #define MAX_CPUS 16
87 #define MAX_PILS 16
88
89 #define ESCC_CLOCK 4915200
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
175 {
176 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
177 return 0;
178 }
179
180 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
181 const char *boot_devices, ram_addr_t RAM_size,
182 uint32_t kernel_size,
183 int width, int height, int depth,
184 int nvram_machine_id, const char *arch)
185 {
186 unsigned int i;
187 uint32_t start, end;
188 uint8_t image[0x1ff0];
189 struct OpenBIOS_nvpart_v1 *part_header;
190
191 memset(image, '\0', sizeof(image));
192
193 start = 0;
194
195 // OpenBIOS nvram variables
196 // Variable partition
197 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
198 part_header->signature = OPENBIOS_PART_SYSTEM;
199 pstrcpy(part_header->name, sizeof(part_header->name), "system");
200
201 end = start + sizeof(struct OpenBIOS_nvpart_v1);
202 for (i = 0; i < nb_prom_envs; i++)
203 end = OpenBIOS_set_var(image, end, prom_envs[i]);
204
205 // End marker
206 image[end++] = '\0';
207
208 end = start + ((end - start + 15) & ~15);
209 OpenBIOS_finish_partition(part_header, end - start);
210
211 // free partition
212 start = end;
213 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
214 part_header->signature = OPENBIOS_PART_FREE;
215 pstrcpy(part_header->name, sizeof(part_header->name), "free");
216
217 end = 0x1fd0;
218 OpenBIOS_finish_partition(part_header, end - start);
219
220 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
221 nvram_machine_id);
222
223 for (i = 0; i < sizeof(image); i++)
224 m48t59_write(nvram, i, image[i]);
225 }
226
227 static void *slavio_intctl;
228
229 void pic_info(Monitor *mon)
230 {
231 if (slavio_intctl)
232 slavio_pic_info(mon, slavio_intctl);
233 }
234
235 void irq_info(Monitor *mon)
236 {
237 if (slavio_intctl)
238 slavio_irq_info(mon, slavio_intctl);
239 }
240
241 void cpu_check_irqs(CPUState *env)
242 {
243 if (env->pil_in && (env->interrupt_index == 0 ||
244 (env->interrupt_index & ~15) == TT_EXTINT)) {
245 unsigned int i;
246
247 for (i = 15; i > 0; i--) {
248 if (env->pil_in & (1 << i)) {
249 int old_interrupt = env->interrupt_index;
250
251 env->interrupt_index = TT_EXTINT | i;
252 if (old_interrupt != env->interrupt_index) {
253 DPRINTF("Set CPU IRQ %d\n", i);
254 cpu_interrupt(env, CPU_INTERRUPT_HARD);
255 }
256 break;
257 }
258 }
259 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
260 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
261 env->interrupt_index = 0;
262 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
263 }
264 }
265
266 static void cpu_set_irq(void *opaque, int irq, int level)
267 {
268 CPUState *env = opaque;
269
270 if (level) {
271 DPRINTF("Raise CPU IRQ %d\n", irq);
272 env->halted = 0;
273 env->pil_in |= 1 << irq;
274 cpu_check_irqs(env);
275 } else {
276 DPRINTF("Lower CPU IRQ %d\n", irq);
277 env->pil_in &= ~(1 << irq);
278 cpu_check_irqs(env);
279 }
280 }
281
282 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
283 {
284 }
285
286 static void *slavio_misc;
287
288 void qemu_system_powerdown(void)
289 {
290 slavio_set_power_fail(slavio_misc, 1);
291 }
292
293 static void main_cpu_reset(void *opaque)
294 {
295 CPUState *env = opaque;
296
297 cpu_reset(env);
298 env->halted = 0;
299 }
300
301 static void secondary_cpu_reset(void *opaque)
302 {
303 CPUState *env = opaque;
304
305 cpu_reset(env);
306 env->halted = 1;
307 }
308
309 static void cpu_halt_signal(void *opaque, int irq, int level)
310 {
311 if (level && cpu_single_env)
312 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *initrd_filename,
317 ram_addr_t RAM_size)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
331 RAM_size - KERNEL_LOAD_ADDR);
332 if (kernel_size < 0)
333 kernel_size = load_image_targphys(kernel_filename,
334 KERNEL_LOAD_ADDR,
335 RAM_size - KERNEL_LOAD_ADDR);
336 if (kernel_size < 0) {
337 fprintf(stderr, "qemu: could not load kernel '%s'\n",
338 kernel_filename);
339 exit(1);
340 }
341
342 /* load initrd */
343 initrd_size = 0;
344 if (initrd_filename) {
345 initrd_size = load_image_targphys(initrd_filename,
346 INITRD_LOAD_ADDR,
347 RAM_size - INITRD_LOAD_ADDR);
348 if (initrd_size < 0) {
349 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
350 initrd_filename);
351 exit(1);
352 }
353 }
354 if (initrd_size > 0) {
355 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
356 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
357 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
358 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
359 break;
360 }
361 }
362 }
363 }
364 return kernel_size;
365 }
366
367 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
368 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
369 {
370 DeviceState *dev;
371 SysBusDevice *s;
372
373 qemu_check_nic_model(&nd_table[0], "lance");
374
375 dev = qdev_create(NULL, "lance");
376 qdev_set_netdev(dev, nd);
377 qdev_set_prop_ptr(dev, "dma", dma_opaque);
378 qdev_init(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_mmio_map(s, 0, leaddr);
381 sysbus_connect_irq(s, 0, irq);
382 *reset = qdev_get_gpio_in(dev, 0);
383 }
384
385 /* NCR89C100/MACIO Internal ID register */
386 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
387
388 static void idreg_init(target_phys_addr_t addr)
389 {
390 DeviceState *dev;
391 SysBusDevice *s;
392
393 dev = qdev_create(NULL, "macio_idreg");
394 qdev_init(dev);
395 s = sysbus_from_qdev(dev);
396
397 sysbus_mmio_map(s, 0, addr);
398 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
399 }
400
401 static void idreg_init1(SysBusDevice *dev)
402 {
403 ram_addr_t idreg_offset;
404
405 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
406 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
407 }
408
409 static SysBusDeviceInfo idreg_info = {
410 .init = idreg_init1,
411 .qdev.name = "macio_idreg",
412 .qdev.size = sizeof(SysBusDevice),
413 .qdev.props = (DevicePropList[]) {
414 {.name = NULL}
415 }
416 };
417
418 static void idreg_register_devices(void)
419 {
420 sysbus_register_withprop(&idreg_info);
421 }
422
423 device_init(idreg_register_devices);
424
425 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
426 const char *boot_device,
427 const char *kernel_filename,
428 const char *kernel_cmdline,
429 const char *initrd_filename, const char *cpu_model)
430
431 {
432 CPUState *env, *envs[MAX_CPUS];
433 unsigned int i;
434 void *iommu, *espdma, *ledma, *nvram;
435 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
436 *espdma_irq, *ledma_irq;
437 qemu_irq *esp_reset, *le_reset;
438 qemu_irq *fdc_tc;
439 qemu_irq *cpu_halt;
440 ram_addr_t ram_offset, prom_offset;
441 unsigned long kernel_size;
442 int ret;
443 char *filename;
444 BlockDriverState *fd[MAX_FD];
445 int drive_index;
446 void *fw_cfg;
447
448 /* init CPUs */
449 if (!cpu_model)
450 cpu_model = hwdef->default_cpu_model;
451
452 for(i = 0; i < smp_cpus; i++) {
453 env = cpu_init(cpu_model);
454 if (!env) {
455 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
456 exit(1);
457 }
458 cpu_sparc_set_id(env, i);
459 envs[i] = env;
460 if (i == 0) {
461 qemu_register_reset(main_cpu_reset, env);
462 } else {
463 qemu_register_reset(secondary_cpu_reset, env);
464 env->halted = 1;
465 }
466 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
467 env->prom_addr = hwdef->slavio_base;
468 }
469
470 for (i = smp_cpus; i < MAX_CPUS; i++)
471 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
472
473
474 /* allocate RAM */
475 if ((uint64_t)RAM_size > hwdef->max_mem) {
476 fprintf(stderr,
477 "qemu: Too much memory for this machine: %d, maximum %d\n",
478 (unsigned int)(RAM_size / (1024 * 1024)),
479 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
480 exit(1);
481 }
482 ram_offset = qemu_ram_alloc(RAM_size);
483 cpu_register_physical_memory(0, RAM_size, ram_offset);
484
485 /* load boot prom */
486 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
487 cpu_register_physical_memory(hwdef->slavio_base,
488 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
489 TARGET_PAGE_MASK,
490 prom_offset | IO_MEM_ROM);
491
492 if (bios_name == NULL)
493 bios_name = PROM_FILENAME;
494 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
495 if (filename) {
496 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
497 NULL, NULL, NULL);
498 if (ret < 0 || ret > PROM_SIZE_MAX)
499 ret = load_image_targphys(filename, hwdef->slavio_base,
500 PROM_SIZE_MAX);
501 qemu_free(filename);
502 } else {
503 ret = -1;
504 }
505 if (ret < 0 || ret > PROM_SIZE_MAX) {
506 fprintf(stderr, "qemu: could not load prom '%s'\n",
507 bios_name);
508 exit(1);
509 }
510
511 /* set up devices */
512 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
513 hwdef->intctl_base + 0x10000ULL,
514 &hwdef->intbit_to_level[0],
515 &slavio_irq, &slavio_cpu_irq,
516 cpu_irqs,
517 hwdef->clock_irq);
518
519 if (hwdef->idreg_base) {
520 idreg_init(hwdef->idreg_base);
521 }
522
523 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
524 slavio_irq[hwdef->me_irq]);
525
526 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
527 iommu, &espdma_irq, &esp_reset);
528
529 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
530 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
531 &le_reset);
532
533 if (graphic_depth != 8 && graphic_depth != 24) {
534 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
535 exit (1);
536 }
537 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
538 graphic_depth);
539
540 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
541
542 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
543 hwdef->nvram_size, 8);
544
545 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
546 slavio_cpu_irq, smp_cpus);
547
548 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
549 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
550 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
551 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
552 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
553 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
554
555 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
556 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
557 hwdef->aux1_base, hwdef->aux2_base,
558 slavio_irq[hwdef->me_irq], cpu_halt[0],
559 &fdc_tc);
560
561 if (hwdef->fd_base) {
562 /* there is zero or one floppy drive */
563 memset(fd, 0, sizeof(fd));
564 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
565 if (drive_index != -1)
566 fd[0] = drives_table[drive_index].bdrv;
567
568 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
569 fdc_tc);
570 }
571
572 if (drive_get_max_bus(IF_SCSI) > 0) {
573 fprintf(stderr, "qemu: too many SCSI bus\n");
574 exit(1);
575 }
576
577 esp_init(hwdef->esp_base, 2,
578 espdma_memory_read, espdma_memory_write,
579 espdma, *espdma_irq, esp_reset);
580
581 if (hwdef->cs_base)
582 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
583
584 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
585 RAM_size);
586
587 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
588 boot_device, RAM_size, kernel_size, graphic_width,
589 graphic_height, graphic_depth, hwdef->nvram_machine_id,
590 "Sun4m");
591
592 if (hwdef->ecc_base)
593 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
594 hwdef->ecc_version);
595
596 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
597 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
598 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
599 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
600 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
601 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
602 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
603 if (kernel_cmdline) {
604 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
605 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
606 } else {
607 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
608 }
609 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
610 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
611 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
612 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
613 }
614
615 enum {
616 ss2_id = 0,
617 ss5_id = 32,
618 vger_id,
619 lx_id,
620 ss4_id,
621 scls_id,
622 sbook_id,
623 ss10_id = 64,
624 ss20_id,
625 ss600mp_id,
626 ss1000_id = 96,
627 ss2000_id,
628 };
629
630 static const struct sun4m_hwdef sun4m_hwdefs[] = {
631 /* SS-5 */
632 {
633 .iommu_base = 0x10000000,
634 .tcx_base = 0x50000000,
635 .cs_base = 0x6c000000,
636 .slavio_base = 0x70000000,
637 .ms_kb_base = 0x71000000,
638 .serial_base = 0x71100000,
639 .nvram_base = 0x71200000,
640 .fd_base = 0x71400000,
641 .counter_base = 0x71d00000,
642 .intctl_base = 0x71e00000,
643 .idreg_base = 0x78000000,
644 .dma_base = 0x78400000,
645 .esp_base = 0x78800000,
646 .le_base = 0x78c00000,
647 .apc_base = 0x6a000000,
648 .aux1_base = 0x71900000,
649 .aux2_base = 0x71910000,
650 .vram_size = 0x00100000,
651 .nvram_size = 0x2000,
652 .esp_irq = 18,
653 .le_irq = 16,
654 .clock_irq = 7,
655 .clock1_irq = 19,
656 .ms_kb_irq = 14,
657 .ser_irq = 15,
658 .fd_irq = 22,
659 .me_irq = 30,
660 .cs_irq = 5,
661 .nvram_machine_id = 0x80,
662 .machine_id = ss5_id,
663 .iommu_version = 0x05000000,
664 .intbit_to_level = {
665 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
666 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
667 },
668 .max_mem = 0x10000000,
669 .default_cpu_model = "Fujitsu MB86904",
670 },
671 /* SS-10 */
672 {
673 .iommu_base = 0xfe0000000ULL,
674 .tcx_base = 0xe20000000ULL,
675 .slavio_base = 0xff0000000ULL,
676 .ms_kb_base = 0xff1000000ULL,
677 .serial_base = 0xff1100000ULL,
678 .nvram_base = 0xff1200000ULL,
679 .fd_base = 0xff1700000ULL,
680 .counter_base = 0xff1300000ULL,
681 .intctl_base = 0xff1400000ULL,
682 .idreg_base = 0xef0000000ULL,
683 .dma_base = 0xef0400000ULL,
684 .esp_base = 0xef0800000ULL,
685 .le_base = 0xef0c00000ULL,
686 .apc_base = 0xefa000000ULL, // XXX should not exist
687 .aux1_base = 0xff1800000ULL,
688 .aux2_base = 0xff1a01000ULL,
689 .ecc_base = 0xf00000000ULL,
690 .ecc_version = 0x10000000, // version 0, implementation 1
691 .vram_size = 0x00100000,
692 .nvram_size = 0x2000,
693 .esp_irq = 18,
694 .le_irq = 16,
695 .clock_irq = 7,
696 .clock1_irq = 19,
697 .ms_kb_irq = 14,
698 .ser_irq = 15,
699 .fd_irq = 22,
700 .me_irq = 30,
701 .ecc_irq = 28,
702 .nvram_machine_id = 0x72,
703 .machine_id = ss10_id,
704 .iommu_version = 0x03000000,
705 .intbit_to_level = {
706 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
707 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
708 },
709 .max_mem = 0xf00000000ULL,
710 .default_cpu_model = "TI SuperSparc II",
711 },
712 /* SS-600MP */
713 {
714 .iommu_base = 0xfe0000000ULL,
715 .tcx_base = 0xe20000000ULL,
716 .slavio_base = 0xff0000000ULL,
717 .ms_kb_base = 0xff1000000ULL,
718 .serial_base = 0xff1100000ULL,
719 .nvram_base = 0xff1200000ULL,
720 .counter_base = 0xff1300000ULL,
721 .intctl_base = 0xff1400000ULL,
722 .dma_base = 0xef0081000ULL,
723 .esp_base = 0xef0080000ULL,
724 .le_base = 0xef0060000ULL,
725 .apc_base = 0xefa000000ULL, // XXX should not exist
726 .aux1_base = 0xff1800000ULL,
727 .aux2_base = 0xff1a01000ULL, // XXX should not exist
728 .ecc_base = 0xf00000000ULL,
729 .ecc_version = 0x00000000, // version 0, implementation 0
730 .vram_size = 0x00100000,
731 .nvram_size = 0x2000,
732 .esp_irq = 18,
733 .le_irq = 16,
734 .clock_irq = 7,
735 .clock1_irq = 19,
736 .ms_kb_irq = 14,
737 .ser_irq = 15,
738 .fd_irq = 22,
739 .me_irq = 30,
740 .ecc_irq = 28,
741 .nvram_machine_id = 0x71,
742 .machine_id = ss600mp_id,
743 .iommu_version = 0x01000000,
744 .intbit_to_level = {
745 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
746 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
747 },
748 .max_mem = 0xf00000000ULL,
749 .default_cpu_model = "TI SuperSparc II",
750 },
751 /* SS-20 */
752 {
753 .iommu_base = 0xfe0000000ULL,
754 .tcx_base = 0xe20000000ULL,
755 .slavio_base = 0xff0000000ULL,
756 .ms_kb_base = 0xff1000000ULL,
757 .serial_base = 0xff1100000ULL,
758 .nvram_base = 0xff1200000ULL,
759 .fd_base = 0xff1700000ULL,
760 .counter_base = 0xff1300000ULL,
761 .intctl_base = 0xff1400000ULL,
762 .idreg_base = 0xef0000000ULL,
763 .dma_base = 0xef0400000ULL,
764 .esp_base = 0xef0800000ULL,
765 .le_base = 0xef0c00000ULL,
766 .apc_base = 0xefa000000ULL, // XXX should not exist
767 .aux1_base = 0xff1800000ULL,
768 .aux2_base = 0xff1a01000ULL,
769 .ecc_base = 0xf00000000ULL,
770 .ecc_version = 0x20000000, // version 0, implementation 2
771 .vram_size = 0x00100000,
772 .nvram_size = 0x2000,
773 .esp_irq = 18,
774 .le_irq = 16,
775 .clock_irq = 7,
776 .clock1_irq = 19,
777 .ms_kb_irq = 14,
778 .ser_irq = 15,
779 .fd_irq = 22,
780 .me_irq = 30,
781 .ecc_irq = 28,
782 .nvram_machine_id = 0x72,
783 .machine_id = ss20_id,
784 .iommu_version = 0x13000000,
785 .intbit_to_level = {
786 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
787 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
788 },
789 .max_mem = 0xf00000000ULL,
790 .default_cpu_model = "TI SuperSparc II",
791 },
792 /* Voyager */
793 {
794 .iommu_base = 0x10000000,
795 .tcx_base = 0x50000000,
796 .slavio_base = 0x70000000,
797 .ms_kb_base = 0x71000000,
798 .serial_base = 0x71100000,
799 .nvram_base = 0x71200000,
800 .fd_base = 0x71400000,
801 .counter_base = 0x71d00000,
802 .intctl_base = 0x71e00000,
803 .idreg_base = 0x78000000,
804 .dma_base = 0x78400000,
805 .esp_base = 0x78800000,
806 .le_base = 0x78c00000,
807 .apc_base = 0x71300000, // pmc
808 .aux1_base = 0x71900000,
809 .aux2_base = 0x71910000,
810 .vram_size = 0x00100000,
811 .nvram_size = 0x2000,
812 .esp_irq = 18,
813 .le_irq = 16,
814 .clock_irq = 7,
815 .clock1_irq = 19,
816 .ms_kb_irq = 14,
817 .ser_irq = 15,
818 .fd_irq = 22,
819 .me_irq = 30,
820 .nvram_machine_id = 0x80,
821 .machine_id = vger_id,
822 .iommu_version = 0x05000000,
823 .intbit_to_level = {
824 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
825 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
826 },
827 .max_mem = 0x10000000,
828 .default_cpu_model = "Fujitsu MB86904",
829 },
830 /* LX */
831 {
832 .iommu_base = 0x10000000,
833 .tcx_base = 0x50000000,
834 .slavio_base = 0x70000000,
835 .ms_kb_base = 0x71000000,
836 .serial_base = 0x71100000,
837 .nvram_base = 0x71200000,
838 .fd_base = 0x71400000,
839 .counter_base = 0x71d00000,
840 .intctl_base = 0x71e00000,
841 .idreg_base = 0x78000000,
842 .dma_base = 0x78400000,
843 .esp_base = 0x78800000,
844 .le_base = 0x78c00000,
845 .aux1_base = 0x71900000,
846 .aux2_base = 0x71910000,
847 .vram_size = 0x00100000,
848 .nvram_size = 0x2000,
849 .esp_irq = 18,
850 .le_irq = 16,
851 .clock_irq = 7,
852 .clock1_irq = 19,
853 .ms_kb_irq = 14,
854 .ser_irq = 15,
855 .fd_irq = 22,
856 .me_irq = 30,
857 .nvram_machine_id = 0x80,
858 .machine_id = lx_id,
859 .iommu_version = 0x04000000,
860 .intbit_to_level = {
861 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
862 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
863 },
864 .max_mem = 0x10000000,
865 .default_cpu_model = "TI MicroSparc I",
866 },
867 /* SS-4 */
868 {
869 .iommu_base = 0x10000000,
870 .tcx_base = 0x50000000,
871 .cs_base = 0x6c000000,
872 .slavio_base = 0x70000000,
873 .ms_kb_base = 0x71000000,
874 .serial_base = 0x71100000,
875 .nvram_base = 0x71200000,
876 .fd_base = 0x71400000,
877 .counter_base = 0x71d00000,
878 .intctl_base = 0x71e00000,
879 .idreg_base = 0x78000000,
880 .dma_base = 0x78400000,
881 .esp_base = 0x78800000,
882 .le_base = 0x78c00000,
883 .apc_base = 0x6a000000,
884 .aux1_base = 0x71900000,
885 .aux2_base = 0x71910000,
886 .vram_size = 0x00100000,
887 .nvram_size = 0x2000,
888 .esp_irq = 18,
889 .le_irq = 16,
890 .clock_irq = 7,
891 .clock1_irq = 19,
892 .ms_kb_irq = 14,
893 .ser_irq = 15,
894 .fd_irq = 22,
895 .me_irq = 30,
896 .cs_irq = 5,
897 .nvram_machine_id = 0x80,
898 .machine_id = ss4_id,
899 .iommu_version = 0x05000000,
900 .intbit_to_level = {
901 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
902 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
903 },
904 .max_mem = 0x10000000,
905 .default_cpu_model = "Fujitsu MB86904",
906 },
907 /* SPARCClassic */
908 {
909 .iommu_base = 0x10000000,
910 .tcx_base = 0x50000000,
911 .slavio_base = 0x70000000,
912 .ms_kb_base = 0x71000000,
913 .serial_base = 0x71100000,
914 .nvram_base = 0x71200000,
915 .fd_base = 0x71400000,
916 .counter_base = 0x71d00000,
917 .intctl_base = 0x71e00000,
918 .idreg_base = 0x78000000,
919 .dma_base = 0x78400000,
920 .esp_base = 0x78800000,
921 .le_base = 0x78c00000,
922 .apc_base = 0x6a000000,
923 .aux1_base = 0x71900000,
924 .aux2_base = 0x71910000,
925 .vram_size = 0x00100000,
926 .nvram_size = 0x2000,
927 .esp_irq = 18,
928 .le_irq = 16,
929 .clock_irq = 7,
930 .clock1_irq = 19,
931 .ms_kb_irq = 14,
932 .ser_irq = 15,
933 .fd_irq = 22,
934 .me_irq = 30,
935 .nvram_machine_id = 0x80,
936 .machine_id = scls_id,
937 .iommu_version = 0x05000000,
938 .intbit_to_level = {
939 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
940 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
941 },
942 .max_mem = 0x10000000,
943 .default_cpu_model = "TI MicroSparc I",
944 },
945 /* SPARCbook */
946 {
947 .iommu_base = 0x10000000,
948 .tcx_base = 0x50000000, // XXX
949 .slavio_base = 0x70000000,
950 .ms_kb_base = 0x71000000,
951 .serial_base = 0x71100000,
952 .nvram_base = 0x71200000,
953 .fd_base = 0x71400000,
954 .counter_base = 0x71d00000,
955 .intctl_base = 0x71e00000,
956 .idreg_base = 0x78000000,
957 .dma_base = 0x78400000,
958 .esp_base = 0x78800000,
959 .le_base = 0x78c00000,
960 .apc_base = 0x6a000000,
961 .aux1_base = 0x71900000,
962 .aux2_base = 0x71910000,
963 .vram_size = 0x00100000,
964 .nvram_size = 0x2000,
965 .esp_irq = 18,
966 .le_irq = 16,
967 .clock_irq = 7,
968 .clock1_irq = 19,
969 .ms_kb_irq = 14,
970 .ser_irq = 15,
971 .fd_irq = 22,
972 .me_irq = 30,
973 .nvram_machine_id = 0x80,
974 .machine_id = sbook_id,
975 .iommu_version = 0x05000000,
976 .intbit_to_level = {
977 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
978 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
979 },
980 .max_mem = 0x10000000,
981 .default_cpu_model = "TI MicroSparc I",
982 },
983 };
984
985 /* SPARCstation 5 hardware initialisation */
986 static void ss5_init(ram_addr_t RAM_size,
987 const char *boot_device,
988 const char *kernel_filename, const char *kernel_cmdline,
989 const char *initrd_filename, const char *cpu_model)
990 {
991 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
992 kernel_cmdline, initrd_filename, cpu_model);
993 }
994
995 /* SPARCstation 10 hardware initialisation */
996 static void ss10_init(ram_addr_t RAM_size,
997 const char *boot_device,
998 const char *kernel_filename, const char *kernel_cmdline,
999 const char *initrd_filename, const char *cpu_model)
1000 {
1001 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1002 kernel_cmdline, initrd_filename, cpu_model);
1003 }
1004
1005 /* SPARCserver 600MP hardware initialisation */
1006 static void ss600mp_init(ram_addr_t RAM_size,
1007 const char *boot_device,
1008 const char *kernel_filename,
1009 const char *kernel_cmdline,
1010 const char *initrd_filename, const char *cpu_model)
1011 {
1012 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1013 kernel_cmdline, initrd_filename, cpu_model);
1014 }
1015
1016 /* SPARCstation 20 hardware initialisation */
1017 static void ss20_init(ram_addr_t RAM_size,
1018 const char *boot_device,
1019 const char *kernel_filename, const char *kernel_cmdline,
1020 const char *initrd_filename, const char *cpu_model)
1021 {
1022 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1023 kernel_cmdline, initrd_filename, cpu_model);
1024 }
1025
1026 /* SPARCstation Voyager hardware initialisation */
1027 static void vger_init(ram_addr_t RAM_size,
1028 const char *boot_device,
1029 const char *kernel_filename, const char *kernel_cmdline,
1030 const char *initrd_filename, const char *cpu_model)
1031 {
1032 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1033 kernel_cmdline, initrd_filename, cpu_model);
1034 }
1035
1036 /* SPARCstation LX hardware initialisation */
1037 static void ss_lx_init(ram_addr_t RAM_size,
1038 const char *boot_device,
1039 const char *kernel_filename, const char *kernel_cmdline,
1040 const char *initrd_filename, const char *cpu_model)
1041 {
1042 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1043 kernel_cmdline, initrd_filename, cpu_model);
1044 }
1045
1046 /* SPARCstation 4 hardware initialisation */
1047 static void ss4_init(ram_addr_t RAM_size,
1048 const char *boot_device,
1049 const char *kernel_filename, const char *kernel_cmdline,
1050 const char *initrd_filename, const char *cpu_model)
1051 {
1052 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1053 kernel_cmdline, initrd_filename, cpu_model);
1054 }
1055
1056 /* SPARCClassic hardware initialisation */
1057 static void scls_init(ram_addr_t RAM_size,
1058 const char *boot_device,
1059 const char *kernel_filename, const char *kernel_cmdline,
1060 const char *initrd_filename, const char *cpu_model)
1061 {
1062 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1063 kernel_cmdline, initrd_filename, cpu_model);
1064 }
1065
1066 /* SPARCbook hardware initialisation */
1067 static void sbook_init(ram_addr_t RAM_size,
1068 const char *boot_device,
1069 const char *kernel_filename, const char *kernel_cmdline,
1070 const char *initrd_filename, const char *cpu_model)
1071 {
1072 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1073 kernel_cmdline, initrd_filename, cpu_model);
1074 }
1075
1076 static QEMUMachine ss5_machine = {
1077 .name = "SS-5",
1078 .desc = "Sun4m platform, SPARCstation 5",
1079 .init = ss5_init,
1080 .use_scsi = 1,
1081 .is_default = 1,
1082 };
1083
1084 static QEMUMachine ss10_machine = {
1085 .name = "SS-10",
1086 .desc = "Sun4m platform, SPARCstation 10",
1087 .init = ss10_init,
1088 .use_scsi = 1,
1089 .max_cpus = 4,
1090 };
1091
1092 static QEMUMachine ss600mp_machine = {
1093 .name = "SS-600MP",
1094 .desc = "Sun4m platform, SPARCserver 600MP",
1095 .init = ss600mp_init,
1096 .use_scsi = 1,
1097 .max_cpus = 4,
1098 };
1099
1100 static QEMUMachine ss20_machine = {
1101 .name = "SS-20",
1102 .desc = "Sun4m platform, SPARCstation 20",
1103 .init = ss20_init,
1104 .use_scsi = 1,
1105 .max_cpus = 4,
1106 };
1107
1108 static QEMUMachine voyager_machine = {
1109 .name = "Voyager",
1110 .desc = "Sun4m platform, SPARCstation Voyager",
1111 .init = vger_init,
1112 .use_scsi = 1,
1113 };
1114
1115 static QEMUMachine ss_lx_machine = {
1116 .name = "LX",
1117 .desc = "Sun4m platform, SPARCstation LX",
1118 .init = ss_lx_init,
1119 .use_scsi = 1,
1120 };
1121
1122 static QEMUMachine ss4_machine = {
1123 .name = "SS-4",
1124 .desc = "Sun4m platform, SPARCstation 4",
1125 .init = ss4_init,
1126 .use_scsi = 1,
1127 };
1128
1129 static QEMUMachine scls_machine = {
1130 .name = "SPARCClassic",
1131 .desc = "Sun4m platform, SPARCClassic",
1132 .init = scls_init,
1133 .use_scsi = 1,
1134 };
1135
1136 static QEMUMachine sbook_machine = {
1137 .name = "SPARCbook",
1138 .desc = "Sun4m platform, SPARCbook",
1139 .init = sbook_init,
1140 .use_scsi = 1,
1141 };
1142
1143 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1144 /* SS-1000 */
1145 {
1146 .iounit_bases = {
1147 0xfe0200000ULL,
1148 0xfe1200000ULL,
1149 0xfe2200000ULL,
1150 0xfe3200000ULL,
1151 -1,
1152 },
1153 .tcx_base = 0x820000000ULL,
1154 .slavio_base = 0xf00000000ULL,
1155 .ms_kb_base = 0xf00240000ULL,
1156 .serial_base = 0xf00200000ULL,
1157 .nvram_base = 0xf00280000ULL,
1158 .counter_base = 0xf00300000ULL,
1159 .espdma_base = 0x800081000ULL,
1160 .esp_base = 0x800080000ULL,
1161 .ledma_base = 0x800040000ULL,
1162 .le_base = 0x800060000ULL,
1163 .sbi_base = 0xf02800000ULL,
1164 .vram_size = 0x00100000,
1165 .nvram_size = 0x2000,
1166 .esp_irq = 3,
1167 .le_irq = 4,
1168 .clock_irq = 14,
1169 .clock1_irq = 10,
1170 .ms_kb_irq = 12,
1171 .ser_irq = 12,
1172 .nvram_machine_id = 0x80,
1173 .machine_id = ss1000_id,
1174 .iounit_version = 0x03000000,
1175 .max_mem = 0xf00000000ULL,
1176 .default_cpu_model = "TI SuperSparc II",
1177 },
1178 /* SS-2000 */
1179 {
1180 .iounit_bases = {
1181 0xfe0200000ULL,
1182 0xfe1200000ULL,
1183 0xfe2200000ULL,
1184 0xfe3200000ULL,
1185 0xfe4200000ULL,
1186 },
1187 .tcx_base = 0x820000000ULL,
1188 .slavio_base = 0xf00000000ULL,
1189 .ms_kb_base = 0xf00240000ULL,
1190 .serial_base = 0xf00200000ULL,
1191 .nvram_base = 0xf00280000ULL,
1192 .counter_base = 0xf00300000ULL,
1193 .espdma_base = 0x800081000ULL,
1194 .esp_base = 0x800080000ULL,
1195 .ledma_base = 0x800040000ULL,
1196 .le_base = 0x800060000ULL,
1197 .sbi_base = 0xf02800000ULL,
1198 .vram_size = 0x00100000,
1199 .nvram_size = 0x2000,
1200 .esp_irq = 3,
1201 .le_irq = 4,
1202 .clock_irq = 14,
1203 .clock1_irq = 10,
1204 .ms_kb_irq = 12,
1205 .ser_irq = 12,
1206 .nvram_machine_id = 0x80,
1207 .machine_id = ss2000_id,
1208 .iounit_version = 0x03000000,
1209 .max_mem = 0xf00000000ULL,
1210 .default_cpu_model = "TI SuperSparc II",
1211 },
1212 };
1213
1214 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1215 const char *boot_device,
1216 const char *kernel_filename,
1217 const char *kernel_cmdline,
1218 const char *initrd_filename, const char *cpu_model)
1219 {
1220 CPUState *env, *envs[MAX_CPUS];
1221 unsigned int i;
1222 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram, *sbi;
1223 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1224 *espdma_irq, *ledma_irq;
1225 qemu_irq *esp_reset, *le_reset;
1226 ram_addr_t ram_offset, prom_offset;
1227 unsigned long kernel_size;
1228 int ret;
1229 char *filename;
1230 void *fw_cfg;
1231
1232 /* init CPUs */
1233 if (!cpu_model)
1234 cpu_model = hwdef->default_cpu_model;
1235
1236 for (i = 0; i < smp_cpus; i++) {
1237 env = cpu_init(cpu_model);
1238 if (!env) {
1239 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1240 exit(1);
1241 }
1242 cpu_sparc_set_id(env, i);
1243 envs[i] = env;
1244 if (i == 0) {
1245 qemu_register_reset(main_cpu_reset, env);
1246 } else {
1247 qemu_register_reset(secondary_cpu_reset, env);
1248 env->halted = 1;
1249 }
1250 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1251 env->prom_addr = hwdef->slavio_base;
1252 }
1253
1254 for (i = smp_cpus; i < MAX_CPUS; i++)
1255 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1256
1257 /* allocate RAM */
1258 if ((uint64_t)RAM_size > hwdef->max_mem) {
1259 fprintf(stderr,
1260 "qemu: Too much memory for this machine: %d, maximum %d\n",
1261 (unsigned int)(RAM_size / (1024 * 1024)),
1262 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1263 exit(1);
1264 }
1265 ram_offset = qemu_ram_alloc(RAM_size);
1266 cpu_register_physical_memory(0, RAM_size, ram_offset);
1267
1268 /* load boot prom */
1269 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1270 cpu_register_physical_memory(hwdef->slavio_base,
1271 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1272 TARGET_PAGE_MASK,
1273 prom_offset | IO_MEM_ROM);
1274
1275 if (bios_name == NULL)
1276 bios_name = PROM_FILENAME;
1277 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1278 if (filename) {
1279 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1280 NULL, NULL, NULL);
1281 if (ret < 0 || ret > PROM_SIZE_MAX)
1282 ret = load_image_targphys(filename, hwdef->slavio_base,
1283 PROM_SIZE_MAX);
1284 qemu_free(filename);
1285 } else {
1286 ret = -1;
1287 }
1288 if (ret < 0 || ret > PROM_SIZE_MAX) {
1289 fprintf(stderr, "qemu: could not load prom '%s'\n",
1290 bios_name);
1291 exit(1);
1292 }
1293
1294 /* set up devices */
1295 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1296
1297 for (i = 0; i < MAX_IOUNITS; i++)
1298 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1299 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1300 hwdef->iounit_version,
1301 sbi_irq[hwdef->me_irq]);
1302
1303 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1304 iounits[0], &espdma_irq, &esp_reset);
1305
1306 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1307 iounits[0], &ledma_irq, &le_reset);
1308
1309 if (graphic_depth != 8 && graphic_depth != 24) {
1310 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1311 exit (1);
1312 }
1313 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1314 graphic_depth);
1315
1316 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1317
1318 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1319 hwdef->nvram_size, 8);
1320
1321 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1322 sbi_cpu_irq, smp_cpus);
1323
1324 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1325 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1326 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1327 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1328 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1329 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1330
1331 if (drive_get_max_bus(IF_SCSI) > 0) {
1332 fprintf(stderr, "qemu: too many SCSI bus\n");
1333 exit(1);
1334 }
1335
1336 esp_init(hwdef->esp_base, 2,
1337 espdma_memory_read, espdma_memory_write,
1338 espdma, *espdma_irq, esp_reset);
1339
1340 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1341 RAM_size);
1342
1343 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1344 boot_device, RAM_size, kernel_size, graphic_width,
1345 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1346 "Sun4d");
1347
1348 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1349 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1350 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1351 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1352 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1353 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1354 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1355 if (kernel_cmdline) {
1356 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1357 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1358 } else {
1359 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1360 }
1361 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1362 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1363 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1364 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1365 }
1366
1367 /* SPARCserver 1000 hardware initialisation */
1368 static void ss1000_init(ram_addr_t RAM_size,
1369 const char *boot_device,
1370 const char *kernel_filename, const char *kernel_cmdline,
1371 const char *initrd_filename, const char *cpu_model)
1372 {
1373 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1374 kernel_cmdline, initrd_filename, cpu_model);
1375 }
1376
1377 /* SPARCcenter 2000 hardware initialisation */
1378 static void ss2000_init(ram_addr_t RAM_size,
1379 const char *boot_device,
1380 const char *kernel_filename, const char *kernel_cmdline,
1381 const char *initrd_filename, const char *cpu_model)
1382 {
1383 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1384 kernel_cmdline, initrd_filename, cpu_model);
1385 }
1386
1387 static QEMUMachine ss1000_machine = {
1388 .name = "SS-1000",
1389 .desc = "Sun4d platform, SPARCserver 1000",
1390 .init = ss1000_init,
1391 .use_scsi = 1,
1392 .max_cpus = 8,
1393 };
1394
1395 static QEMUMachine ss2000_machine = {
1396 .name = "SS-2000",
1397 .desc = "Sun4d platform, SPARCcenter 2000",
1398 .init = ss2000_init,
1399 .use_scsi = 1,
1400 .max_cpus = 20,
1401 };
1402
1403 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1404 /* SS-2 */
1405 {
1406 .iommu_base = 0xf8000000,
1407 .tcx_base = 0xfe000000,
1408 .slavio_base = 0xf6000000,
1409 .intctl_base = 0xf5000000,
1410 .counter_base = 0xf3000000,
1411 .ms_kb_base = 0xf0000000,
1412 .serial_base = 0xf1000000,
1413 .nvram_base = 0xf2000000,
1414 .fd_base = 0xf7200000,
1415 .dma_base = 0xf8400000,
1416 .esp_base = 0xf8800000,
1417 .le_base = 0xf8c00000,
1418 .aux1_base = 0xf7400003,
1419 .vram_size = 0x00100000,
1420 .nvram_size = 0x800,
1421 .esp_irq = 2,
1422 .le_irq = 3,
1423 .clock_irq = 5,
1424 .clock1_irq = 7,
1425 .ms_kb_irq = 1,
1426 .ser_irq = 1,
1427 .fd_irq = 1,
1428 .me_irq = 1,
1429 .nvram_machine_id = 0x55,
1430 .machine_id = ss2_id,
1431 .max_mem = 0x10000000,
1432 .default_cpu_model = "Cypress CY7C601",
1433 },
1434 };
1435
1436 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1437 const char *boot_device,
1438 const char *kernel_filename,
1439 const char *kernel_cmdline,
1440 const char *initrd_filename, const char *cpu_model)
1441 {
1442 CPUState *env;
1443 void *iommu, *espdma, *ledma, *nvram;
1444 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1445 qemu_irq *esp_reset, *le_reset;
1446 qemu_irq *fdc_tc;
1447 ram_addr_t ram_offset, prom_offset;
1448 unsigned long kernel_size;
1449 int ret;
1450 char *filename;
1451 BlockDriverState *fd[MAX_FD];
1452 int drive_index;
1453 void *fw_cfg;
1454
1455 /* init CPU */
1456 if (!cpu_model)
1457 cpu_model = hwdef->default_cpu_model;
1458
1459 env = cpu_init(cpu_model);
1460 if (!env) {
1461 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1462 exit(1);
1463 }
1464
1465 cpu_sparc_set_id(env, 0);
1466
1467 qemu_register_reset(main_cpu_reset, env);
1468 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1469 env->prom_addr = hwdef->slavio_base;
1470
1471 /* allocate RAM */
1472 if ((uint64_t)RAM_size > hwdef->max_mem) {
1473 fprintf(stderr,
1474 "qemu: Too much memory for this machine: %d, maximum %d\n",
1475 (unsigned int)(RAM_size / (1024 * 1024)),
1476 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1477 exit(1);
1478 }
1479 ram_offset = qemu_ram_alloc(RAM_size);
1480 cpu_register_physical_memory(0, RAM_size, ram_offset);
1481
1482 /* load boot prom */
1483 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
1484 cpu_register_physical_memory(hwdef->slavio_base,
1485 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1486 TARGET_PAGE_MASK,
1487 prom_offset | IO_MEM_ROM);
1488
1489 if (bios_name == NULL)
1490 bios_name = PROM_FILENAME;
1491 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1492 if (filename) {
1493 ret = load_elf(filename, hwdef->slavio_base - PROM_VADDR,
1494 NULL, NULL, NULL);
1495 if (ret < 0 || ret > PROM_SIZE_MAX)
1496 ret = load_image_targphys(filename, hwdef->slavio_base,
1497 PROM_SIZE_MAX);
1498 qemu_free(filename);
1499 } else {
1500 ret = -1;
1501 }
1502 if (ret < 0 || ret > PROM_SIZE_MAX) {
1503 fprintf(stderr, "qemu: could not load prom '%s'\n",
1504 filename);
1505 exit(1);
1506 }
1507
1508 /* set up devices */
1509 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1510 &slavio_irq, cpu_irqs);
1511
1512 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1513 slavio_irq[hwdef->me_irq]);
1514
1515 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1516 iommu, &espdma_irq, &esp_reset);
1517
1518 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1519 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1520 &le_reset);
1521
1522 if (graphic_depth != 8 && graphic_depth != 24) {
1523 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1524 exit (1);
1525 }
1526 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1527 graphic_depth);
1528
1529 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1530
1531 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1532 hwdef->nvram_size, 2);
1533
1534 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1535 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1536 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1537 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1538 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1539 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1540 ESCC_CLOCK, 1);
1541
1542 slavio_misc = slavio_misc_init(0, 0, hwdef->aux1_base, 0,
1543 slavio_irq[hwdef->me_irq], NULL, &fdc_tc);
1544
1545 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1546 /* there is zero or one floppy drive */
1547 memset(fd, 0, sizeof(fd));
1548 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1549 if (drive_index != -1)
1550 fd[0] = drives_table[drive_index].bdrv;
1551
1552 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1553 fdc_tc);
1554 }
1555
1556 if (drive_get_max_bus(IF_SCSI) > 0) {
1557 fprintf(stderr, "qemu: too many SCSI bus\n");
1558 exit(1);
1559 }
1560
1561 esp_init(hwdef->esp_base, 2,
1562 espdma_memory_read, espdma_memory_write,
1563 espdma, *espdma_irq, esp_reset);
1564
1565 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1566 RAM_size);
1567
1568 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1569 boot_device, RAM_size, kernel_size, graphic_width,
1570 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1571 "Sun4c");
1572
1573 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1574 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1575 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1576 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1577 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1578 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1579 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1580 if (kernel_cmdline) {
1581 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1582 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1583 } else {
1584 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1585 }
1586 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1587 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1588 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1589 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1590 }
1591
1592 /* SPARCstation 2 hardware initialisation */
1593 static void ss2_init(ram_addr_t RAM_size,
1594 const char *boot_device,
1595 const char *kernel_filename, const char *kernel_cmdline,
1596 const char *initrd_filename, const char *cpu_model)
1597 {
1598 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1599 kernel_cmdline, initrd_filename, cpu_model);
1600 }
1601
1602 static QEMUMachine ss2_machine = {
1603 .name = "SS-2",
1604 .desc = "Sun4c platform, SPARCstation 2",
1605 .init = ss2_init,
1606 .use_scsi = 1,
1607 };
1608
1609 static void ss2_machine_init(void)
1610 {
1611 qemu_register_machine(&ss5_machine);
1612 qemu_register_machine(&ss10_machine);
1613 qemu_register_machine(&ss600mp_machine);
1614 qemu_register_machine(&ss20_machine);
1615 qemu_register_machine(&voyager_machine);
1616 qemu_register_machine(&ss_lx_machine);
1617 qemu_register_machine(&ss4_machine);
1618 qemu_register_machine(&scls_machine);
1619 qemu_register_machine(&sbook_machine);
1620 qemu_register_machine(&ss1000_machine);
1621 qemu_register_machine(&ss2000_machine);
1622 qemu_register_machine(&ss2_machine);
1623 }
1624
1625 machine_init(ss2_machine_init);
Qemu copy for testing