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Make DMA bottom-half driven (v2)
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38
39 //#define DEBUG_IRQ
40
41 /*
42 * Sun4m architecture was used in the following machines:
43 *
44 * SPARCserver 6xxMP/xx
45 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
46 * SPARCclassic X (4/10)
47 * SPARCstation LX/ZX (4/30)
48 * SPARCstation Voyager
49 * SPARCstation 10/xx, SPARCserver 10/xx
50 * SPARCstation 5, SPARCserver 5
51 * SPARCstation 20/xx, SPARCserver 20
52 * SPARCstation 4
53 *
54 * Sun4d architecture was used in the following machines:
55 *
56 * SPARCcenter 2000
57 * SPARCserver 1000
58 *
59 * Sun4c architecture was used in the following machines:
60 * SPARCstation 1/1+, SPARCserver 1/1+
61 * SPARCstation SLC
62 * SPARCstation IPC
63 * SPARCstation ELC
64 * SPARCstation IPX
65 *
66 * See for example: http://www.sunhelp.org/faq/sunref1.html
67 */
68
69 #ifdef DEBUG_IRQ
70 #define DPRINTF(fmt, args...) \
71 do { printf("CPUIRQ: " fmt , ##args); } while (0)
72 #else
73 #define DPRINTF(fmt, args...)
74 #endif
75
76 #define KERNEL_LOAD_ADDR 0x00004000
77 #define CMDLINE_ADDR 0x007ff000
78 #define INITRD_LOAD_ADDR 0x00800000
79 #define PROM_SIZE_MAX (512 * 1024)
80 #define PROM_VADDR 0xffd00000
81 #define PROM_FILENAME "openbios-sparc32"
82 #define CFG_ADDR 0xd00000510ULL
83 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
84
85 // Control plane, 8-bit and 24-bit planes
86 #define TCX_SIZE (9 * 1024 * 1024)
87
88 #define MAX_CPUS 16
89 #define MAX_PILS 16
90
91 struct sun4m_hwdef {
92 target_phys_addr_t iommu_base, slavio_base;
93 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
94 target_phys_addr_t serial_base, fd_base;
95 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
96 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
97 target_phys_addr_t ecc_base;
98 uint32_t ecc_version;
99 long vram_size, nvram_size;
100 // IRQ numbers are not PIL ones, but master interrupt controller
101 // register bit numbers
102 int esp_irq, le_irq, clock_irq, clock1_irq;
103 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
104 uint8_t nvram_machine_id;
105 uint16_t machine_id;
106 uint32_t iommu_version;
107 uint32_t intbit_to_level[32];
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint32_t intbit_to_level[32];
148 uint64_t max_mem;
149 const char * const default_cpu_model;
150 };
151
152 int DMA_get_channel_mode (int nchan)
153 {
154 return 0;
155 }
156 int DMA_read_memory (int nchan, void *buf, int pos, int size)
157 {
158 return 0;
159 }
160 int DMA_write_memory (int nchan, void *buf, int pos, int size)
161 {
162 return 0;
163 }
164 void DMA_hold_DREQ (int nchan) {}
165 void DMA_release_DREQ (int nchan) {}
166 void DMA_schedule(int nchan) {}
167 void DMA_init (int high_page_enable) {}
168 void DMA_register_channel (int nchan,
169 DMA_transfer_handler transfer_handler,
170 void *opaque)
171 {
172 }
173
174 static int nvram_boot_set(void *opaque, const char *boot_device)
175 {
176 unsigned int i;
177 uint8_t image[sizeof(ohwcfg_v3_t)];
178 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
179 m48t59_t *nvram = (m48t59_t *)opaque;
180
181 for (i = 0; i < sizeof(image); i++)
182 image[i] = m48t59_read(nvram, i) & 0xff;
183
184 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
185 boot_device);
186 header->nboot_devices = strlen(boot_device) & 0xff;
187 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
188
189 for (i = 0; i < sizeof(image); i++)
190 m48t59_write(nvram, i, image[i]);
191
192 return 0;
193 }
194
195 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
196 const char *boot_devices, ram_addr_t RAM_size,
197 uint32_t kernel_size,
198 int width, int height, int depth,
199 int nvram_machine_id, const char *arch)
200 {
201 unsigned int i;
202 uint32_t start, end;
203 uint8_t image[0x1ff0];
204 ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
205 struct sparc_arch_cfg *sparc_header;
206 struct OpenBIOS_nvpart_v1 *part_header;
207
208 memset(image, '\0', sizeof(image));
209
210 // Try to match PPC NVRAM
211 pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
212 "QEMU_BIOS");
213 header->struct_version = cpu_to_be32(3); /* structure v3 */
214
215 header->nvram_size = cpu_to_be16(0x2000);
216 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
217 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
218 pstrcpy((char *)header->arch, sizeof(header->arch), arch);
219 header->nb_cpus = smp_cpus & 0xff;
220 header->RAM0_base = 0;
221 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
222 pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
223 boot_devices);
224 header->nboot_devices = strlen(boot_devices) & 0xff;
225 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
226 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
227 if (cmdline) {
228 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
229 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
230 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
231 }
232 // XXX add initrd_image, initrd_size
233 header->width = cpu_to_be16(width);
234 header->height = cpu_to_be16(height);
235 header->depth = cpu_to_be16(depth);
236 if (nographic)
237 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
238
239 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
240
241 // Architecture specific header
242 start = sizeof(ohwcfg_v3_t);
243 sparc_header = (struct sparc_arch_cfg *)&image[start];
244 sparc_header->valid = 0;
245 start += sizeof(struct sparc_arch_cfg);
246
247 // OpenBIOS nvram variables
248 // Variable partition
249 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
250 part_header->signature = OPENBIOS_PART_SYSTEM;
251 pstrcpy(part_header->name, sizeof(part_header->name), "system");
252
253 end = start + sizeof(struct OpenBIOS_nvpart_v1);
254 for (i = 0; i < nb_prom_envs; i++)
255 end = OpenBIOS_set_var(image, end, prom_envs[i]);
256
257 // End marker
258 image[end++] = '\0';
259
260 end = start + ((end - start + 15) & ~15);
261 OpenBIOS_finish_partition(part_header, end - start);
262
263 // free partition
264 start = end;
265 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
266 part_header->signature = OPENBIOS_PART_FREE;
267 pstrcpy(part_header->name, sizeof(part_header->name), "free");
268
269 end = 0x1fd0;
270 OpenBIOS_finish_partition(part_header, end - start);
271
272 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
273 nvram_machine_id);
274
275 for (i = 0; i < sizeof(image); i++)
276 m48t59_write(nvram, i, image[i]);
277
278 qemu_register_boot_set(nvram_boot_set, nvram);
279 }
280
281 static void *slavio_intctl;
282
283 void pic_info(void)
284 {
285 if (slavio_intctl)
286 slavio_pic_info(slavio_intctl);
287 }
288
289 void irq_info(void)
290 {
291 if (slavio_intctl)
292 slavio_irq_info(slavio_intctl);
293 }
294
295 void cpu_check_irqs(CPUState *env)
296 {
297 if (env->pil_in && (env->interrupt_index == 0 ||
298 (env->interrupt_index & ~15) == TT_EXTINT)) {
299 unsigned int i;
300
301 for (i = 15; i > 0; i--) {
302 if (env->pil_in & (1 << i)) {
303 int old_interrupt = env->interrupt_index;
304
305 env->interrupt_index = TT_EXTINT | i;
306 if (old_interrupt != env->interrupt_index) {
307 DPRINTF("Set CPU IRQ %d\n", i);
308 cpu_interrupt(env, CPU_INTERRUPT_HARD);
309 }
310 break;
311 }
312 }
313 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
314 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
315 env->interrupt_index = 0;
316 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
317 }
318 }
319
320 static void cpu_set_irq(void *opaque, int irq, int level)
321 {
322 CPUState *env = opaque;
323
324 if (level) {
325 DPRINTF("Raise CPU IRQ %d\n", irq);
326 env->halted = 0;
327 env->pil_in |= 1 << irq;
328 cpu_check_irqs(env);
329 } else {
330 DPRINTF("Lower CPU IRQ %d\n", irq);
331 env->pil_in &= ~(1 << irq);
332 cpu_check_irqs(env);
333 }
334 }
335
336 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
337 {
338 }
339
340 static void *slavio_misc;
341
342 void qemu_system_powerdown(void)
343 {
344 slavio_set_power_fail(slavio_misc, 1);
345 }
346
347 static void main_cpu_reset(void *opaque)
348 {
349 CPUState *env = opaque;
350
351 cpu_reset(env);
352 env->halted = 0;
353 }
354
355 static void secondary_cpu_reset(void *opaque)
356 {
357 CPUState *env = opaque;
358
359 cpu_reset(env);
360 env->halted = 1;
361 }
362
363 static unsigned long sun4m_load_kernel(const char *kernel_filename,
364 const char *initrd_filename,
365 ram_addr_t RAM_size)
366 {
367 int linux_boot;
368 unsigned int i;
369 long initrd_size, kernel_size;
370
371 linux_boot = (kernel_filename != NULL);
372
373 kernel_size = 0;
374 if (linux_boot) {
375 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
376 NULL);
377 if (kernel_size < 0)
378 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
379 RAM_size - KERNEL_LOAD_ADDR);
380 if (kernel_size < 0)
381 kernel_size = load_image_targphys(kernel_filename,
382 KERNEL_LOAD_ADDR,
383 RAM_size - KERNEL_LOAD_ADDR);
384 if (kernel_size < 0) {
385 fprintf(stderr, "qemu: could not load kernel '%s'\n",
386 kernel_filename);
387 exit(1);
388 }
389
390 /* load initrd */
391 initrd_size = 0;
392 if (initrd_filename) {
393 initrd_size = load_image_targphys(initrd_filename,
394 INITRD_LOAD_ADDR,
395 RAM_size - INITRD_LOAD_ADDR);
396 if (initrd_size < 0) {
397 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
398 initrd_filename);
399 exit(1);
400 }
401 }
402 if (initrd_size > 0) {
403 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
404 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
405 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
406 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
407 break;
408 }
409 }
410 }
411 }
412 return kernel_size;
413 }
414
415 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
416 const char *boot_device,
417 DisplayState *ds, const char *kernel_filename,
418 const char *kernel_cmdline,
419 const char *initrd_filename, const char *cpu_model)
420
421 {
422 CPUState *env, *envs[MAX_CPUS];
423 unsigned int i;
424 void *iommu, *espdma, *ledma, *main_esp, *nvram;
425 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
426 *espdma_irq, *ledma_irq;
427 qemu_irq *esp_reset, *le_reset;
428 qemu_irq *fdc_tc;
429 unsigned long prom_offset, kernel_size;
430 int ret;
431 char buf[1024];
432 BlockDriverState *fd[MAX_FD];
433 int drive_index;
434 void *fw_cfg;
435
436 /* init CPUs */
437 if (!cpu_model)
438 cpu_model = hwdef->default_cpu_model;
439
440 for(i = 0; i < smp_cpus; i++) {
441 env = cpu_init(cpu_model);
442 if (!env) {
443 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
444 exit(1);
445 }
446 cpu_sparc_set_id(env, i);
447 envs[i] = env;
448 if (i == 0) {
449 qemu_register_reset(main_cpu_reset, env);
450 } else {
451 qemu_register_reset(secondary_cpu_reset, env);
452 env->halted = 1;
453 }
454 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
455 env->prom_addr = hwdef->slavio_base;
456 }
457
458 for (i = smp_cpus; i < MAX_CPUS; i++)
459 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
460
461
462 /* allocate RAM */
463 if ((uint64_t)RAM_size > hwdef->max_mem) {
464 fprintf(stderr,
465 "qemu: Too much memory for this machine: %d, maximum %d\n",
466 (unsigned int)(RAM_size / (1024 * 1024)),
467 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
468 exit(1);
469 }
470 cpu_register_physical_memory(0, RAM_size, 0);
471
472 /* load boot prom */
473 prom_offset = RAM_size + hwdef->vram_size;
474 cpu_register_physical_memory(hwdef->slavio_base,
475 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
476 TARGET_PAGE_MASK,
477 prom_offset | IO_MEM_ROM);
478
479 if (bios_name == NULL)
480 bios_name = PROM_FILENAME;
481 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
482 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
483 if (ret < 0 || ret > PROM_SIZE_MAX)
484 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
485 if (ret < 0 || ret > PROM_SIZE_MAX) {
486 fprintf(stderr, "qemu: could not load prom '%s'\n",
487 buf);
488 exit(1);
489 }
490 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
491
492 /* set up devices */
493 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
494 hwdef->intctl_base + 0x10000ULL,
495 &hwdef->intbit_to_level[0],
496 &slavio_irq, &slavio_cpu_irq,
497 cpu_irqs,
498 hwdef->clock_irq);
499
500 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
501 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
502
503 cpu_register_physical_memory(hwdef->idreg_base, sizeof(idreg_data),
504 prom_offset | IO_MEM_ROM);
505 cpu_physical_memory_write_rom(hwdef->idreg_base, idreg_data,
506 sizeof(idreg_data));
507 }
508
509 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
510 slavio_irq[hwdef->me_irq]);
511
512 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
513 iommu, &espdma_irq, &esp_reset);
514
515 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
516 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
517 &le_reset);
518
519 if (graphic_depth != 8 && graphic_depth != 24) {
520 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
521 exit (1);
522 }
523 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
524 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
525
526 if (nd_table[0].model == NULL
527 || strcmp(nd_table[0].model, "lance") == 0) {
528 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
529 } else if (strcmp(nd_table[0].model, "?") == 0) {
530 fprintf(stderr, "qemu: Supported NICs: lance\n");
531 exit (1);
532 } else {
533 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
534 exit (1);
535 }
536
537 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
538 hwdef->nvram_size, 8);
539
540 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
541 slavio_cpu_irq, smp_cpus);
542
543 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
544 nographic);
545 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
546 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
547 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
548 serial_hds[1], serial_hds[0]);
549
550 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
551 hwdef->aux1_base, hwdef->aux2_base,
552 slavio_irq[hwdef->me_irq], envs[0],
553 &fdc_tc);
554
555 if (hwdef->fd_base != (target_phys_addr_t)-1) {
556 /* there is zero or one floppy drive */
557 memset(fd, 0, sizeof(fd));
558 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
559 if (drive_index != -1)
560 fd[0] = drives_table[drive_index].bdrv;
561
562 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
563 fdc_tc);
564 }
565
566 if (drive_get_max_bus(IF_SCSI) > 0) {
567 fprintf(stderr, "qemu: too many SCSI bus\n");
568 exit(1);
569 }
570
571 main_esp = esp_init(hwdef->esp_base, 2,
572 espdma_memory_read, espdma_memory_write,
573 espdma, *espdma_irq, esp_reset);
574
575 for (i = 0; i < ESP_MAX_DEVS; i++) {
576 drive_index = drive_get_index(IF_SCSI, 0, i);
577 if (drive_index == -1)
578 continue;
579 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
580 }
581
582 if (hwdef->cs_base != (target_phys_addr_t)-1)
583 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
584
585 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
586 RAM_size);
587
588 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
589 boot_device, RAM_size, kernel_size, graphic_width,
590 graphic_height, graphic_depth, hwdef->nvram_machine_id,
591 "Sun4m");
592
593 if (hwdef->ecc_base != (target_phys_addr_t)-1)
594 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
595 hwdef->ecc_version);
596
597 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
598 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
599 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
600 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
601 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
602 }
603
604 enum {
605 ss2_id = 0,
606 ss5_id = 32,
607 vger_id,
608 lx_id,
609 ss4_id,
610 scls_id,
611 sbook_id,
612 ss10_id = 64,
613 ss20_id,
614 ss600mp_id,
615 ss1000_id = 96,
616 ss2000_id,
617 };
618
619 static const struct sun4m_hwdef sun4m_hwdefs[] = {
620 /* SS-5 */
621 {
622 .iommu_base = 0x10000000,
623 .tcx_base = 0x50000000,
624 .cs_base = 0x6c000000,
625 .slavio_base = 0x70000000,
626 .ms_kb_base = 0x71000000,
627 .serial_base = 0x71100000,
628 .nvram_base = 0x71200000,
629 .fd_base = 0x71400000,
630 .counter_base = 0x71d00000,
631 .intctl_base = 0x71e00000,
632 .idreg_base = 0x78000000,
633 .dma_base = 0x78400000,
634 .esp_base = 0x78800000,
635 .le_base = 0x78c00000,
636 .apc_base = 0x6a000000,
637 .aux1_base = 0x71900000,
638 .aux2_base = 0x71910000,
639 .ecc_base = -1,
640 .vram_size = 0x00100000,
641 .nvram_size = 0x2000,
642 .esp_irq = 18,
643 .le_irq = 16,
644 .clock_irq = 7,
645 .clock1_irq = 19,
646 .ms_kb_irq = 14,
647 .ser_irq = 15,
648 .fd_irq = 22,
649 .me_irq = 30,
650 .cs_irq = 5,
651 .nvram_machine_id = 0x80,
652 .machine_id = ss5_id,
653 .iommu_version = 0x05000000,
654 .intbit_to_level = {
655 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
656 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
657 },
658 .max_mem = 0x10000000,
659 .default_cpu_model = "Fujitsu MB86904",
660 },
661 /* SS-10 */
662 {
663 .iommu_base = 0xfe0000000ULL,
664 .tcx_base = 0xe20000000ULL,
665 .cs_base = -1,
666 .slavio_base = 0xff0000000ULL,
667 .ms_kb_base = 0xff1000000ULL,
668 .serial_base = 0xff1100000ULL,
669 .nvram_base = 0xff1200000ULL,
670 .fd_base = 0xff1700000ULL,
671 .counter_base = 0xff1300000ULL,
672 .intctl_base = 0xff1400000ULL,
673 .idreg_base = 0xef0000000ULL,
674 .dma_base = 0xef0400000ULL,
675 .esp_base = 0xef0800000ULL,
676 .le_base = 0xef0c00000ULL,
677 .apc_base = 0xefa000000ULL, // XXX should not exist
678 .aux1_base = 0xff1800000ULL,
679 .aux2_base = 0xff1a01000ULL,
680 .ecc_base = 0xf00000000ULL,
681 .ecc_version = 0x10000000, // version 0, implementation 1
682 .vram_size = 0x00100000,
683 .nvram_size = 0x2000,
684 .esp_irq = 18,
685 .le_irq = 16,
686 .clock_irq = 7,
687 .clock1_irq = 19,
688 .ms_kb_irq = 14,
689 .ser_irq = 15,
690 .fd_irq = 22,
691 .me_irq = 30,
692 .cs_irq = -1,
693 .ecc_irq = 28,
694 .nvram_machine_id = 0x72,
695 .machine_id = ss10_id,
696 .iommu_version = 0x03000000,
697 .intbit_to_level = {
698 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
699 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
700 },
701 .max_mem = 0xf00000000ULL,
702 .default_cpu_model = "TI SuperSparc II",
703 },
704 /* SS-600MP */
705 {
706 .iommu_base = 0xfe0000000ULL,
707 .tcx_base = 0xe20000000ULL,
708 .cs_base = -1,
709 .slavio_base = 0xff0000000ULL,
710 .ms_kb_base = 0xff1000000ULL,
711 .serial_base = 0xff1100000ULL,
712 .nvram_base = 0xff1200000ULL,
713 .fd_base = -1,
714 .counter_base = 0xff1300000ULL,
715 .intctl_base = 0xff1400000ULL,
716 .idreg_base = -1,
717 .dma_base = 0xef0081000ULL,
718 .esp_base = 0xef0080000ULL,
719 .le_base = 0xef0060000ULL,
720 .apc_base = 0xefa000000ULL, // XXX should not exist
721 .aux1_base = 0xff1800000ULL,
722 .aux2_base = 0xff1a01000ULL, // XXX should not exist
723 .ecc_base = 0xf00000000ULL,
724 .ecc_version = 0x00000000, // version 0, implementation 0
725 .vram_size = 0x00100000,
726 .nvram_size = 0x2000,
727 .esp_irq = 18,
728 .le_irq = 16,
729 .clock_irq = 7,
730 .clock1_irq = 19,
731 .ms_kb_irq = 14,
732 .ser_irq = 15,
733 .fd_irq = 22,
734 .me_irq = 30,
735 .cs_irq = -1,
736 .ecc_irq = 28,
737 .nvram_machine_id = 0x71,
738 .machine_id = ss600mp_id,
739 .iommu_version = 0x01000000,
740 .intbit_to_level = {
741 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
742 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
743 },
744 .max_mem = 0xf00000000ULL,
745 .default_cpu_model = "TI SuperSparc II",
746 },
747 /* SS-20 */
748 {
749 .iommu_base = 0xfe0000000ULL,
750 .tcx_base = 0xe20000000ULL,
751 .cs_base = -1,
752 .slavio_base = 0xff0000000ULL,
753 .ms_kb_base = 0xff1000000ULL,
754 .serial_base = 0xff1100000ULL,
755 .nvram_base = 0xff1200000ULL,
756 .fd_base = 0xff1700000ULL,
757 .counter_base = 0xff1300000ULL,
758 .intctl_base = 0xff1400000ULL,
759 .idreg_base = 0xef0000000ULL,
760 .dma_base = 0xef0400000ULL,
761 .esp_base = 0xef0800000ULL,
762 .le_base = 0xef0c00000ULL,
763 .apc_base = 0xefa000000ULL, // XXX should not exist
764 .aux1_base = 0xff1800000ULL,
765 .aux2_base = 0xff1a01000ULL,
766 .ecc_base = 0xf00000000ULL,
767 .ecc_version = 0x20000000, // version 0, implementation 2
768 .vram_size = 0x00100000,
769 .nvram_size = 0x2000,
770 .esp_irq = 18,
771 .le_irq = 16,
772 .clock_irq = 7,
773 .clock1_irq = 19,
774 .ms_kb_irq = 14,
775 .ser_irq = 15,
776 .fd_irq = 22,
777 .me_irq = 30,
778 .cs_irq = -1,
779 .ecc_irq = 28,
780 .nvram_machine_id = 0x72,
781 .machine_id = ss20_id,
782 .iommu_version = 0x13000000,
783 .intbit_to_level = {
784 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
785 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
786 },
787 .max_mem = 0xf00000000ULL,
788 .default_cpu_model = "TI SuperSparc II",
789 },
790 /* Voyager */
791 {
792 .iommu_base = 0x10000000,
793 .tcx_base = 0x50000000,
794 .cs_base = -1,
795 .slavio_base = 0x70000000,
796 .ms_kb_base = 0x71000000,
797 .serial_base = 0x71100000,
798 .nvram_base = 0x71200000,
799 .fd_base = 0x71400000,
800 .counter_base = 0x71d00000,
801 .intctl_base = 0x71e00000,
802 .idreg_base = 0x78000000,
803 .dma_base = 0x78400000,
804 .esp_base = 0x78800000,
805 .le_base = 0x78c00000,
806 .apc_base = 0x71300000, // pmc
807 .aux1_base = 0x71900000,
808 .aux2_base = 0x71910000,
809 .ecc_base = -1,
810 .vram_size = 0x00100000,
811 .nvram_size = 0x2000,
812 .esp_irq = 18,
813 .le_irq = 16,
814 .clock_irq = 7,
815 .clock1_irq = 19,
816 .ms_kb_irq = 14,
817 .ser_irq = 15,
818 .fd_irq = 22,
819 .me_irq = 30,
820 .cs_irq = -1,
821 .nvram_machine_id = 0x80,
822 .machine_id = vger_id,
823 .iommu_version = 0x05000000,
824 .intbit_to_level = {
825 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
826 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
827 },
828 .max_mem = 0x10000000,
829 .default_cpu_model = "Fujitsu MB86904",
830 },
831 /* LX */
832 {
833 .iommu_base = 0x10000000,
834 .tcx_base = 0x50000000,
835 .cs_base = -1,
836 .slavio_base = 0x70000000,
837 .ms_kb_base = 0x71000000,
838 .serial_base = 0x71100000,
839 .nvram_base = 0x71200000,
840 .fd_base = 0x71400000,
841 .counter_base = 0x71d00000,
842 .intctl_base = 0x71e00000,
843 .idreg_base = 0x78000000,
844 .dma_base = 0x78400000,
845 .esp_base = 0x78800000,
846 .le_base = 0x78c00000,
847 .apc_base = -1,
848 .aux1_base = 0x71900000,
849 .aux2_base = 0x71910000,
850 .ecc_base = -1,
851 .vram_size = 0x00100000,
852 .nvram_size = 0x2000,
853 .esp_irq = 18,
854 .le_irq = 16,
855 .clock_irq = 7,
856 .clock1_irq = 19,
857 .ms_kb_irq = 14,
858 .ser_irq = 15,
859 .fd_irq = 22,
860 .me_irq = 30,
861 .cs_irq = -1,
862 .nvram_machine_id = 0x80,
863 .machine_id = lx_id,
864 .iommu_version = 0x04000000,
865 .intbit_to_level = {
866 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
867 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
868 },
869 .max_mem = 0x10000000,
870 .default_cpu_model = "TI MicroSparc I",
871 },
872 /* SS-4 */
873 {
874 .iommu_base = 0x10000000,
875 .tcx_base = 0x50000000,
876 .cs_base = 0x6c000000,
877 .slavio_base = 0x70000000,
878 .ms_kb_base = 0x71000000,
879 .serial_base = 0x71100000,
880 .nvram_base = 0x71200000,
881 .fd_base = 0x71400000,
882 .counter_base = 0x71d00000,
883 .intctl_base = 0x71e00000,
884 .idreg_base = 0x78000000,
885 .dma_base = 0x78400000,
886 .esp_base = 0x78800000,
887 .le_base = 0x78c00000,
888 .apc_base = 0x6a000000,
889 .aux1_base = 0x71900000,
890 .aux2_base = 0x71910000,
891 .ecc_base = -1,
892 .vram_size = 0x00100000,
893 .nvram_size = 0x2000,
894 .esp_irq = 18,
895 .le_irq = 16,
896 .clock_irq = 7,
897 .clock1_irq = 19,
898 .ms_kb_irq = 14,
899 .ser_irq = 15,
900 .fd_irq = 22,
901 .me_irq = 30,
902 .cs_irq = 5,
903 .nvram_machine_id = 0x80,
904 .machine_id = ss4_id,
905 .iommu_version = 0x05000000,
906 .intbit_to_level = {
907 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
908 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
909 },
910 .max_mem = 0x10000000,
911 .default_cpu_model = "Fujitsu MB86904",
912 },
913 /* SPARCClassic */
914 {
915 .iommu_base = 0x10000000,
916 .tcx_base = 0x50000000,
917 .cs_base = -1,
918 .slavio_base = 0x70000000,
919 .ms_kb_base = 0x71000000,
920 .serial_base = 0x71100000,
921 .nvram_base = 0x71200000,
922 .fd_base = 0x71400000,
923 .counter_base = 0x71d00000,
924 .intctl_base = 0x71e00000,
925 .idreg_base = 0x78000000,
926 .dma_base = 0x78400000,
927 .esp_base = 0x78800000,
928 .le_base = 0x78c00000,
929 .apc_base = 0x6a000000,
930 .aux1_base = 0x71900000,
931 .aux2_base = 0x71910000,
932 .ecc_base = -1,
933 .vram_size = 0x00100000,
934 .nvram_size = 0x2000,
935 .esp_irq = 18,
936 .le_irq = 16,
937 .clock_irq = 7,
938 .clock1_irq = 19,
939 .ms_kb_irq = 14,
940 .ser_irq = 15,
941 .fd_irq = 22,
942 .me_irq = 30,
943 .cs_irq = -1,
944 .nvram_machine_id = 0x80,
945 .machine_id = scls_id,
946 .iommu_version = 0x05000000,
947 .intbit_to_level = {
948 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
949 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
950 },
951 .max_mem = 0x10000000,
952 .default_cpu_model = "TI MicroSparc I",
953 },
954 /* SPARCbook */
955 {
956 .iommu_base = 0x10000000,
957 .tcx_base = 0x50000000, // XXX
958 .cs_base = -1,
959 .slavio_base = 0x70000000,
960 .ms_kb_base = 0x71000000,
961 .serial_base = 0x71100000,
962 .nvram_base = 0x71200000,
963 .fd_base = 0x71400000,
964 .counter_base = 0x71d00000,
965 .intctl_base = 0x71e00000,
966 .idreg_base = 0x78000000,
967 .dma_base = 0x78400000,
968 .esp_base = 0x78800000,
969 .le_base = 0x78c00000,
970 .apc_base = 0x6a000000,
971 .aux1_base = 0x71900000,
972 .aux2_base = 0x71910000,
973 .ecc_base = -1,
974 .vram_size = 0x00100000,
975 .nvram_size = 0x2000,
976 .esp_irq = 18,
977 .le_irq = 16,
978 .clock_irq = 7,
979 .clock1_irq = 19,
980 .ms_kb_irq = 14,
981 .ser_irq = 15,
982 .fd_irq = 22,
983 .me_irq = 30,
984 .cs_irq = -1,
985 .nvram_machine_id = 0x80,
986 .machine_id = sbook_id,
987 .iommu_version = 0x05000000,
988 .intbit_to_level = {
989 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
990 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
991 },
992 .max_mem = 0x10000000,
993 .default_cpu_model = "TI MicroSparc I",
994 },
995 };
996
997 /* SPARCstation 5 hardware initialisation */
998 static void ss5_init(ram_addr_t RAM_size, int vga_ram_size,
999 const char *boot_device, DisplayState *ds,
1000 const char *kernel_filename, const char *kernel_cmdline,
1001 const char *initrd_filename, const char *cpu_model)
1002 {
1003 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1004 kernel_cmdline, initrd_filename, cpu_model);
1005 }
1006
1007 /* SPARCstation 10 hardware initialisation */
1008 static void ss10_init(ram_addr_t RAM_size, int vga_ram_size,
1009 const char *boot_device, DisplayState *ds,
1010 const char *kernel_filename, const char *kernel_cmdline,
1011 const char *initrd_filename, const char *cpu_model)
1012 {
1013 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1014 kernel_cmdline, initrd_filename, cpu_model);
1015 }
1016
1017 /* SPARCserver 600MP hardware initialisation */
1018 static void ss600mp_init(ram_addr_t RAM_size, int vga_ram_size,
1019 const char *boot_device, DisplayState *ds,
1020 const char *kernel_filename,
1021 const char *kernel_cmdline,
1022 const char *initrd_filename, const char *cpu_model)
1023 {
1024 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
1025 kernel_cmdline, initrd_filename, cpu_model);
1026 }
1027
1028 /* SPARCstation 20 hardware initialisation */
1029 static void ss20_init(ram_addr_t RAM_size, int vga_ram_size,
1030 const char *boot_device, DisplayState *ds,
1031 const char *kernel_filename, const char *kernel_cmdline,
1032 const char *initrd_filename, const char *cpu_model)
1033 {
1034 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
1035 kernel_cmdline, initrd_filename, cpu_model);
1036 }
1037
1038 /* SPARCstation Voyager hardware initialisation */
1039 static void vger_init(ram_addr_t RAM_size, int vga_ram_size,
1040 const char *boot_device, DisplayState *ds,
1041 const char *kernel_filename, const char *kernel_cmdline,
1042 const char *initrd_filename, const char *cpu_model)
1043 {
1044 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
1045 kernel_cmdline, initrd_filename, cpu_model);
1046 }
1047
1048 /* SPARCstation LX hardware initialisation */
1049 static void ss_lx_init(ram_addr_t RAM_size, int vga_ram_size,
1050 const char *boot_device, DisplayState *ds,
1051 const char *kernel_filename, const char *kernel_cmdline,
1052 const char *initrd_filename, const char *cpu_model)
1053 {
1054 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, ds, kernel_filename,
1055 kernel_cmdline, initrd_filename, cpu_model);
1056 }
1057
1058 /* SPARCstation 4 hardware initialisation */
1059 static void ss4_init(ram_addr_t RAM_size, int vga_ram_size,
1060 const char *boot_device, DisplayState *ds,
1061 const char *kernel_filename, const char *kernel_cmdline,
1062 const char *initrd_filename, const char *cpu_model)
1063 {
1064 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, ds, kernel_filename,
1065 kernel_cmdline, initrd_filename, cpu_model);
1066 }
1067
1068 /* SPARCClassic hardware initialisation */
1069 static void scls_init(ram_addr_t RAM_size, int vga_ram_size,
1070 const char *boot_device, DisplayState *ds,
1071 const char *kernel_filename, const char *kernel_cmdline,
1072 const char *initrd_filename, const char *cpu_model)
1073 {
1074 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, ds, kernel_filename,
1075 kernel_cmdline, initrd_filename, cpu_model);
1076 }
1077
1078 /* SPARCbook hardware initialisation */
1079 static void sbook_init(ram_addr_t RAM_size, int vga_ram_size,
1080 const char *boot_device, DisplayState *ds,
1081 const char *kernel_filename, const char *kernel_cmdline,
1082 const char *initrd_filename, const char *cpu_model)
1083 {
1084 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, ds, kernel_filename,
1085 kernel_cmdline, initrd_filename, cpu_model);
1086 }
1087
1088 QEMUMachine ss5_machine = {
1089 .name = "SS-5",
1090 .desc = "Sun4m platform, SPARCstation 5",
1091 .init = ss5_init,
1092 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1093 .nodisk_ok = 1,
1094 .use_scsi = 1,
1095 .max_cpus = 16,
1096 };
1097
1098 QEMUMachine ss10_machine = {
1099 .name = "SS-10",
1100 .desc = "Sun4m platform, SPARCstation 10",
1101 .init = ss10_init,
1102 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1103 .nodisk_ok = 1,
1104 .use_scsi = 1,
1105 .max_cpus = 16,
1106 };
1107
1108 QEMUMachine ss600mp_machine = {
1109 .name = "SS-600MP",
1110 .desc = "Sun4m platform, SPARCserver 600MP",
1111 .init = ss600mp_init,
1112 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1113 .nodisk_ok = 1,
1114 .use_scsi = 1,
1115 .max_cpus = 16,
1116 };
1117
1118 QEMUMachine ss20_machine = {
1119 .name = "SS-20",
1120 .desc = "Sun4m platform, SPARCstation 20",
1121 .init = ss20_init,
1122 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1123 .nodisk_ok = 1,
1124 .use_scsi = 1,
1125 .max_cpus = 16,
1126 };
1127
1128 QEMUMachine voyager_machine = {
1129 .name = "Voyager",
1130 .desc = "Sun4m platform, SPARCstation Voyager",
1131 .init = vger_init,
1132 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1133 .nodisk_ok = 1,
1134 .use_scsi = 1,
1135 .max_cpus = 16,
1136 };
1137
1138 QEMUMachine ss_lx_machine = {
1139 .name = "LX",
1140 .desc = "Sun4m platform, SPARCstation LX",
1141 .init = ss_lx_init,
1142 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1143 .nodisk_ok = 1,
1144 .use_scsi = 1,
1145 .max_cpus = 16,
1146 };
1147
1148 QEMUMachine ss4_machine = {
1149 .name = "SS-4",
1150 .desc = "Sun4m platform, SPARCstation 4",
1151 .init = ss4_init,
1152 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1153 .nodisk_ok = 1,
1154 .use_scsi = 1,
1155 .max_cpus = 16,
1156 };
1157
1158 QEMUMachine scls_machine = {
1159 .name = "SPARCClassic",
1160 .desc = "Sun4m platform, SPARCClassic",
1161 .init = scls_init,
1162 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1163 .nodisk_ok = 1,
1164 .use_scsi = 1,
1165 .max_cpus = 16,
1166 };
1167
1168 QEMUMachine sbook_machine = {
1169 .name = "SPARCbook",
1170 .desc = "Sun4m platform, SPARCbook",
1171 .init = sbook_init,
1172 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1173 .nodisk_ok = 1,
1174 .use_scsi = 1,
1175 .max_cpus = 16,
1176 };
1177
1178 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1179 /* SS-1000 */
1180 {
1181 .iounit_bases = {
1182 0xfe0200000ULL,
1183 0xfe1200000ULL,
1184 0xfe2200000ULL,
1185 0xfe3200000ULL,
1186 -1,
1187 },
1188 .tcx_base = 0x820000000ULL,
1189 .slavio_base = 0xf00000000ULL,
1190 .ms_kb_base = 0xf00240000ULL,
1191 .serial_base = 0xf00200000ULL,
1192 .nvram_base = 0xf00280000ULL,
1193 .counter_base = 0xf00300000ULL,
1194 .espdma_base = 0x800081000ULL,
1195 .esp_base = 0x800080000ULL,
1196 .ledma_base = 0x800040000ULL,
1197 .le_base = 0x800060000ULL,
1198 .sbi_base = 0xf02800000ULL,
1199 .vram_size = 0x00100000,
1200 .nvram_size = 0x2000,
1201 .esp_irq = 3,
1202 .le_irq = 4,
1203 .clock_irq = 14,
1204 .clock1_irq = 10,
1205 .ms_kb_irq = 12,
1206 .ser_irq = 12,
1207 .nvram_machine_id = 0x80,
1208 .machine_id = ss1000_id,
1209 .iounit_version = 0x03000000,
1210 .max_mem = 0xf00000000ULL,
1211 .default_cpu_model = "TI SuperSparc II",
1212 },
1213 /* SS-2000 */
1214 {
1215 .iounit_bases = {
1216 0xfe0200000ULL,
1217 0xfe1200000ULL,
1218 0xfe2200000ULL,
1219 0xfe3200000ULL,
1220 0xfe4200000ULL,
1221 },
1222 .tcx_base = 0x820000000ULL,
1223 .slavio_base = 0xf00000000ULL,
1224 .ms_kb_base = 0xf00240000ULL,
1225 .serial_base = 0xf00200000ULL,
1226 .nvram_base = 0xf00280000ULL,
1227 .counter_base = 0xf00300000ULL,
1228 .espdma_base = 0x800081000ULL,
1229 .esp_base = 0x800080000ULL,
1230 .ledma_base = 0x800040000ULL,
1231 .le_base = 0x800060000ULL,
1232 .sbi_base = 0xf02800000ULL,
1233 .vram_size = 0x00100000,
1234 .nvram_size = 0x2000,
1235 .esp_irq = 3,
1236 .le_irq = 4,
1237 .clock_irq = 14,
1238 .clock1_irq = 10,
1239 .ms_kb_irq = 12,
1240 .ser_irq = 12,
1241 .nvram_machine_id = 0x80,
1242 .machine_id = ss2000_id,
1243 .iounit_version = 0x03000000,
1244 .max_mem = 0xf00000000ULL,
1245 .default_cpu_model = "TI SuperSparc II",
1246 },
1247 };
1248
1249 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1250 const char *boot_device,
1251 DisplayState *ds, const char *kernel_filename,
1252 const char *kernel_cmdline,
1253 const char *initrd_filename, const char *cpu_model)
1254 {
1255 CPUState *env, *envs[MAX_CPUS];
1256 unsigned int i;
1257 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1258 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1259 *espdma_irq, *ledma_irq;
1260 qemu_irq *esp_reset, *le_reset;
1261 unsigned long prom_offset, kernel_size;
1262 int ret;
1263 char buf[1024];
1264 int drive_index;
1265 void *fw_cfg;
1266
1267 /* init CPUs */
1268 if (!cpu_model)
1269 cpu_model = hwdef->default_cpu_model;
1270
1271 for (i = 0; i < smp_cpus; i++) {
1272 env = cpu_init(cpu_model);
1273 if (!env) {
1274 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1275 exit(1);
1276 }
1277 cpu_sparc_set_id(env, i);
1278 envs[i] = env;
1279 if (i == 0) {
1280 qemu_register_reset(main_cpu_reset, env);
1281 } else {
1282 qemu_register_reset(secondary_cpu_reset, env);
1283 env->halted = 1;
1284 }
1285 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1286 env->prom_addr = hwdef->slavio_base;
1287 }
1288
1289 for (i = smp_cpus; i < MAX_CPUS; i++)
1290 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1291
1292 /* allocate RAM */
1293 if ((uint64_t)RAM_size > hwdef->max_mem) {
1294 fprintf(stderr,
1295 "qemu: Too much memory for this machine: %d, maximum %d\n",
1296 (unsigned int)(RAM_size / (1024 * 1024)),
1297 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1298 exit(1);
1299 }
1300 cpu_register_physical_memory(0, RAM_size, 0);
1301
1302 /* load boot prom */
1303 prom_offset = RAM_size + hwdef->vram_size;
1304 cpu_register_physical_memory(hwdef->slavio_base,
1305 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1306 TARGET_PAGE_MASK,
1307 prom_offset | IO_MEM_ROM);
1308
1309 if (bios_name == NULL)
1310 bios_name = PROM_FILENAME;
1311 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1312 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1313 if (ret < 0 || ret > PROM_SIZE_MAX)
1314 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1315 if (ret < 0 || ret > PROM_SIZE_MAX) {
1316 fprintf(stderr, "qemu: could not load prom '%s'\n",
1317 buf);
1318 exit(1);
1319 }
1320
1321 /* set up devices */
1322 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1323
1324 for (i = 0; i < MAX_IOUNITS; i++)
1325 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1326 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1327 hwdef->iounit_version,
1328 sbi_irq[hwdef->me_irq]);
1329
1330 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1331 iounits[0], &espdma_irq, &esp_reset);
1332
1333 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1334 iounits[0], &ledma_irq, &le_reset);
1335
1336 if (graphic_depth != 8 && graphic_depth != 24) {
1337 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1338 exit (1);
1339 }
1340 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1341 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1342
1343 if (nd_table[0].model == NULL
1344 || strcmp(nd_table[0].model, "lance") == 0) {
1345 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1346 } else if (strcmp(nd_table[0].model, "?") == 0) {
1347 fprintf(stderr, "qemu: Supported NICs: lance\n");
1348 exit (1);
1349 } else {
1350 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1351 exit (1);
1352 }
1353
1354 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1355 hwdef->nvram_size, 8);
1356
1357 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1358 sbi_cpu_irq, smp_cpus);
1359
1360 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1361 nographic);
1362 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1363 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1364 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1365 serial_hds[1], serial_hds[0]);
1366
1367 if (drive_get_max_bus(IF_SCSI) > 0) {
1368 fprintf(stderr, "qemu: too many SCSI bus\n");
1369 exit(1);
1370 }
1371
1372 main_esp = esp_init(hwdef->esp_base, 2,
1373 espdma_memory_read, espdma_memory_write,
1374 espdma, *espdma_irq, esp_reset);
1375
1376 for (i = 0; i < ESP_MAX_DEVS; i++) {
1377 drive_index = drive_get_index(IF_SCSI, 0, i);
1378 if (drive_index == -1)
1379 continue;
1380 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1381 }
1382
1383 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1384 RAM_size);
1385
1386 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1387 boot_device, RAM_size, kernel_size, graphic_width,
1388 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1389 "Sun4d");
1390
1391 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1392 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1393 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1394 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1395 }
1396
1397 /* SPARCserver 1000 hardware initialisation */
1398 static void ss1000_init(ram_addr_t RAM_size, int vga_ram_size,
1399 const char *boot_device, DisplayState *ds,
1400 const char *kernel_filename, const char *kernel_cmdline,
1401 const char *initrd_filename, const char *cpu_model)
1402 {
1403 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1404 kernel_cmdline, initrd_filename, cpu_model);
1405 }
1406
1407 /* SPARCcenter 2000 hardware initialisation */
1408 static void ss2000_init(ram_addr_t RAM_size, int vga_ram_size,
1409 const char *boot_device, DisplayState *ds,
1410 const char *kernel_filename, const char *kernel_cmdline,
1411 const char *initrd_filename, const char *cpu_model)
1412 {
1413 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1414 kernel_cmdline, initrd_filename, cpu_model);
1415 }
1416
1417 QEMUMachine ss1000_machine = {
1418 .name = "SS-1000",
1419 .desc = "Sun4d platform, SPARCserver 1000",
1420 .init = ss1000_init,
1421 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1422 .nodisk_ok = 1,
1423 .use_scsi = 1,
1424 .max_cpus = 16,
1425 };
1426
1427 QEMUMachine ss2000_machine = {
1428 .name = "SS-2000",
1429 .desc = "Sun4d platform, SPARCcenter 2000",
1430 .init = ss2000_init,
1431 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1432 .nodisk_ok = 1,
1433 .use_scsi = 1,
1434 .max_cpus = 16,
1435 };
1436
1437 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1438 /* SS-2 */
1439 {
1440 .iommu_base = 0xf8000000,
1441 .tcx_base = 0xfe000000,
1442 .slavio_base = 0xf6000000,
1443 .intctl_base = 0xf5000000,
1444 .counter_base = 0xf3000000,
1445 .ms_kb_base = 0xf0000000,
1446 .serial_base = 0xf1000000,
1447 .nvram_base = 0xf2000000,
1448 .fd_base = 0xf7200000,
1449 .dma_base = 0xf8400000,
1450 .esp_base = 0xf8800000,
1451 .le_base = 0xf8c00000,
1452 .aux1_base = 0xf7400003,
1453 .vram_size = 0x00100000,
1454 .nvram_size = 0x800,
1455 .esp_irq = 2,
1456 .le_irq = 3,
1457 .clock_irq = 5,
1458 .clock1_irq = 7,
1459 .ms_kb_irq = 1,
1460 .ser_irq = 1,
1461 .fd_irq = 1,
1462 .me_irq = 1,
1463 .nvram_machine_id = 0x55,
1464 .machine_id = ss2_id,
1465 .max_mem = 0x10000000,
1466 .default_cpu_model = "Cypress CY7C601",
1467 },
1468 };
1469
1470 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1471 const char *boot_device,
1472 DisplayState *ds, const char *kernel_filename,
1473 const char *kernel_cmdline,
1474 const char *initrd_filename, const char *cpu_model)
1475 {
1476 CPUState *env;
1477 unsigned int i;
1478 void *iommu, *espdma, *ledma, *main_esp, *nvram;
1479 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
1480 qemu_irq *esp_reset, *le_reset;
1481 qemu_irq *fdc_tc;
1482 unsigned long prom_offset, kernel_size;
1483 int ret;
1484 char buf[1024];
1485 BlockDriverState *fd[MAX_FD];
1486 int drive_index;
1487 void *fw_cfg;
1488
1489 /* init CPU */
1490 if (!cpu_model)
1491 cpu_model = hwdef->default_cpu_model;
1492
1493 env = cpu_init(cpu_model);
1494 if (!env) {
1495 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1496 exit(1);
1497 }
1498
1499 cpu_sparc_set_id(env, 0);
1500
1501 qemu_register_reset(main_cpu_reset, env);
1502 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
1503 env->prom_addr = hwdef->slavio_base;
1504
1505 /* allocate RAM */
1506 if ((uint64_t)RAM_size > hwdef->max_mem) {
1507 fprintf(stderr,
1508 "qemu: Too much memory for this machine: %d, maximum %d\n",
1509 (unsigned int)(RAM_size / (1024 * 1024)),
1510 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1511 exit(1);
1512 }
1513 cpu_register_physical_memory(0, RAM_size, 0);
1514
1515 /* load boot prom */
1516 prom_offset = RAM_size + hwdef->vram_size;
1517 cpu_register_physical_memory(hwdef->slavio_base,
1518 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1519 TARGET_PAGE_MASK,
1520 prom_offset | IO_MEM_ROM);
1521
1522 if (bios_name == NULL)
1523 bios_name = PROM_FILENAME;
1524 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1525 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1526 if (ret < 0 || ret > PROM_SIZE_MAX)
1527 ret = load_image_targphys(buf, hwdef->slavio_base, PROM_SIZE_MAX);
1528 if (ret < 0 || ret > PROM_SIZE_MAX) {
1529 fprintf(stderr, "qemu: could not load prom '%s'\n",
1530 buf);
1531 exit(1);
1532 }
1533 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
1534
1535 /* set up devices */
1536 slavio_intctl = sun4c_intctl_init(hwdef->intctl_base,
1537 &slavio_irq, cpu_irqs);
1538
1539 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1540 slavio_irq[hwdef->me_irq]);
1541
1542 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1543 iommu, &espdma_irq, &esp_reset);
1544
1545 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1546 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1547 &le_reset);
1548
1549 if (graphic_depth != 8 && graphic_depth != 24) {
1550 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1551 exit (1);
1552 }
1553 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1554 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1555
1556 if (nd_table[0].model == NULL
1557 || strcmp(nd_table[0].model, "lance") == 0) {
1558 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1559 } else if (strcmp(nd_table[0].model, "?") == 0) {
1560 fprintf(stderr, "qemu: Supported NICs: lance\n");
1561 exit (1);
1562 } else {
1563 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1564 exit (1);
1565 }
1566
1567 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1568 hwdef->nvram_size, 2);
1569
1570 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1571 nographic);
1572 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1573 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1574 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1575 serial_hds[1], serial_hds[0]);
1576
1577 slavio_misc = slavio_misc_init(0, -1, hwdef->aux1_base, -1,
1578 slavio_irq[hwdef->me_irq], env, &fdc_tc);
1579
1580 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1581 /* there is zero or one floppy drive */
1582 fd[1] = fd[0] = NULL;
1583 drive_index = drive_get_index(IF_FLOPPY, 0, 0);
1584 if (drive_index != -1)
1585 fd[0] = drives_table[drive_index].bdrv;
1586
1587 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1588 fdc_tc);
1589 }
1590
1591 if (drive_get_max_bus(IF_SCSI) > 0) {
1592 fprintf(stderr, "qemu: too many SCSI bus\n");
1593 exit(1);
1594 }
1595
1596 main_esp = esp_init(hwdef->esp_base, 2,
1597 espdma_memory_read, espdma_memory_write,
1598 espdma, *espdma_irq, esp_reset);
1599
1600 for (i = 0; i < ESP_MAX_DEVS; i++) {
1601 drive_index = drive_get_index(IF_SCSI, 0, i);
1602 if (drive_index == -1)
1603 continue;
1604 esp_scsi_attach(main_esp, drives_table[drive_index].bdrv, i);
1605 }
1606
1607 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1608 RAM_size);
1609
1610 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1611 boot_device, RAM_size, kernel_size, graphic_width,
1612 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1613 "Sun4c");
1614
1615 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1616 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1617 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1618 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1619 }
1620
1621 /* SPARCstation 2 hardware initialisation */
1622 static void ss2_init(ram_addr_t RAM_size, int vga_ram_size,
1623 const char *boot_device, DisplayState *ds,
1624 const char *kernel_filename, const char *kernel_cmdline,
1625 const char *initrd_filename, const char *cpu_model)
1626 {
1627 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1628 kernel_cmdline, initrd_filename, cpu_model);
1629 }
1630
1631 QEMUMachine ss2_machine = {
1632 .name = "SS-2",
1633 .desc = "Sun4c platform, SPARCstation 2",
1634 .init = ss2_init,
1635 .ram_require = PROM_SIZE_MAX + TCX_SIZE,
1636 .nodisk_ok = 1,
1637 .use_scsi = 1,
1638 .max_cpus = 16,
1639 };
1640
Qemu copy for testing