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Sparc32: move intbit_to_level table back to slavio_intctl.c
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40
41 //#define DEBUG_IRQ
42
43 /*
44 * Sun4m architecture was used in the following machines:
45 *
46 * SPARCserver 6xxMP/xx
47 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
48 * SPARCclassic X (4/10)
49 * SPARCstation LX/ZX (4/30)
50 * SPARCstation Voyager
51 * SPARCstation 10/xx, SPARCserver 10/xx
52 * SPARCstation 5, SPARCserver 5
53 * SPARCstation 20/xx, SPARCserver 20
54 * SPARCstation 4
55 *
56 * Sun4d architecture was used in the following machines:
57 *
58 * SPARCcenter 2000
59 * SPARCserver 1000
60 *
61 * Sun4c architecture was used in the following machines:
62 * SPARCstation 1/1+, SPARCserver 1/1+
63 * SPARCstation SLC
64 * SPARCstation IPC
65 * SPARCstation ELC
66 * SPARCstation IPX
67 *
68 * See for example: http://www.sunhelp.org/faq/sunref1.html
69 */
70
71 #ifdef DEBUG_IRQ
72 #define DPRINTF(fmt, ...) \
73 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
74 #else
75 #define DPRINTF(fmt, ...)
76 #endif
77
78 #define KERNEL_LOAD_ADDR 0x00004000
79 #define CMDLINE_ADDR 0x007ff000
80 #define INITRD_LOAD_ADDR 0x00800000
81 #define PROM_SIZE_MAX (1024 * 1024)
82 #define PROM_VADDR 0xffd00000
83 #define PROM_FILENAME "openbios-sparc32"
84 #define CFG_ADDR 0xd00000510ULL
85 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
86
87 #define MAX_CPUS 16
88 #define MAX_PILS 16
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 target_phys_addr_t iommu_base, slavio_base;
94 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
95 target_phys_addr_t serial_base, fd_base;
96 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
97 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 target_phys_addr_t ecc_base;
99 uint32_t ecc_version;
100 long vram_size, nvram_size;
101 // IRQ numbers are not PIL ones, but master interrupt controller
102 // register bit numbers
103 int esp_irq, le_irq, clock_irq, clock1_irq;
104 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
105 uint8_t nvram_machine_id;
106 uint16_t machine_id;
107 uint32_t iommu_version;
108 uint64_t max_mem;
109 const char * const default_cpu_model;
110 };
111
112 #define MAX_IOUNITS 5
113
114 struct sun4d_hwdef {
115 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
116 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
117 target_phys_addr_t serial_base;
118 target_phys_addr_t espdma_base, esp_base;
119 target_phys_addr_t ledma_base, le_base;
120 target_phys_addr_t tcx_base;
121 target_phys_addr_t sbi_base;
122 unsigned long vram_size, nvram_size;
123 // IRQ numbers are not PIL ones, but SBI register bit numbers
124 int esp_irq, le_irq, clock_irq, clock1_irq;
125 int ser_irq, ms_kb_irq, me_irq;
126 uint8_t nvram_machine_id;
127 uint16_t machine_id;
128 uint32_t iounit_version;
129 uint64_t max_mem;
130 const char * const default_cpu_model;
131 };
132
133 struct sun4c_hwdef {
134 target_phys_addr_t iommu_base, slavio_base;
135 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
136 target_phys_addr_t serial_base, fd_base;
137 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
138 target_phys_addr_t tcx_base, aux1_base;
139 long vram_size, nvram_size;
140 // IRQ numbers are not PIL ones, but master interrupt controller
141 // register bit numbers
142 int esp_irq, le_irq, clock_irq, clock1_irq;
143 int ser_irq, ms_kb_irq, fd_irq, me_irq;
144 uint8_t nvram_machine_id;
145 uint16_t machine_id;
146 uint32_t iommu_version;
147 uint64_t max_mem;
148 const char * const default_cpu_model;
149 };
150
151 int DMA_get_channel_mode (int nchan)
152 {
153 return 0;
154 }
155 int DMA_read_memory (int nchan, void *buf, int pos, int size)
156 {
157 return 0;
158 }
159 int DMA_write_memory (int nchan, void *buf, int pos, int size)
160 {
161 return 0;
162 }
163 void DMA_hold_DREQ (int nchan) {}
164 void DMA_release_DREQ (int nchan) {}
165 void DMA_schedule(int nchan) {}
166 void DMA_init (int high_page_enable) {}
167 void DMA_register_channel (int nchan,
168 DMA_transfer_handler transfer_handler,
169 void *opaque)
170 {
171 }
172
173 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
174 {
175 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
176 return 0;
177 }
178
179 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
180 const char *boot_devices, ram_addr_t RAM_size,
181 uint32_t kernel_size,
182 int width, int height, int depth,
183 int nvram_machine_id, const char *arch)
184 {
185 unsigned int i;
186 uint32_t start, end;
187 uint8_t image[0x1ff0];
188 struct OpenBIOS_nvpart_v1 *part_header;
189
190 memset(image, '\0', sizeof(image));
191
192 start = 0;
193
194 // OpenBIOS nvram variables
195 // Variable partition
196 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
197 part_header->signature = OPENBIOS_PART_SYSTEM;
198 pstrcpy(part_header->name, sizeof(part_header->name), "system");
199
200 end = start + sizeof(struct OpenBIOS_nvpart_v1);
201 for (i = 0; i < nb_prom_envs; i++)
202 end = OpenBIOS_set_var(image, end, prom_envs[i]);
203
204 // End marker
205 image[end++] = '\0';
206
207 end = start + ((end - start + 15) & ~15);
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 // free partition
211 start = end;
212 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
213 part_header->signature = OPENBIOS_PART_FREE;
214 pstrcpy(part_header->name, sizeof(part_header->name), "free");
215
216 end = 0x1fd0;
217 OpenBIOS_finish_partition(part_header, end - start);
218
219 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
220 nvram_machine_id);
221
222 for (i = 0; i < sizeof(image); i++)
223 m48t59_write(nvram, i, image[i]);
224 }
225
226 static void *slavio_intctl;
227
228 void pic_info(Monitor *mon)
229 {
230 if (slavio_intctl)
231 slavio_pic_info(mon, slavio_intctl);
232 }
233
234 void irq_info(Monitor *mon)
235 {
236 if (slavio_intctl)
237 slavio_irq_info(mon, slavio_intctl);
238 }
239
240 void cpu_check_irqs(CPUState *env)
241 {
242 if (env->pil_in && (env->interrupt_index == 0 ||
243 (env->interrupt_index & ~15) == TT_EXTINT)) {
244 unsigned int i;
245
246 for (i = 15; i > 0; i--) {
247 if (env->pil_in & (1 << i)) {
248 int old_interrupt = env->interrupt_index;
249
250 env->interrupt_index = TT_EXTINT | i;
251 if (old_interrupt != env->interrupt_index) {
252 DPRINTF("Set CPU IRQ %d\n", i);
253 cpu_interrupt(env, CPU_INTERRUPT_HARD);
254 }
255 break;
256 }
257 }
258 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
259 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
260 env->interrupt_index = 0;
261 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
262 }
263 }
264
265 static void cpu_set_irq(void *opaque, int irq, int level)
266 {
267 CPUState *env = opaque;
268
269 if (level) {
270 DPRINTF("Raise CPU IRQ %d\n", irq);
271 env->halted = 0;
272 env->pil_in |= 1 << irq;
273 cpu_check_irqs(env);
274 } else {
275 DPRINTF("Lower CPU IRQ %d\n", irq);
276 env->pil_in &= ~(1 << irq);
277 cpu_check_irqs(env);
278 }
279 }
280
281 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
282 {
283 }
284
285 static void *slavio_misc;
286
287 void qemu_system_powerdown(void)
288 {
289 slavio_set_power_fail(slavio_misc, 1);
290 }
291
292 static void main_cpu_reset(void *opaque)
293 {
294 CPUState *env = opaque;
295
296 cpu_reset(env);
297 env->halted = 0;
298 }
299
300 static void secondary_cpu_reset(void *opaque)
301 {
302 CPUState *env = opaque;
303
304 cpu_reset(env);
305 env->halted = 1;
306 }
307
308 static void cpu_halt_signal(void *opaque, int irq, int level)
309 {
310 if (level && cpu_single_env)
311 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
312 }
313
314 static unsigned long sun4m_load_kernel(const char *kernel_filename,
315 const char *initrd_filename,
316 ram_addr_t RAM_size)
317 {
318 int linux_boot;
319 unsigned int i;
320 long initrd_size, kernel_size;
321
322 linux_boot = (kernel_filename != NULL);
323
324 kernel_size = 0;
325 if (linux_boot) {
326 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
327 NULL);
328 if (kernel_size < 0)
329 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
330 RAM_size - KERNEL_LOAD_ADDR);
331 if (kernel_size < 0)
332 kernel_size = load_image_targphys(kernel_filename,
333 KERNEL_LOAD_ADDR,
334 RAM_size - KERNEL_LOAD_ADDR);
335 if (kernel_size < 0) {
336 fprintf(stderr, "qemu: could not load kernel '%s'\n",
337 kernel_filename);
338 exit(1);
339 }
340
341 /* load initrd */
342 initrd_size = 0;
343 if (initrd_filename) {
344 initrd_size = load_image_targphys(initrd_filename,
345 INITRD_LOAD_ADDR,
346 RAM_size - INITRD_LOAD_ADDR);
347 if (initrd_size < 0) {
348 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
349 initrd_filename);
350 exit(1);
351 }
352 }
353 if (initrd_size > 0) {
354 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
355 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
356 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
357 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
358 break;
359 }
360 }
361 }
362 }
363 return kernel_size;
364 }
365
366 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
367 {
368 DeviceState *dev;
369 SysBusDevice *s;
370
371 dev = qdev_create(NULL, "iommu");
372 qdev_prop_set_uint32(dev, "version", version);
373 qdev_init(dev);
374 s = sysbus_from_qdev(dev);
375 sysbus_connect_irq(s, 0, irq);
376 sysbus_mmio_map(s, 0, addr);
377
378 return s;
379 }
380
381 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
382 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
383 {
384 DeviceState *dev;
385 SysBusDevice *s;
386
387 qemu_check_nic_model(&nd_table[0], "lance");
388
389 dev = qdev_create(NULL, "lance");
390 dev->nd = nd;
391 qdev_prop_set_ptr(dev, "dma", dma_opaque);
392 qdev_init(dev);
393 s = sysbus_from_qdev(dev);
394 sysbus_mmio_map(s, 0, leaddr);
395 sysbus_connect_irq(s, 0, irq);
396 *reset = qdev_get_gpio_in(dev, 0);
397 }
398
399 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
400 target_phys_addr_t addrg,
401 qemu_irq **parent_irq,
402 unsigned int cputimer)
403 {
404 DeviceState *dev;
405 SysBusDevice *s;
406 unsigned int i, j;
407
408 dev = qdev_create(NULL, "slavio_intctl");
409 qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
410 qdev_init(dev);
411
412 s = sysbus_from_qdev(dev);
413
414 for (i = 0; i < MAX_CPUS; i++) {
415 for (j = 0; j < MAX_PILS; j++) {
416 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
417 }
418 }
419 sysbus_mmio_map(s, 0, addrg);
420 for (i = 0; i < MAX_CPUS; i++) {
421 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
422 }
423
424 return dev;
425 }
426
427 #define SYS_TIMER_OFFSET 0x10000ULL
428 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
429
430 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
431 qemu_irq *cpu_irqs, unsigned int num_cpus)
432 {
433 DeviceState *dev;
434 SysBusDevice *s;
435 unsigned int i;
436
437 dev = qdev_create(NULL, "slavio_timer");
438 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
439 qdev_init(dev);
440 s = sysbus_from_qdev(dev);
441 sysbus_connect_irq(s, 0, master_irq);
442 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
443
444 for (i = 0; i < MAX_CPUS; i++) {
445 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
446 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
447 }
448 }
449
450 #define MISC_LEDS 0x01600000
451 #define MISC_CFG 0x01800000
452 #define MISC_DIAG 0x01a00000
453 #define MISC_MDM 0x01b00000
454 #define MISC_SYS 0x01f00000
455
456 static void *slavio_misc_init(target_phys_addr_t base,
457 target_phys_addr_t aux1_base,
458 target_phys_addr_t aux2_base, qemu_irq irq,
459 qemu_irq fdc_tc)
460 {
461 DeviceState *dev;
462 SysBusDevice *s;
463
464 dev = qdev_create(NULL, "slavio_misc");
465 qdev_init(dev);
466 s = sysbus_from_qdev(dev);
467 if (base) {
468 /* 8 bit registers */
469 /* Slavio control */
470 sysbus_mmio_map(s, 0, base + MISC_CFG);
471 /* Diagnostics */
472 sysbus_mmio_map(s, 1, base + MISC_DIAG);
473 /* Modem control */
474 sysbus_mmio_map(s, 2, base + MISC_MDM);
475 /* 16 bit registers */
476 /* ss600mp diag LEDs */
477 sysbus_mmio_map(s, 3, base + MISC_LEDS);
478 /* 32 bit registers */
479 /* System control */
480 sysbus_mmio_map(s, 4, base + MISC_SYS);
481 }
482 if (aux1_base) {
483 /* AUX 1 (Misc System Functions) */
484 sysbus_mmio_map(s, 5, aux1_base);
485 }
486 if (aux2_base) {
487 /* AUX 2 (Software Powerdown Control) */
488 sysbus_mmio_map(s, 6, aux2_base);
489 }
490 sysbus_connect_irq(s, 0, irq);
491 sysbus_connect_irq(s, 1, fdc_tc);
492
493 return s;
494 }
495
496 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
497 {
498 DeviceState *dev;
499 SysBusDevice *s;
500
501 dev = qdev_create(NULL, "eccmemctl");
502 qdev_prop_set_uint32(dev, "version", version);
503 qdev_init(dev);
504 s = sysbus_from_qdev(dev);
505 sysbus_connect_irq(s, 0, irq);
506 sysbus_mmio_map(s, 0, base);
507 if (version == 0) { // SS-600MP only
508 sysbus_mmio_map(s, 1, base + 0x1000);
509 }
510 }
511
512 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
513 {
514 DeviceState *dev;
515 SysBusDevice *s;
516
517 dev = qdev_create(NULL, "apc");
518 qdev_init(dev);
519 s = sysbus_from_qdev(dev);
520 /* Power management (APC) XXX: not a Slavio device */
521 sysbus_mmio_map(s, 0, power_base);
522 sysbus_connect_irq(s, 0, cpu_halt);
523 }
524
525 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
526 int height, int depth)
527 {
528 DeviceState *dev;
529 SysBusDevice *s;
530
531 dev = qdev_create(NULL, "SUNW,tcx");
532 qdev_prop_set_taddr(dev, "addr", addr);
533 qdev_prop_set_uint32(dev, "vram_size", vram_size);
534 qdev_prop_set_uint16(dev, "width", width);
535 qdev_prop_set_uint16(dev, "height", height);
536 qdev_prop_set_uint16(dev, "depth", depth);
537 qdev_init(dev);
538 s = sysbus_from_qdev(dev);
539 /* 8-bit plane */
540 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
541 /* DAC */
542 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
543 /* TEC (dummy) */
544 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
545 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
546 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
547 if (depth == 24) {
548 /* 24-bit plane */
549 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
550 /* Control plane */
551 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
552 } else {
553 /* THC 8 bit (dummy) */
554 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
555 }
556 }
557
558 /* NCR89C100/MACIO Internal ID register */
559 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
560
561 static void idreg_init(target_phys_addr_t addr)
562 {
563 DeviceState *dev;
564 SysBusDevice *s;
565
566 dev = qdev_create(NULL, "macio_idreg");
567 qdev_init(dev);
568 s = sysbus_from_qdev(dev);
569
570 sysbus_mmio_map(s, 0, addr);
571 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
572 }
573
574 static void idreg_init1(SysBusDevice *dev)
575 {
576 ram_addr_t idreg_offset;
577
578 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
579 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
580 }
581
582 static SysBusDeviceInfo idreg_info = {
583 .init = idreg_init1,
584 .qdev.name = "macio_idreg",
585 .qdev.size = sizeof(SysBusDevice),
586 };
587
588 static void idreg_register_devices(void)
589 {
590 sysbus_register_withprop(&idreg_info);
591 }
592
593 device_init(idreg_register_devices);
594
595 /* Boot PROM (OpenBIOS) */
596 static void prom_init(target_phys_addr_t addr, const char *bios_name)
597 {
598 DeviceState *dev;
599 SysBusDevice *s;
600 char *filename;
601 int ret;
602
603 dev = qdev_create(NULL, "openprom");
604 qdev_init(dev);
605 s = sysbus_from_qdev(dev);
606
607 sysbus_mmio_map(s, 0, addr);
608
609 /* load boot prom */
610 if (bios_name == NULL) {
611 bios_name = PROM_FILENAME;
612 }
613 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
614 if (filename) {
615 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
616 if (ret < 0 || ret > PROM_SIZE_MAX) {
617 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
618 }
619 qemu_free(filename);
620 } else {
621 ret = -1;
622 }
623 if (ret < 0 || ret > PROM_SIZE_MAX) {
624 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
625 exit(1);
626 }
627 }
628
629 static void prom_init1(SysBusDevice *dev)
630 {
631 ram_addr_t prom_offset;
632
633 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
634 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
635 }
636
637 static SysBusDeviceInfo prom_info = {
638 .init = prom_init1,
639 .qdev.name = "openprom",
640 .qdev.size = sizeof(SysBusDevice),
641 .qdev.props = (Property[]) {
642 {/* end of property list */}
643 }
644 };
645
646 static void prom_register_devices(void)
647 {
648 sysbus_register_withprop(&prom_info);
649 }
650
651 device_init(prom_register_devices);
652
653 typedef struct RamDevice
654 {
655 SysBusDevice busdev;
656 uint64_t size;
657 } RamDevice;
658
659 /* System RAM */
660 static void ram_init1(SysBusDevice *dev)
661 {
662 ram_addr_t RAM_size, ram_offset;
663 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
664
665 RAM_size = d->size;
666
667 ram_offset = qemu_ram_alloc(RAM_size);
668 sysbus_init_mmio(dev, RAM_size, ram_offset);
669 }
670
671 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
672 uint64_t max_mem)
673 {
674 DeviceState *dev;
675 SysBusDevice *s;
676 RamDevice *d;
677
678 /* allocate RAM */
679 if ((uint64_t)RAM_size > max_mem) {
680 fprintf(stderr,
681 "qemu: Too much memory for this machine: %d, maximum %d\n",
682 (unsigned int)(RAM_size / (1024 * 1024)),
683 (unsigned int)(max_mem / (1024 * 1024)));
684 exit(1);
685 }
686 dev = qdev_create(NULL, "memory");
687 s = sysbus_from_qdev(dev);
688
689 d = FROM_SYSBUS(RamDevice, s);
690 d->size = RAM_size;
691 qdev_init(dev);
692
693 sysbus_mmio_map(s, 0, addr);
694 }
695
696 static SysBusDeviceInfo ram_info = {
697 .init = ram_init1,
698 .qdev.name = "memory",
699 .qdev.size = sizeof(RamDevice),
700 .qdev.props = (Property[]) {
701 {
702 .name = "size",
703 .info = &qdev_prop_uint64,
704 .offset = offsetof(RamDevice, size),
705 },
706 {/* end of property list */}
707 }
708 };
709
710 static void ram_register_devices(void)
711 {
712 sysbus_register_withprop(&ram_info);
713 }
714
715 device_init(ram_register_devices);
716
717 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
718 uint64_t prom_addr, qemu_irq **cpu_irqs)
719 {
720 CPUState *env;
721
722 env = cpu_init(cpu_model);
723 if (!env) {
724 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
725 exit(1);
726 }
727
728 cpu_sparc_set_id(env, id);
729 if (id == 0) {
730 qemu_register_reset(main_cpu_reset, env);
731 } else {
732 qemu_register_reset(secondary_cpu_reset, env);
733 env->halted = 1;
734 }
735 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
736 env->prom_addr = prom_addr;
737
738 return env;
739 }
740
741 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
742 const char *boot_device,
743 const char *kernel_filename,
744 const char *kernel_cmdline,
745 const char *initrd_filename, const char *cpu_model)
746 {
747 CPUState *envs[MAX_CPUS];
748 unsigned int i;
749 void *iommu, *espdma, *ledma, *nvram;
750 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
751 espdma_irq, ledma_irq;
752 qemu_irq *esp_reset, *le_reset;
753 qemu_irq fdc_tc;
754 qemu_irq *cpu_halt;
755 unsigned long kernel_size;
756 BlockDriverState *fd[MAX_FD];
757 void *fw_cfg;
758 DeviceState *dev;
759 DriveInfo *dinfo;
760
761 /* init CPUs */
762 if (!cpu_model)
763 cpu_model = hwdef->default_cpu_model;
764
765 for(i = 0; i < smp_cpus; i++) {
766 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
767 }
768
769 for (i = smp_cpus; i < MAX_CPUS; i++)
770 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
771
772
773 /* set up devices */
774 ram_init(0, RAM_size, hwdef->max_mem);
775
776 prom_init(hwdef->slavio_base, bios_name);
777
778 dev = slavio_intctl_init(hwdef->intctl_base,
779 hwdef->intctl_base + 0x10000ULL,
780 cpu_irqs,
781 hwdef->clock_irq);
782
783 for (i = 0; i < 32; i++) {
784 slavio_irq[i] = qdev_get_gpio_in(dev, i);
785 }
786 for (i = 0; i < MAX_CPUS; i++) {
787 slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
788 }
789
790 if (hwdef->idreg_base) {
791 idreg_init(hwdef->idreg_base);
792 }
793
794 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
795 slavio_irq[hwdef->me_irq]);
796
797 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
798 iommu, &espdma_irq, &esp_reset);
799
800 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
801 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
802 &le_reset);
803
804 if (graphic_depth != 8 && graphic_depth != 24) {
805 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
806 exit (1);
807 }
808 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
809 graphic_depth);
810
811 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
812
813 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
814 hwdef->nvram_size, 8);
815
816 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
817 slavio_cpu_irq, smp_cpus);
818
819 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
820 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
821 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
822 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
823 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], slavio_irq[hwdef->ser_irq],
824 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
825
826 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
827 slavio_misc = slavio_misc_init(hwdef->slavio_base,
828 hwdef->aux1_base, hwdef->aux2_base,
829 slavio_irq[hwdef->me_irq], fdc_tc);
830 if (hwdef->apc_base) {
831 apc_init(hwdef->apc_base, cpu_halt[0]);
832 }
833
834 if (hwdef->fd_base) {
835 /* there is zero or one floppy drive */
836 memset(fd, 0, sizeof(fd));
837 dinfo = drive_get(IF_FLOPPY, 0, 0);
838 if (dinfo)
839 fd[0] = dinfo->bdrv;
840
841 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
842 &fdc_tc);
843 }
844
845 if (drive_get_max_bus(IF_SCSI) > 0) {
846 fprintf(stderr, "qemu: too many SCSI bus\n");
847 exit(1);
848 }
849
850 esp_init(hwdef->esp_base, 2,
851 espdma_memory_read, espdma_memory_write,
852 espdma, espdma_irq, esp_reset);
853
854 if (hwdef->cs_base) {
855 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
856 slavio_irq[hwdef->cs_irq]);
857 }
858
859 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
860 RAM_size);
861
862 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
863 boot_device, RAM_size, kernel_size, graphic_width,
864 graphic_height, graphic_depth, hwdef->nvram_machine_id,
865 "Sun4m");
866
867 if (hwdef->ecc_base)
868 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
869 hwdef->ecc_version);
870
871 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
872 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
873 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
874 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
875 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
876 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
877 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
878 if (kernel_cmdline) {
879 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
880 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
881 } else {
882 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
883 }
884 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
885 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
886 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
887 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
888 }
889
890 enum {
891 ss2_id = 0,
892 ss5_id = 32,
893 vger_id,
894 lx_id,
895 ss4_id,
896 scls_id,
897 sbook_id,
898 ss10_id = 64,
899 ss20_id,
900 ss600mp_id,
901 ss1000_id = 96,
902 ss2000_id,
903 };
904
905 static const struct sun4m_hwdef sun4m_hwdefs[] = {
906 /* SS-5 */
907 {
908 .iommu_base = 0x10000000,
909 .tcx_base = 0x50000000,
910 .cs_base = 0x6c000000,
911 .slavio_base = 0x70000000,
912 .ms_kb_base = 0x71000000,
913 .serial_base = 0x71100000,
914 .nvram_base = 0x71200000,
915 .fd_base = 0x71400000,
916 .counter_base = 0x71d00000,
917 .intctl_base = 0x71e00000,
918 .idreg_base = 0x78000000,
919 .dma_base = 0x78400000,
920 .esp_base = 0x78800000,
921 .le_base = 0x78c00000,
922 .apc_base = 0x6a000000,
923 .aux1_base = 0x71900000,
924 .aux2_base = 0x71910000,
925 .vram_size = 0x00100000,
926 .nvram_size = 0x2000,
927 .esp_irq = 18,
928 .le_irq = 16,
929 .clock_irq = 7,
930 .clock1_irq = 19,
931 .ms_kb_irq = 14,
932 .ser_irq = 15,
933 .fd_irq = 22,
934 .me_irq = 30,
935 .cs_irq = 5,
936 .nvram_machine_id = 0x80,
937 .machine_id = ss5_id,
938 .iommu_version = 0x05000000,
939 .max_mem = 0x10000000,
940 .default_cpu_model = "Fujitsu MB86904",
941 },
942 /* SS-10 */
943 {
944 .iommu_base = 0xfe0000000ULL,
945 .tcx_base = 0xe20000000ULL,
946 .slavio_base = 0xff0000000ULL,
947 .ms_kb_base = 0xff1000000ULL,
948 .serial_base = 0xff1100000ULL,
949 .nvram_base = 0xff1200000ULL,
950 .fd_base = 0xff1700000ULL,
951 .counter_base = 0xff1300000ULL,
952 .intctl_base = 0xff1400000ULL,
953 .idreg_base = 0xef0000000ULL,
954 .dma_base = 0xef0400000ULL,
955 .esp_base = 0xef0800000ULL,
956 .le_base = 0xef0c00000ULL,
957 .apc_base = 0xefa000000ULL, // XXX should not exist
958 .aux1_base = 0xff1800000ULL,
959 .aux2_base = 0xff1a01000ULL,
960 .ecc_base = 0xf00000000ULL,
961 .ecc_version = 0x10000000, // version 0, implementation 1
962 .vram_size = 0x00100000,
963 .nvram_size = 0x2000,
964 .esp_irq = 18,
965 .le_irq = 16,
966 .clock_irq = 7,
967 .clock1_irq = 19,
968 .ms_kb_irq = 14,
969 .ser_irq = 15,
970 .fd_irq = 22,
971 .me_irq = 30,
972 .ecc_irq = 28,
973 .nvram_machine_id = 0x72,
974 .machine_id = ss10_id,
975 .iommu_version = 0x03000000,
976 .max_mem = 0xf00000000ULL,
977 .default_cpu_model = "TI SuperSparc II",
978 },
979 /* SS-600MP */
980 {
981 .iommu_base = 0xfe0000000ULL,
982 .tcx_base = 0xe20000000ULL,
983 .slavio_base = 0xff0000000ULL,
984 .ms_kb_base = 0xff1000000ULL,
985 .serial_base = 0xff1100000ULL,
986 .nvram_base = 0xff1200000ULL,
987 .counter_base = 0xff1300000ULL,
988 .intctl_base = 0xff1400000ULL,
989 .dma_base = 0xef0081000ULL,
990 .esp_base = 0xef0080000ULL,
991 .le_base = 0xef0060000ULL,
992 .apc_base = 0xefa000000ULL, // XXX should not exist
993 .aux1_base = 0xff1800000ULL,
994 .aux2_base = 0xff1a01000ULL, // XXX should not exist
995 .ecc_base = 0xf00000000ULL,
996 .ecc_version = 0x00000000, // version 0, implementation 0
997 .vram_size = 0x00100000,
998 .nvram_size = 0x2000,
999 .esp_irq = 18,
1000 .le_irq = 16,
1001 .clock_irq = 7,
1002 .clock1_irq = 19,
1003 .ms_kb_irq = 14,
1004 .ser_irq = 15,
1005 .fd_irq = 22,
1006 .me_irq = 30,
1007 .ecc_irq = 28,
1008 .nvram_machine_id = 0x71,
1009 .machine_id = ss600mp_id,
1010 .iommu_version = 0x01000000,
1011 .max_mem = 0xf00000000ULL,
1012 .default_cpu_model = "TI SuperSparc II",
1013 },
1014 /* SS-20 */
1015 {
1016 .iommu_base = 0xfe0000000ULL,
1017 .tcx_base = 0xe20000000ULL,
1018 .slavio_base = 0xff0000000ULL,
1019 .ms_kb_base = 0xff1000000ULL,
1020 .serial_base = 0xff1100000ULL,
1021 .nvram_base = 0xff1200000ULL,
1022 .fd_base = 0xff1700000ULL,
1023 .counter_base = 0xff1300000ULL,
1024 .intctl_base = 0xff1400000ULL,
1025 .idreg_base = 0xef0000000ULL,
1026 .dma_base = 0xef0400000ULL,
1027 .esp_base = 0xef0800000ULL,
1028 .le_base = 0xef0c00000ULL,
1029 .apc_base = 0xefa000000ULL, // XXX should not exist
1030 .aux1_base = 0xff1800000ULL,
1031 .aux2_base = 0xff1a01000ULL,
1032 .ecc_base = 0xf00000000ULL,
1033 .ecc_version = 0x20000000, // version 0, implementation 2
1034 .vram_size = 0x00100000,
1035 .nvram_size = 0x2000,
1036 .esp_irq = 18,
1037 .le_irq = 16,
1038 .clock_irq = 7,
1039 .clock1_irq = 19,
1040 .ms_kb_irq = 14,
1041 .ser_irq = 15,
1042 .fd_irq = 22,
1043 .me_irq = 30,
1044 .ecc_irq = 28,
1045 .nvram_machine_id = 0x72,
1046 .machine_id = ss20_id,
1047 .iommu_version = 0x13000000,
1048 .max_mem = 0xf00000000ULL,
1049 .default_cpu_model = "TI SuperSparc II",
1050 },
1051 /* Voyager */
1052 {
1053 .iommu_base = 0x10000000,
1054 .tcx_base = 0x50000000,
1055 .slavio_base = 0x70000000,
1056 .ms_kb_base = 0x71000000,
1057 .serial_base = 0x71100000,
1058 .nvram_base = 0x71200000,
1059 .fd_base = 0x71400000,
1060 .counter_base = 0x71d00000,
1061 .intctl_base = 0x71e00000,
1062 .idreg_base = 0x78000000,
1063 .dma_base = 0x78400000,
1064 .esp_base = 0x78800000,
1065 .le_base = 0x78c00000,
1066 .apc_base = 0x71300000, // pmc
1067 .aux1_base = 0x71900000,
1068 .aux2_base = 0x71910000,
1069 .vram_size = 0x00100000,
1070 .nvram_size = 0x2000,
1071 .esp_irq = 18,
1072 .le_irq = 16,
1073 .clock_irq = 7,
1074 .clock1_irq = 19,
1075 .ms_kb_irq = 14,
1076 .ser_irq = 15,
1077 .fd_irq = 22,
1078 .me_irq = 30,
1079 .nvram_machine_id = 0x80,
1080 .machine_id = vger_id,
1081 .iommu_version = 0x05000000,
1082 .max_mem = 0x10000000,
1083 .default_cpu_model = "Fujitsu MB86904",
1084 },
1085 /* LX */
1086 {
1087 .iommu_base = 0x10000000,
1088 .tcx_base = 0x50000000,
1089 .slavio_base = 0x70000000,
1090 .ms_kb_base = 0x71000000,
1091 .serial_base = 0x71100000,
1092 .nvram_base = 0x71200000,
1093 .fd_base = 0x71400000,
1094 .counter_base = 0x71d00000,
1095 .intctl_base = 0x71e00000,
1096 .idreg_base = 0x78000000,
1097 .dma_base = 0x78400000,
1098 .esp_base = 0x78800000,
1099 .le_base = 0x78c00000,
1100 .aux1_base = 0x71900000,
1101 .aux2_base = 0x71910000,
1102 .vram_size = 0x00100000,
1103 .nvram_size = 0x2000,
1104 .esp_irq = 18,
1105 .le_irq = 16,
1106 .clock_irq = 7,
1107 .clock1_irq = 19,
1108 .ms_kb_irq = 14,
1109 .ser_irq = 15,
1110 .fd_irq = 22,
1111 .me_irq = 30,
1112 .nvram_machine_id = 0x80,
1113 .machine_id = lx_id,
1114 .iommu_version = 0x04000000,
1115 .max_mem = 0x10000000,
1116 .default_cpu_model = "TI MicroSparc I",
1117 },
1118 /* SS-4 */
1119 {
1120 .iommu_base = 0x10000000,
1121 .tcx_base = 0x50000000,
1122 .cs_base = 0x6c000000,
1123 .slavio_base = 0x70000000,
1124 .ms_kb_base = 0x71000000,
1125 .serial_base = 0x71100000,
1126 .nvram_base = 0x71200000,
1127 .fd_base = 0x71400000,
1128 .counter_base = 0x71d00000,
1129 .intctl_base = 0x71e00000,
1130 .idreg_base = 0x78000000,
1131 .dma_base = 0x78400000,
1132 .esp_base = 0x78800000,
1133 .le_base = 0x78c00000,
1134 .apc_base = 0x6a000000,
1135 .aux1_base = 0x71900000,
1136 .aux2_base = 0x71910000,
1137 .vram_size = 0x00100000,
1138 .nvram_size = 0x2000,
1139 .esp_irq = 18,
1140 .le_irq = 16,
1141 .clock_irq = 7,
1142 .clock1_irq = 19,
1143 .ms_kb_irq = 14,
1144 .ser_irq = 15,
1145 .fd_irq = 22,
1146 .me_irq = 30,
1147 .cs_irq = 5,
1148 .nvram_machine_id = 0x80,
1149 .machine_id = ss4_id,
1150 .iommu_version = 0x05000000,
1151 .max_mem = 0x10000000,
1152 .default_cpu_model = "Fujitsu MB86904",
1153 },
1154 /* SPARCClassic */
1155 {
1156 .iommu_base = 0x10000000,
1157 .tcx_base = 0x50000000,
1158 .slavio_base = 0x70000000,
1159 .ms_kb_base = 0x71000000,
1160 .serial_base = 0x71100000,
1161 .nvram_base = 0x71200000,
1162 .fd_base = 0x71400000,
1163 .counter_base = 0x71d00000,
1164 .intctl_base = 0x71e00000,
1165 .idreg_base = 0x78000000,
1166 .dma_base = 0x78400000,
1167 .esp_base = 0x78800000,
1168 .le_base = 0x78c00000,
1169 .apc_base = 0x6a000000,
1170 .aux1_base = 0x71900000,
1171 .aux2_base = 0x71910000,
1172 .vram_size = 0x00100000,
1173 .nvram_size = 0x2000,
1174 .esp_irq = 18,
1175 .le_irq = 16,
1176 .clock_irq = 7,
1177 .clock1_irq = 19,
1178 .ms_kb_irq = 14,
1179 .ser_irq = 15,
1180 .fd_irq = 22,
1181 .me_irq = 30,
1182 .nvram_machine_id = 0x80,
1183 .machine_id = scls_id,
1184 .iommu_version = 0x05000000,
1185 .max_mem = 0x10000000,
1186 .default_cpu_model = "TI MicroSparc I",
1187 },
1188 /* SPARCbook */
1189 {
1190 .iommu_base = 0x10000000,
1191 .tcx_base = 0x50000000, // XXX
1192 .slavio_base = 0x70000000,
1193 .ms_kb_base = 0x71000000,
1194 .serial_base = 0x71100000,
1195 .nvram_base = 0x71200000,
1196 .fd_base = 0x71400000,
1197 .counter_base = 0x71d00000,
1198 .intctl_base = 0x71e00000,
1199 .idreg_base = 0x78000000,
1200 .dma_base = 0x78400000,
1201 .esp_base = 0x78800000,
1202 .le_base = 0x78c00000,
1203 .apc_base = 0x6a000000,
1204 .aux1_base = 0x71900000,
1205 .aux2_base = 0x71910000,
1206 .vram_size = 0x00100000,
1207 .nvram_size = 0x2000,
1208 .esp_irq = 18,
1209 .le_irq = 16,
1210 .clock_irq = 7,
1211 .clock1_irq = 19,
1212 .ms_kb_irq = 14,
1213 .ser_irq = 15,
1214 .fd_irq = 22,
1215 .me_irq = 30,
1216 .nvram_machine_id = 0x80,
1217 .machine_id = sbook_id,
1218 .iommu_version = 0x05000000,
1219 .max_mem = 0x10000000,
1220 .default_cpu_model = "TI MicroSparc I",
1221 },
1222 };
1223
1224 /* SPARCstation 5 hardware initialisation */
1225 static void ss5_init(ram_addr_t RAM_size,
1226 const char *boot_device,
1227 const char *kernel_filename, const char *kernel_cmdline,
1228 const char *initrd_filename, const char *cpu_model)
1229 {
1230 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1231 kernel_cmdline, initrd_filename, cpu_model);
1232 }
1233
1234 /* SPARCstation 10 hardware initialisation */
1235 static void ss10_init(ram_addr_t RAM_size,
1236 const char *boot_device,
1237 const char *kernel_filename, const char *kernel_cmdline,
1238 const char *initrd_filename, const char *cpu_model)
1239 {
1240 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1241 kernel_cmdline, initrd_filename, cpu_model);
1242 }
1243
1244 /* SPARCserver 600MP hardware initialisation */
1245 static void ss600mp_init(ram_addr_t RAM_size,
1246 const char *boot_device,
1247 const char *kernel_filename,
1248 const char *kernel_cmdline,
1249 const char *initrd_filename, const char *cpu_model)
1250 {
1251 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1252 kernel_cmdline, initrd_filename, cpu_model);
1253 }
1254
1255 /* SPARCstation 20 hardware initialisation */
1256 static void ss20_init(ram_addr_t RAM_size,
1257 const char *boot_device,
1258 const char *kernel_filename, const char *kernel_cmdline,
1259 const char *initrd_filename, const char *cpu_model)
1260 {
1261 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1262 kernel_cmdline, initrd_filename, cpu_model);
1263 }
1264
1265 /* SPARCstation Voyager hardware initialisation */
1266 static void vger_init(ram_addr_t RAM_size,
1267 const char *boot_device,
1268 const char *kernel_filename, const char *kernel_cmdline,
1269 const char *initrd_filename, const char *cpu_model)
1270 {
1271 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1272 kernel_cmdline, initrd_filename, cpu_model);
1273 }
1274
1275 /* SPARCstation LX hardware initialisation */
1276 static void ss_lx_init(ram_addr_t RAM_size,
1277 const char *boot_device,
1278 const char *kernel_filename, const char *kernel_cmdline,
1279 const char *initrd_filename, const char *cpu_model)
1280 {
1281 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1282 kernel_cmdline, initrd_filename, cpu_model);
1283 }
1284
1285 /* SPARCstation 4 hardware initialisation */
1286 static void ss4_init(ram_addr_t RAM_size,
1287 const char *boot_device,
1288 const char *kernel_filename, const char *kernel_cmdline,
1289 const char *initrd_filename, const char *cpu_model)
1290 {
1291 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1292 kernel_cmdline, initrd_filename, cpu_model);
1293 }
1294
1295 /* SPARCClassic hardware initialisation */
1296 static void scls_init(ram_addr_t RAM_size,
1297 const char *boot_device,
1298 const char *kernel_filename, const char *kernel_cmdline,
1299 const char *initrd_filename, const char *cpu_model)
1300 {
1301 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1302 kernel_cmdline, initrd_filename, cpu_model);
1303 }
1304
1305 /* SPARCbook hardware initialisation */
1306 static void sbook_init(ram_addr_t RAM_size,
1307 const char *boot_device,
1308 const char *kernel_filename, const char *kernel_cmdline,
1309 const char *initrd_filename, const char *cpu_model)
1310 {
1311 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1312 kernel_cmdline, initrd_filename, cpu_model);
1313 }
1314
1315 static QEMUMachine ss5_machine = {
1316 .name = "SS-5",
1317 .desc = "Sun4m platform, SPARCstation 5",
1318 .init = ss5_init,
1319 .use_scsi = 1,
1320 .is_default = 1,
1321 };
1322
1323 static QEMUMachine ss10_machine = {
1324 .name = "SS-10",
1325 .desc = "Sun4m platform, SPARCstation 10",
1326 .init = ss10_init,
1327 .use_scsi = 1,
1328 .max_cpus = 4,
1329 };
1330
1331 static QEMUMachine ss600mp_machine = {
1332 .name = "SS-600MP",
1333 .desc = "Sun4m platform, SPARCserver 600MP",
1334 .init = ss600mp_init,
1335 .use_scsi = 1,
1336 .max_cpus = 4,
1337 };
1338
1339 static QEMUMachine ss20_machine = {
1340 .name = "SS-20",
1341 .desc = "Sun4m platform, SPARCstation 20",
1342 .init = ss20_init,
1343 .use_scsi = 1,
1344 .max_cpus = 4,
1345 };
1346
1347 static QEMUMachine voyager_machine = {
1348 .name = "Voyager",
1349 .desc = "Sun4m platform, SPARCstation Voyager",
1350 .init = vger_init,
1351 .use_scsi = 1,
1352 };
1353
1354 static QEMUMachine ss_lx_machine = {
1355 .name = "LX",
1356 .desc = "Sun4m platform, SPARCstation LX",
1357 .init = ss_lx_init,
1358 .use_scsi = 1,
1359 };
1360
1361 static QEMUMachine ss4_machine = {
1362 .name = "SS-4",
1363 .desc = "Sun4m platform, SPARCstation 4",
1364 .init = ss4_init,
1365 .use_scsi = 1,
1366 };
1367
1368 static QEMUMachine scls_machine = {
1369 .name = "SPARCClassic",
1370 .desc = "Sun4m platform, SPARCClassic",
1371 .init = scls_init,
1372 .use_scsi = 1,
1373 };
1374
1375 static QEMUMachine sbook_machine = {
1376 .name = "SPARCbook",
1377 .desc = "Sun4m platform, SPARCbook",
1378 .init = sbook_init,
1379 .use_scsi = 1,
1380 };
1381
1382 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1383 /* SS-1000 */
1384 {
1385 .iounit_bases = {
1386 0xfe0200000ULL,
1387 0xfe1200000ULL,
1388 0xfe2200000ULL,
1389 0xfe3200000ULL,
1390 -1,
1391 },
1392 .tcx_base = 0x820000000ULL,
1393 .slavio_base = 0xf00000000ULL,
1394 .ms_kb_base = 0xf00240000ULL,
1395 .serial_base = 0xf00200000ULL,
1396 .nvram_base = 0xf00280000ULL,
1397 .counter_base = 0xf00300000ULL,
1398 .espdma_base = 0x800081000ULL,
1399 .esp_base = 0x800080000ULL,
1400 .ledma_base = 0x800040000ULL,
1401 .le_base = 0x800060000ULL,
1402 .sbi_base = 0xf02800000ULL,
1403 .vram_size = 0x00100000,
1404 .nvram_size = 0x2000,
1405 .esp_irq = 3,
1406 .le_irq = 4,
1407 .clock_irq = 14,
1408 .clock1_irq = 10,
1409 .ms_kb_irq = 12,
1410 .ser_irq = 12,
1411 .nvram_machine_id = 0x80,
1412 .machine_id = ss1000_id,
1413 .iounit_version = 0x03000000,
1414 .max_mem = 0xf00000000ULL,
1415 .default_cpu_model = "TI SuperSparc II",
1416 },
1417 /* SS-2000 */
1418 {
1419 .iounit_bases = {
1420 0xfe0200000ULL,
1421 0xfe1200000ULL,
1422 0xfe2200000ULL,
1423 0xfe3200000ULL,
1424 0xfe4200000ULL,
1425 },
1426 .tcx_base = 0x820000000ULL,
1427 .slavio_base = 0xf00000000ULL,
1428 .ms_kb_base = 0xf00240000ULL,
1429 .serial_base = 0xf00200000ULL,
1430 .nvram_base = 0xf00280000ULL,
1431 .counter_base = 0xf00300000ULL,
1432 .espdma_base = 0x800081000ULL,
1433 .esp_base = 0x800080000ULL,
1434 .ledma_base = 0x800040000ULL,
1435 .le_base = 0x800060000ULL,
1436 .sbi_base = 0xf02800000ULL,
1437 .vram_size = 0x00100000,
1438 .nvram_size = 0x2000,
1439 .esp_irq = 3,
1440 .le_irq = 4,
1441 .clock_irq = 14,
1442 .clock1_irq = 10,
1443 .ms_kb_irq = 12,
1444 .ser_irq = 12,
1445 .nvram_machine_id = 0x80,
1446 .machine_id = ss2000_id,
1447 .iounit_version = 0x03000000,
1448 .max_mem = 0xf00000000ULL,
1449 .default_cpu_model = "TI SuperSparc II",
1450 },
1451 };
1452
1453 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1454 {
1455 DeviceState *dev;
1456 SysBusDevice *s;
1457 unsigned int i;
1458
1459 dev = qdev_create(NULL, "sbi");
1460 qdev_init(dev);
1461
1462 s = sysbus_from_qdev(dev);
1463
1464 for (i = 0; i < MAX_CPUS; i++) {
1465 sysbus_connect_irq(s, i, *parent_irq[i]);
1466 }
1467
1468 sysbus_mmio_map(s, 0, addr);
1469
1470 return dev;
1471 }
1472
1473 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1474 const char *boot_device,
1475 const char *kernel_filename,
1476 const char *kernel_cmdline,
1477 const char *initrd_filename, const char *cpu_model)
1478 {
1479 CPUState *envs[MAX_CPUS];
1480 unsigned int i;
1481 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1482 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1483 espdma_irq, ledma_irq;
1484 qemu_irq *esp_reset, *le_reset;
1485 unsigned long kernel_size;
1486 void *fw_cfg;
1487 DeviceState *dev;
1488
1489 /* init CPUs */
1490 if (!cpu_model)
1491 cpu_model = hwdef->default_cpu_model;
1492
1493 for(i = 0; i < smp_cpus; i++) {
1494 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1495 }
1496
1497 for (i = smp_cpus; i < MAX_CPUS; i++)
1498 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1499
1500 /* set up devices */
1501 ram_init(0, RAM_size, hwdef->max_mem);
1502
1503 prom_init(hwdef->slavio_base, bios_name);
1504
1505 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1506
1507 for (i = 0; i < 32; i++) {
1508 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1509 }
1510 for (i = 0; i < MAX_CPUS; i++) {
1511 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1512 }
1513
1514 for (i = 0; i < MAX_IOUNITS; i++)
1515 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1516 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1517 hwdef->iounit_version,
1518 sbi_irq[hwdef->me_irq]);
1519
1520 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1521 iounits[0], &espdma_irq, &esp_reset);
1522
1523 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1524 iounits[0], &ledma_irq, &le_reset);
1525
1526 if (graphic_depth != 8 && graphic_depth != 24) {
1527 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1528 exit (1);
1529 }
1530 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1531 graphic_depth);
1532
1533 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1534
1535 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1536 hwdef->nvram_size, 8);
1537
1538 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1539 sbi_cpu_irq, smp_cpus);
1540
1541 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1542 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1543 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1544 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1545 escc_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], sbi_irq[hwdef->ser_irq],
1546 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1547
1548 if (drive_get_max_bus(IF_SCSI) > 0) {
1549 fprintf(stderr, "qemu: too many SCSI bus\n");
1550 exit(1);
1551 }
1552
1553 esp_init(hwdef->esp_base, 2,
1554 espdma_memory_read, espdma_memory_write,
1555 espdma, espdma_irq, esp_reset);
1556
1557 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1558 RAM_size);
1559
1560 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1561 boot_device, RAM_size, kernel_size, graphic_width,
1562 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1563 "Sun4d");
1564
1565 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1566 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1567 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1568 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1569 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1570 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1571 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1572 if (kernel_cmdline) {
1573 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1574 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1575 } else {
1576 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1577 }
1578 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1579 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1580 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1581 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1582 }
1583
1584 /* SPARCserver 1000 hardware initialisation */
1585 static void ss1000_init(ram_addr_t RAM_size,
1586 const char *boot_device,
1587 const char *kernel_filename, const char *kernel_cmdline,
1588 const char *initrd_filename, const char *cpu_model)
1589 {
1590 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1591 kernel_cmdline, initrd_filename, cpu_model);
1592 }
1593
1594 /* SPARCcenter 2000 hardware initialisation */
1595 static void ss2000_init(ram_addr_t RAM_size,
1596 const char *boot_device,
1597 const char *kernel_filename, const char *kernel_cmdline,
1598 const char *initrd_filename, const char *cpu_model)
1599 {
1600 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1601 kernel_cmdline, initrd_filename, cpu_model);
1602 }
1603
1604 static QEMUMachine ss1000_machine = {
1605 .name = "SS-1000",
1606 .desc = "Sun4d platform, SPARCserver 1000",
1607 .init = ss1000_init,
1608 .use_scsi = 1,
1609 .max_cpus = 8,
1610 };
1611
1612 static QEMUMachine ss2000_machine = {
1613 .name = "SS-2000",
1614 .desc = "Sun4d platform, SPARCcenter 2000",
1615 .init = ss2000_init,
1616 .use_scsi = 1,
1617 .max_cpus = 20,
1618 };
1619
1620 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1621 /* SS-2 */
1622 {
1623 .iommu_base = 0xf8000000,
1624 .tcx_base = 0xfe000000,
1625 .slavio_base = 0xf6000000,
1626 .intctl_base = 0xf5000000,
1627 .counter_base = 0xf3000000,
1628 .ms_kb_base = 0xf0000000,
1629 .serial_base = 0xf1000000,
1630 .nvram_base = 0xf2000000,
1631 .fd_base = 0xf7200000,
1632 .dma_base = 0xf8400000,
1633 .esp_base = 0xf8800000,
1634 .le_base = 0xf8c00000,
1635 .aux1_base = 0xf7400003,
1636 .vram_size = 0x00100000,
1637 .nvram_size = 0x800,
1638 .esp_irq = 2,
1639 .le_irq = 3,
1640 .clock_irq = 5,
1641 .clock1_irq = 7,
1642 .ms_kb_irq = 1,
1643 .ser_irq = 1,
1644 .fd_irq = 1,
1645 .me_irq = 1,
1646 .nvram_machine_id = 0x55,
1647 .machine_id = ss2_id,
1648 .max_mem = 0x10000000,
1649 .default_cpu_model = "Cypress CY7C601",
1650 },
1651 };
1652
1653 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1654 qemu_irq *parent_irq)
1655 {
1656 DeviceState *dev;
1657 SysBusDevice *s;
1658 unsigned int i;
1659
1660 dev = qdev_create(NULL, "sun4c_intctl");
1661 qdev_init(dev);
1662
1663 s = sysbus_from_qdev(dev);
1664
1665 for (i = 0; i < MAX_PILS; i++) {
1666 sysbus_connect_irq(s, i, parent_irq[i]);
1667 }
1668 sysbus_mmio_map(s, 0, addr);
1669
1670 return dev;
1671 }
1672
1673 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1674 const char *boot_device,
1675 const char *kernel_filename,
1676 const char *kernel_cmdline,
1677 const char *initrd_filename, const char *cpu_model)
1678 {
1679 CPUState *env;
1680 void *iommu, *espdma, *ledma, *nvram;
1681 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1682 qemu_irq *esp_reset, *le_reset;
1683 qemu_irq fdc_tc;
1684 unsigned long kernel_size;
1685 BlockDriverState *fd[MAX_FD];
1686 void *fw_cfg;
1687 DeviceState *dev;
1688 unsigned int i;
1689 DriveInfo *dinfo;
1690
1691 /* init CPU */
1692 if (!cpu_model)
1693 cpu_model = hwdef->default_cpu_model;
1694
1695 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1696
1697 /* set up devices */
1698 ram_init(0, RAM_size, hwdef->max_mem);
1699
1700 prom_init(hwdef->slavio_base, bios_name);
1701
1702 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1703
1704 for (i = 0; i < 8; i++) {
1705 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1706 }
1707
1708 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1709 slavio_irq[hwdef->me_irq]);
1710
1711 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
1712 iommu, &espdma_irq, &esp_reset);
1713
1714 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1715 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
1716 &le_reset);
1717
1718 if (graphic_depth != 8 && graphic_depth != 24) {
1719 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1720 exit (1);
1721 }
1722 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1723 graphic_depth);
1724
1725 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1726
1727 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1728 hwdef->nvram_size, 2);
1729
1730 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
1731 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1732 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1733 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1734 escc_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
1735 slavio_irq[hwdef->ser_irq], serial_hds[0], serial_hds[1],
1736 ESCC_CLOCK, 1);
1737
1738 slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1739 slavio_irq[hwdef->me_irq], fdc_tc);
1740
1741 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1742 /* there is zero or one floppy drive */
1743 memset(fd, 0, sizeof(fd));
1744 dinfo = drive_get(IF_FLOPPY, 0, 0);
1745 if (dinfo)
1746 fd[0] = dinfo->bdrv;
1747
1748 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd,
1749 &fdc_tc);
1750 }
1751
1752 if (drive_get_max_bus(IF_SCSI) > 0) {
1753 fprintf(stderr, "qemu: too many SCSI bus\n");
1754 exit(1);
1755 }
1756
1757 esp_init(hwdef->esp_base, 2,
1758 espdma_memory_read, espdma_memory_write,
1759 espdma, espdma_irq, esp_reset);
1760
1761 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1762 RAM_size);
1763
1764 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1765 boot_device, RAM_size, kernel_size, graphic_width,
1766 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1767 "Sun4c");
1768
1769 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1770 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1771 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1772 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1773 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1774 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1775 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1776 if (kernel_cmdline) {
1777 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1778 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1779 } else {
1780 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1781 }
1782 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1783 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1784 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1785 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1786 }
1787
1788 /* SPARCstation 2 hardware initialisation */
1789 static void ss2_init(ram_addr_t RAM_size,
1790 const char *boot_device,
1791 const char *kernel_filename, const char *kernel_cmdline,
1792 const char *initrd_filename, const char *cpu_model)
1793 {
1794 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1795 kernel_cmdline, initrd_filename, cpu_model);
1796 }
1797
1798 static QEMUMachine ss2_machine = {
1799 .name = "SS-2",
1800 .desc = "Sun4c platform, SPARCstation 2",
1801 .init = ss2_init,
1802 .use_scsi = 1,
1803 };
1804
1805 static void ss2_machine_init(void)
1806 {
1807 qemu_register_machine(&ss5_machine);
1808 qemu_register_machine(&ss10_machine);
1809 qemu_register_machine(&ss600mp_machine);
1810 qemu_register_machine(&ss20_machine);
1811 qemu_register_machine(&voyager_machine);
1812 qemu_register_machine(&ss_lx_machine);
1813 qemu_register_machine(&ss4_machine);
1814 qemu_register_machine(&scls_machine);
1815 qemu_register_machine(&sbook_machine);
1816 qemu_register_machine(&ss1000_machine);
1817 qemu_register_machine(&ss2000_machine);
1818 qemu_register_machine(&ss2_machine);
1819 }
1820
1821 machine_init(ss2_machine_init);
Qemu copy for testing