2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "qemu-timer.h"
28 #include "sparc32_dma.h"
33 #include "firmware_abi.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
47 * Sun4m architecture was used in the following machines:
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
59 * Sun4d architecture was used in the following machines:
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
87 #define ESCC_CLOCK 4915200
90 target_phys_addr_t iommu_base
, iommu_pad_base
, iommu_pad_len
, slavio_base
;
91 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
92 target_phys_addr_t serial_base
, fd_base
;
93 target_phys_addr_t afx_base
, idreg_base
, dma_base
, esp_base
, le_base
;
94 target_phys_addr_t tcx_base
, cs_base
, apc_base
, aux1_base
, aux2_base
;
95 target_phys_addr_t bpp_base
, dbri_base
, sx_base
;
97 target_phys_addr_t reg_base
, vram_base
;
99 target_phys_addr_t ecc_base
;
101 const char * const default_cpu_model
;
102 uint32_t ecc_version
;
103 uint32_t iommu_version
;
105 uint8_t nvram_machine_id
;
108 #define MAX_IOUNITS 5
111 target_phys_addr_t iounit_bases
[MAX_IOUNITS
], slavio_base
;
112 target_phys_addr_t counter_base
, nvram_base
, ms_kb_base
;
113 target_phys_addr_t serial_base
;
114 target_phys_addr_t espdma_base
, esp_base
;
115 target_phys_addr_t ledma_base
, le_base
;
116 target_phys_addr_t tcx_base
;
117 target_phys_addr_t sbi_base
;
119 const char * const default_cpu_model
;
120 uint32_t iounit_version
;
122 uint8_t nvram_machine_id
;
126 target_phys_addr_t iommu_base
, slavio_base
;
127 target_phys_addr_t intctl_base
, counter_base
, nvram_base
, ms_kb_base
;
128 target_phys_addr_t serial_base
, fd_base
;
129 target_phys_addr_t idreg_base
, dma_base
, esp_base
, le_base
;
130 target_phys_addr_t tcx_base
, aux1_base
;
132 const char * const default_cpu_model
;
133 uint32_t iommu_version
;
135 uint8_t nvram_machine_id
;
138 int DMA_get_channel_mode (int nchan
)
142 int DMA_read_memory (int nchan
, void *buf
, int pos
, int size
)
146 int DMA_write_memory (int nchan
, void *buf
, int pos
, int size
)
150 void DMA_hold_DREQ (int nchan
) {}
151 void DMA_release_DREQ (int nchan
) {}
152 void DMA_schedule(int nchan
) {}
154 void DMA_init(int high_page_enable
, qemu_irq
*cpu_request_exit
)
158 void DMA_register_channel (int nchan
,
159 DMA_transfer_handler transfer_handler
,
164 static int fw_cfg_boot_set(void *opaque
, const char *boot_device
)
166 fw_cfg_add_i16(opaque
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
170 static void nvram_init(M48t59State
*nvram
, uint8_t *macaddr
,
171 const char *cmdline
, const char *boot_devices
,
172 ram_addr_t RAM_size
, uint32_t kernel_size
,
173 int width
, int height
, int depth
,
174 int nvram_machine_id
, const char *arch
)
178 uint8_t image
[0x1ff0];
179 struct OpenBIOS_nvpart_v1
*part_header
;
181 memset(image
, '\0', sizeof(image
));
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
188 part_header
->signature
= OPENBIOS_PART_SYSTEM
;
189 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "system");
191 end
= start
+ sizeof(struct OpenBIOS_nvpart_v1
);
192 for (i
= 0; i
< nb_prom_envs
; i
++)
193 end
= OpenBIOS_set_var(image
, end
, prom_envs
[i
]);
198 end
= start
+ ((end
- start
+ 15) & ~15);
199 OpenBIOS_finish_partition(part_header
, end
- start
);
203 part_header
= (struct OpenBIOS_nvpart_v1
*)&image
[start
];
204 part_header
->signature
= OPENBIOS_PART_FREE
;
205 pstrcpy(part_header
->name
, sizeof(part_header
->name
), "free");
208 OpenBIOS_finish_partition(part_header
, end
- start
);
210 Sun_init_header((struct Sun_nvram
*)&image
[0x1fd8], macaddr
,
213 for (i
= 0; i
< sizeof(image
); i
++)
214 m48t59_write(nvram
, i
, image
[i
]);
217 static DeviceState
*slavio_intctl
;
219 void sun4m_pic_info(Monitor
*mon
)
222 slavio_pic_info(mon
, slavio_intctl
);
225 void sun4m_irq_info(Monitor
*mon
)
228 slavio_irq_info(mon
, slavio_intctl
);
231 void cpu_check_irqs(CPUState
*env
)
233 if (env
->pil_in
&& (env
->interrupt_index
== 0 ||
234 (env
->interrupt_index
& ~15) == TT_EXTINT
)) {
237 for (i
= 15; i
> 0; i
--) {
238 if (env
->pil_in
& (1 << i
)) {
239 int old_interrupt
= env
->interrupt_index
;
241 env
->interrupt_index
= TT_EXTINT
| i
;
242 if (old_interrupt
!= env
->interrupt_index
) {
243 trace_sun4m_cpu_interrupt(i
);
244 cpu_interrupt(env
, CPU_INTERRUPT_HARD
);
249 } else if (!env
->pil_in
&& (env
->interrupt_index
& ~15) == TT_EXTINT
) {
250 trace_sun4m_cpu_reset_interrupt(env
->interrupt_index
& 15);
251 env
->interrupt_index
= 0;
252 cpu_reset_interrupt(env
, CPU_INTERRUPT_HARD
);
256 static void cpu_kick_irq(CPUState
*env
)
263 static void cpu_set_irq(void *opaque
, int irq
, int level
)
265 CPUState
*env
= opaque
;
268 trace_sun4m_cpu_set_irq_raise(irq
);
269 env
->pil_in
|= 1 << irq
;
272 trace_sun4m_cpu_set_irq_lower(irq
);
273 env
->pil_in
&= ~(1 << irq
);
278 static void dummy_cpu_set_irq(void *opaque
, int irq
, int level
)
282 static void main_cpu_reset(void *opaque
)
284 CPUState
*env
= opaque
;
290 static void secondary_cpu_reset(void *opaque
)
292 CPUState
*env
= opaque
;
298 static void cpu_halt_signal(void *opaque
, int irq
, int level
)
300 if (level
&& cpu_single_env
)
301 cpu_interrupt(cpu_single_env
, CPU_INTERRUPT_HALT
);
304 static uint64_t translate_kernel_address(void *opaque
, uint64_t addr
)
306 return addr
- 0xf0000000ULL
;
309 static unsigned long sun4m_load_kernel(const char *kernel_filename
,
310 const char *initrd_filename
,
315 long initrd_size
, kernel_size
;
318 linux_boot
= (kernel_filename
!= NULL
);
329 kernel_size
= load_elf(kernel_filename
, translate_kernel_address
, NULL
,
330 NULL
, NULL
, NULL
, 1, ELF_MACHINE
, 0);
332 kernel_size
= load_aout(kernel_filename
, KERNEL_LOAD_ADDR
,
333 RAM_size
- KERNEL_LOAD_ADDR
, bswap_needed
,
336 kernel_size
= load_image_targphys(kernel_filename
,
338 RAM_size
- KERNEL_LOAD_ADDR
);
339 if (kernel_size
< 0) {
340 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
347 if (initrd_filename
) {
348 initrd_size
= load_image_targphys(initrd_filename
,
350 RAM_size
- INITRD_LOAD_ADDR
);
351 if (initrd_size
< 0) {
352 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
357 if (initrd_size
> 0) {
358 for (i
= 0; i
< 64 * TARGET_PAGE_SIZE
; i
+= TARGET_PAGE_SIZE
) {
359 ptr
= rom_ptr(KERNEL_LOAD_ADDR
+ i
);
360 if (ldl_p(ptr
) == 0x48647253) { // HdrS
361 stl_p(ptr
+ 16, INITRD_LOAD_ADDR
);
362 stl_p(ptr
+ 20, initrd_size
);
371 static void *iommu_init(target_phys_addr_t addr
, uint32_t version
, qemu_irq irq
)
376 dev
= qdev_create(NULL
, "iommu");
377 qdev_prop_set_uint32(dev
, "version", version
);
378 qdev_init_nofail(dev
);
379 s
= sysbus_from_qdev(dev
);
380 sysbus_connect_irq(s
, 0, irq
);
381 sysbus_mmio_map(s
, 0, addr
);
386 static void *sparc32_dma_init(target_phys_addr_t daddr
, qemu_irq parent_irq
,
387 void *iommu
, qemu_irq
*dev_irq
, int is_ledma
)
392 dev
= qdev_create(NULL
, "sparc32_dma");
393 qdev_prop_set_ptr(dev
, "iommu_opaque", iommu
);
394 qdev_prop_set_uint32(dev
, "is_ledma", is_ledma
);
395 qdev_init_nofail(dev
);
396 s
= sysbus_from_qdev(dev
);
397 sysbus_connect_irq(s
, 0, parent_irq
);
398 *dev_irq
= qdev_get_gpio_in(dev
, 0);
399 sysbus_mmio_map(s
, 0, daddr
);
404 static void lance_init(NICInfo
*nd
, target_phys_addr_t leaddr
,
405 void *dma_opaque
, qemu_irq irq
)
411 qemu_check_nic_model(&nd_table
[0], "lance");
413 dev
= qdev_create(NULL
, "lance");
414 qdev_set_nic_properties(dev
, nd
);
415 qdev_prop_set_ptr(dev
, "dma", dma_opaque
);
416 qdev_init_nofail(dev
);
417 s
= sysbus_from_qdev(dev
);
418 sysbus_mmio_map(s
, 0, leaddr
);
419 sysbus_connect_irq(s
, 0, irq
);
420 reset
= qdev_get_gpio_in(dev
, 0);
421 qdev_connect_gpio_out(dma_opaque
, 0, reset
);
424 static DeviceState
*slavio_intctl_init(target_phys_addr_t addr
,
425 target_phys_addr_t addrg
,
426 qemu_irq
**parent_irq
)
432 dev
= qdev_create(NULL
, "slavio_intctl");
433 qdev_init_nofail(dev
);
435 s
= sysbus_from_qdev(dev
);
437 for (i
= 0; i
< MAX_CPUS
; i
++) {
438 for (j
= 0; j
< MAX_PILS
; j
++) {
439 sysbus_connect_irq(s
, i
* MAX_PILS
+ j
, parent_irq
[i
][j
]);
442 sysbus_mmio_map(s
, 0, addrg
);
443 for (i
= 0; i
< MAX_CPUS
; i
++) {
444 sysbus_mmio_map(s
, i
+ 1, addr
+ i
* TARGET_PAGE_SIZE
);
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
453 static void slavio_timer_init_all(target_phys_addr_t addr
, qemu_irq master_irq
,
454 qemu_irq
*cpu_irqs
, unsigned int num_cpus
)
460 dev
= qdev_create(NULL
, "slavio_timer");
461 qdev_prop_set_uint32(dev
, "num_cpus", num_cpus
);
462 qdev_init_nofail(dev
);
463 s
= sysbus_from_qdev(dev
);
464 sysbus_connect_irq(s
, 0, master_irq
);
465 sysbus_mmio_map(s
, 0, addr
+ SYS_TIMER_OFFSET
);
467 for (i
= 0; i
< MAX_CPUS
; i
++) {
468 sysbus_mmio_map(s
, i
+ 1, addr
+ (target_phys_addr_t
)CPU_TIMER_OFFSET(i
));
469 sysbus_connect_irq(s
, i
+ 1, cpu_irqs
[i
]);
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
479 static void slavio_misc_init(target_phys_addr_t base
,
480 target_phys_addr_t aux1_base
,
481 target_phys_addr_t aux2_base
, qemu_irq irq
,
487 dev
= qdev_create(NULL
, "slavio_misc");
488 qdev_init_nofail(dev
);
489 s
= sysbus_from_qdev(dev
);
491 /* 8 bit registers */
493 sysbus_mmio_map(s
, 0, base
+ MISC_CFG
);
495 sysbus_mmio_map(s
, 1, base
+ MISC_DIAG
);
497 sysbus_mmio_map(s
, 2, base
+ MISC_MDM
);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s
, 3, base
+ MISC_LEDS
);
501 /* 32 bit registers */
503 sysbus_mmio_map(s
, 4, base
+ MISC_SYS
);
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s
, 5, aux1_base
);
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s
, 6, aux2_base
);
513 sysbus_connect_irq(s
, 0, irq
);
514 sysbus_connect_irq(s
, 1, fdc_tc
);
515 qemu_system_powerdown
= qdev_get_gpio_in(dev
, 0);
518 static void ecc_init(target_phys_addr_t base
, qemu_irq irq
, uint32_t version
)
523 dev
= qdev_create(NULL
, "eccmemctl");
524 qdev_prop_set_uint32(dev
, "version", version
);
525 qdev_init_nofail(dev
);
526 s
= sysbus_from_qdev(dev
);
527 sysbus_connect_irq(s
, 0, irq
);
528 sysbus_mmio_map(s
, 0, base
);
529 if (version
== 0) { // SS-600MP only
530 sysbus_mmio_map(s
, 1, base
+ 0x1000);
534 static void apc_init(target_phys_addr_t power_base
, qemu_irq cpu_halt
)
539 dev
= qdev_create(NULL
, "apc");
540 qdev_init_nofail(dev
);
541 s
= sysbus_from_qdev(dev
);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s
, 0, power_base
);
544 sysbus_connect_irq(s
, 0, cpu_halt
);
547 static void tcx_init(target_phys_addr_t addr
, int vram_size
, int width
,
548 int height
, int depth
)
553 dev
= qdev_create(NULL
, "SUNW,tcx");
554 qdev_prop_set_taddr(dev
, "addr", addr
);
555 qdev_prop_set_uint32(dev
, "vram_size", vram_size
);
556 qdev_prop_set_uint16(dev
, "width", width
);
557 qdev_prop_set_uint16(dev
, "height", height
);
558 qdev_prop_set_uint16(dev
, "depth", depth
);
559 qdev_init_nofail(dev
);
560 s
= sysbus_from_qdev(dev
);
562 sysbus_mmio_map(s
, 0, addr
+ 0x00800000ULL
);
564 sysbus_mmio_map(s
, 1, addr
+ 0x00200000ULL
);
566 sysbus_mmio_map(s
, 2, addr
+ 0x00700000ULL
);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s
, 3, addr
+ 0x00301000ULL
);
571 sysbus_mmio_map(s
, 4, addr
+ 0x02000000ULL
);
573 sysbus_mmio_map(s
, 5, addr
+ 0x0a000000ULL
);
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s
, 4, addr
+ 0x00300000ULL
);
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data
[] = { 0xfe, 0x81, 0x01, 0x03 };
583 static void idreg_init(target_phys_addr_t addr
)
588 dev
= qdev_create(NULL
, "macio_idreg");
589 qdev_init_nofail(dev
);
590 s
= sysbus_from_qdev(dev
);
592 sysbus_mmio_map(s
, 0, addr
);
593 cpu_physical_memory_write_rom(addr
, idreg_data
, sizeof(idreg_data
));
596 typedef struct IDRegState
{
601 static int idreg_init1(SysBusDevice
*dev
)
603 IDRegState
*s
= FROM_SYSBUS(IDRegState
, dev
);
605 memory_region_init_ram(&s
->mem
, "sun4m.idreg", sizeof(idreg_data
));
606 vmstate_register_ram_global(&s
->mem
);
607 memory_region_set_readonly(&s
->mem
, true);
608 sysbus_init_mmio(dev
, &s
->mem
);
612 static void idreg_class_init(ObjectClass
*klass
, void *data
)
614 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
616 k
->init
= idreg_init1
;
619 static DeviceInfo idreg_info
= {
620 .name
= "macio_idreg",
621 .size
= sizeof(IDRegState
),
622 .class_init
= idreg_class_init
,
625 static void idreg_register_devices(void)
627 sysbus_register_withprop(&idreg_info
);
630 device_init(idreg_register_devices
);
632 typedef struct AFXState
{
637 /* SS-5 TCX AFX register */
638 static void afx_init(target_phys_addr_t addr
)
643 dev
= qdev_create(NULL
, "tcx_afx");
644 qdev_init_nofail(dev
);
645 s
= sysbus_from_qdev(dev
);
647 sysbus_mmio_map(s
, 0, addr
);
650 static int afx_init1(SysBusDevice
*dev
)
652 AFXState
*s
= FROM_SYSBUS(AFXState
, dev
);
654 memory_region_init_ram(&s
->mem
, "sun4m.afx", 4);
655 vmstate_register_ram_global(&s
->mem
);
656 sysbus_init_mmio(dev
, &s
->mem
);
660 static void afx_class_init(ObjectClass
*klass
, void *data
)
662 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
667 static DeviceInfo afx_info
= {
669 .size
= sizeof(AFXState
),
670 .class_init
= afx_class_init
,
673 static void afx_register_devices(void)
675 sysbus_register_withprop(&afx_info
);
678 device_init(afx_register_devices
);
680 typedef struct PROMState
{
685 /* Boot PROM (OpenBIOS) */
686 static uint64_t translate_prom_address(void *opaque
, uint64_t addr
)
688 target_phys_addr_t
*base_addr
= (target_phys_addr_t
*)opaque
;
689 return addr
+ *base_addr
- PROM_VADDR
;
692 static void prom_init(target_phys_addr_t addr
, const char *bios_name
)
699 dev
= qdev_create(NULL
, "openprom");
700 qdev_init_nofail(dev
);
701 s
= sysbus_from_qdev(dev
);
703 sysbus_mmio_map(s
, 0, addr
);
706 if (bios_name
== NULL
) {
707 bios_name
= PROM_FILENAME
;
709 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
711 ret
= load_elf(filename
, translate_prom_address
, &addr
, NULL
,
712 NULL
, NULL
, 1, ELF_MACHINE
, 0);
713 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
714 ret
= load_image_targphys(filename
, addr
, PROM_SIZE_MAX
);
720 if (ret
< 0 || ret
> PROM_SIZE_MAX
) {
721 fprintf(stderr
, "qemu: could not load prom '%s'\n", bios_name
);
726 static int prom_init1(SysBusDevice
*dev
)
728 PROMState
*s
= FROM_SYSBUS(PROMState
, dev
);
730 memory_region_init_ram(&s
->prom
, "sun4m.prom", PROM_SIZE_MAX
);
731 vmstate_register_ram_global(&s
->prom
);
732 memory_region_set_readonly(&s
->prom
, true);
733 sysbus_init_mmio(dev
, &s
->prom
);
737 static Property prom_properties
[] = {
738 {/* end of property list */},
741 static void prom_class_init(ObjectClass
*klass
, void *data
)
743 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
745 k
->init
= prom_init1
;
748 static DeviceInfo prom_info
= {
750 .size
= sizeof(PROMState
),
751 .props
= prom_properties
,
752 .class_init
= prom_class_init
,
755 static void prom_register_devices(void)
757 sysbus_register_withprop(&prom_info
);
760 device_init(prom_register_devices
);
762 typedef struct RamDevice
770 static int ram_init1(SysBusDevice
*dev
)
772 RamDevice
*d
= FROM_SYSBUS(RamDevice
, dev
);
774 memory_region_init_ram(&d
->ram
, "sun4m.ram", d
->size
);
775 vmstate_register_ram_global(&d
->ram
);
776 sysbus_init_mmio(dev
, &d
->ram
);
780 static void ram_init(target_phys_addr_t addr
, ram_addr_t RAM_size
,
788 if ((uint64_t)RAM_size
> max_mem
) {
790 "qemu: Too much memory for this machine: %d, maximum %d\n",
791 (unsigned int)(RAM_size
/ (1024 * 1024)),
792 (unsigned int)(max_mem
/ (1024 * 1024)));
795 dev
= qdev_create(NULL
, "memory");
796 s
= sysbus_from_qdev(dev
);
798 d
= FROM_SYSBUS(RamDevice
, s
);
800 qdev_init_nofail(dev
);
802 sysbus_mmio_map(s
, 0, addr
);
805 static Property ram_properties
[] = {
806 DEFINE_PROP_UINT64("size", RamDevice
, size
, 0),
807 DEFINE_PROP_END_OF_LIST(),
810 static void ram_class_init(ObjectClass
*klass
, void *data
)
812 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
817 static DeviceInfo ram_info
= {
819 .size
= sizeof(RamDevice
),
820 .props
= ram_properties
,
821 .class_init
= ram_class_init
,
824 static void ram_register_devices(void)
826 sysbus_register_withprop(&ram_info
);
829 device_init(ram_register_devices
);
831 static void cpu_devinit(const char *cpu_model
, unsigned int id
,
832 uint64_t prom_addr
, qemu_irq
**cpu_irqs
)
836 env
= cpu_init(cpu_model
);
838 fprintf(stderr
, "qemu: Unable to find Sparc CPU definition\n");
842 cpu_sparc_set_id(env
, id
);
844 qemu_register_reset(main_cpu_reset
, env
);
846 qemu_register_reset(secondary_cpu_reset
, env
);
849 *cpu_irqs
= qemu_allocate_irqs(cpu_set_irq
, env
, MAX_PILS
);
850 env
->prom_addr
= prom_addr
;
853 static void sun4m_hw_init(const struct sun4m_hwdef
*hwdef
, ram_addr_t RAM_size
,
854 const char *boot_device
,
855 const char *kernel_filename
,
856 const char *kernel_cmdline
,
857 const char *initrd_filename
, const char *cpu_model
)
860 void *iommu
, *espdma
, *ledma
, *nvram
;
861 qemu_irq
*cpu_irqs
[MAX_CPUS
], slavio_irq
[32], slavio_cpu_irq
[MAX_CPUS
],
862 espdma_irq
, ledma_irq
;
863 qemu_irq esp_reset
, dma_enable
;
866 unsigned long kernel_size
;
867 DriveInfo
*fd
[MAX_FD
];
869 unsigned int num_vsimms
;
873 cpu_model
= hwdef
->default_cpu_model
;
875 for(i
= 0; i
< smp_cpus
; i
++) {
876 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
879 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
880 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
884 ram_init(0, RAM_size
, hwdef
->max_mem
);
885 /* models without ECC don't trap when missing ram is accessed */
886 if (!hwdef
->ecc_base
) {
887 empty_slot_init(RAM_size
, hwdef
->max_mem
- RAM_size
);
890 prom_init(hwdef
->slavio_base
, bios_name
);
892 slavio_intctl
= slavio_intctl_init(hwdef
->intctl_base
,
893 hwdef
->intctl_base
+ 0x10000ULL
,
896 for (i
= 0; i
< 32; i
++) {
897 slavio_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, i
);
899 for (i
= 0; i
< MAX_CPUS
; i
++) {
900 slavio_cpu_irq
[i
] = qdev_get_gpio_in(slavio_intctl
, 32 + i
);
903 if (hwdef
->idreg_base
) {
904 idreg_init(hwdef
->idreg_base
);
907 if (hwdef
->afx_base
) {
908 afx_init(hwdef
->afx_base
);
911 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
914 if (hwdef
->iommu_pad_base
) {
915 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
916 Software shouldn't use aliased addresses, neither should it crash
917 when does. Using empty_slot instead of aliasing can help with
918 debugging such accesses */
919 empty_slot_init(hwdef
->iommu_pad_base
,hwdef
->iommu_pad_len
);
922 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[18],
923 iommu
, &espdma_irq
, 0);
925 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
926 slavio_irq
[16], iommu
, &ledma_irq
, 1);
928 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
929 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
933 if (num_vsimms
== 0) {
934 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
938 for (i
= num_vsimms
; i
< MAX_VSIMMS
; i
++) {
939 /* vsimm registers probed by OBP */
940 if (hwdef
->vsimm
[i
].reg_base
) {
941 empty_slot_init(hwdef
->vsimm
[i
].reg_base
, 0x2000);
945 if (hwdef
->sx_base
) {
946 empty_slot_init(hwdef
->sx_base
, 0x2000);
949 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
951 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
953 slavio_timer_init_all(hwdef
->counter_base
, slavio_irq
[19], slavio_cpu_irq
, smp_cpus
);
955 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[14],
956 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
957 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
958 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
959 escc_init(hwdef
->serial_base
, slavio_irq
[15], slavio_irq
[15],
960 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
962 cpu_halt
= qemu_allocate_irqs(cpu_halt_signal
, NULL
, 1);
963 slavio_misc_init(hwdef
->slavio_base
, hwdef
->aux1_base
, hwdef
->aux2_base
,
964 slavio_irq
[30], fdc_tc
);
966 if (hwdef
->apc_base
) {
967 apc_init(hwdef
->apc_base
, cpu_halt
[0]);
970 if (hwdef
->fd_base
) {
971 /* there is zero or one floppy drive */
972 memset(fd
, 0, sizeof(fd
));
973 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
974 sun4m_fdctrl_init(slavio_irq
[22], hwdef
->fd_base
, fd
,
978 if (drive_get_max_bus(IF_SCSI
) > 0) {
979 fprintf(stderr
, "qemu: too many SCSI bus\n");
983 esp_init(hwdef
->esp_base
, 2,
984 espdma_memory_read
, espdma_memory_write
,
985 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
987 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
988 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
990 if (hwdef
->cs_base
) {
991 sysbus_create_simple("SUNW,CS4231", hwdef
->cs_base
,
995 if (hwdef
->dbri_base
) {
996 /* ISDN chip with attached CS4215 audio codec */
998 empty_slot_init(hwdef
->dbri_base
+0x1000, 0x30);
1000 empty_slot_init(hwdef
->dbri_base
+0x10000, 0x100);
1003 if (hwdef
->bpp_base
) {
1005 empty_slot_init(hwdef
->bpp_base
, 0x20);
1008 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1011 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1012 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1013 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1016 if (hwdef
->ecc_base
)
1017 ecc_init(hwdef
->ecc_base
, slavio_irq
[28],
1018 hwdef
->ecc_version
);
1020 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1021 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1022 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1023 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1024 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1025 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1026 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1027 if (kernel_cmdline
) {
1028 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1029 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1030 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1031 (uint8_t*)strdup(kernel_cmdline
),
1032 strlen(kernel_cmdline
) + 1);
1033 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
,
1034 strlen(kernel_cmdline
) + 1);
1036 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1037 fw_cfg_add_i32(fw_cfg
, FW_CFG_CMDLINE_SIZE
, 0);
1039 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1040 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1041 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1042 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1060 static const struct sun4m_hwdef sun4m_hwdefs
[] = {
1063 .iommu_base
= 0x10000000,
1064 .iommu_pad_base
= 0x10004000,
1065 .iommu_pad_len
= 0x0fffb000,
1066 .tcx_base
= 0x50000000,
1067 .cs_base
= 0x6c000000,
1068 .slavio_base
= 0x70000000,
1069 .ms_kb_base
= 0x71000000,
1070 .serial_base
= 0x71100000,
1071 .nvram_base
= 0x71200000,
1072 .fd_base
= 0x71400000,
1073 .counter_base
= 0x71d00000,
1074 .intctl_base
= 0x71e00000,
1075 .idreg_base
= 0x78000000,
1076 .dma_base
= 0x78400000,
1077 .esp_base
= 0x78800000,
1078 .le_base
= 0x78c00000,
1079 .apc_base
= 0x6a000000,
1080 .afx_base
= 0x6e000000,
1081 .aux1_base
= 0x71900000,
1082 .aux2_base
= 0x71910000,
1083 .nvram_machine_id
= 0x80,
1084 .machine_id
= ss5_id
,
1085 .iommu_version
= 0x05000000,
1086 .max_mem
= 0x10000000,
1087 .default_cpu_model
= "Fujitsu MB86904",
1091 .iommu_base
= 0xfe0000000ULL
,
1092 .tcx_base
= 0xe20000000ULL
,
1093 .slavio_base
= 0xff0000000ULL
,
1094 .ms_kb_base
= 0xff1000000ULL
,
1095 .serial_base
= 0xff1100000ULL
,
1096 .nvram_base
= 0xff1200000ULL
,
1097 .fd_base
= 0xff1700000ULL
,
1098 .counter_base
= 0xff1300000ULL
,
1099 .intctl_base
= 0xff1400000ULL
,
1100 .idreg_base
= 0xef0000000ULL
,
1101 .dma_base
= 0xef0400000ULL
,
1102 .esp_base
= 0xef0800000ULL
,
1103 .le_base
= 0xef0c00000ULL
,
1104 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1105 .aux1_base
= 0xff1800000ULL
,
1106 .aux2_base
= 0xff1a01000ULL
,
1107 .ecc_base
= 0xf00000000ULL
,
1108 .ecc_version
= 0x10000000, // version 0, implementation 1
1109 .nvram_machine_id
= 0x72,
1110 .machine_id
= ss10_id
,
1111 .iommu_version
= 0x03000000,
1112 .max_mem
= 0xf00000000ULL
,
1113 .default_cpu_model
= "TI SuperSparc II",
1117 .iommu_base
= 0xfe0000000ULL
,
1118 .tcx_base
= 0xe20000000ULL
,
1119 .slavio_base
= 0xff0000000ULL
,
1120 .ms_kb_base
= 0xff1000000ULL
,
1121 .serial_base
= 0xff1100000ULL
,
1122 .nvram_base
= 0xff1200000ULL
,
1123 .counter_base
= 0xff1300000ULL
,
1124 .intctl_base
= 0xff1400000ULL
,
1125 .dma_base
= 0xef0081000ULL
,
1126 .esp_base
= 0xef0080000ULL
,
1127 .le_base
= 0xef0060000ULL
,
1128 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1129 .aux1_base
= 0xff1800000ULL
,
1130 .aux2_base
= 0xff1a01000ULL
, // XXX should not exist
1131 .ecc_base
= 0xf00000000ULL
,
1132 .ecc_version
= 0x00000000, // version 0, implementation 0
1133 .nvram_machine_id
= 0x71,
1134 .machine_id
= ss600mp_id
,
1135 .iommu_version
= 0x01000000,
1136 .max_mem
= 0xf00000000ULL
,
1137 .default_cpu_model
= "TI SuperSparc II",
1141 .iommu_base
= 0xfe0000000ULL
,
1142 .tcx_base
= 0xe20000000ULL
,
1143 .slavio_base
= 0xff0000000ULL
,
1144 .ms_kb_base
= 0xff1000000ULL
,
1145 .serial_base
= 0xff1100000ULL
,
1146 .nvram_base
= 0xff1200000ULL
,
1147 .fd_base
= 0xff1700000ULL
,
1148 .counter_base
= 0xff1300000ULL
,
1149 .intctl_base
= 0xff1400000ULL
,
1150 .idreg_base
= 0xef0000000ULL
,
1151 .dma_base
= 0xef0400000ULL
,
1152 .esp_base
= 0xef0800000ULL
,
1153 .le_base
= 0xef0c00000ULL
,
1154 .bpp_base
= 0xef4800000ULL
,
1155 .apc_base
= 0xefa000000ULL
, // XXX should not exist
1156 .aux1_base
= 0xff1800000ULL
,
1157 .aux2_base
= 0xff1a01000ULL
,
1158 .dbri_base
= 0xee0000000ULL
,
1159 .sx_base
= 0xf80000000ULL
,
1162 .reg_base
= 0x9c000000ULL
,
1163 .vram_base
= 0xfc000000ULL
1165 .reg_base
= 0x90000000ULL
,
1166 .vram_base
= 0xf0000000ULL
1168 .reg_base
= 0x94000000ULL
1170 .reg_base
= 0x98000000ULL
1173 .ecc_base
= 0xf00000000ULL
,
1174 .ecc_version
= 0x20000000, // version 0, implementation 2
1175 .nvram_machine_id
= 0x72,
1176 .machine_id
= ss20_id
,
1177 .iommu_version
= 0x13000000,
1178 .max_mem
= 0xf00000000ULL
,
1179 .default_cpu_model
= "TI SuperSparc II",
1183 .iommu_base
= 0x10000000,
1184 .tcx_base
= 0x50000000,
1185 .slavio_base
= 0x70000000,
1186 .ms_kb_base
= 0x71000000,
1187 .serial_base
= 0x71100000,
1188 .nvram_base
= 0x71200000,
1189 .fd_base
= 0x71400000,
1190 .counter_base
= 0x71d00000,
1191 .intctl_base
= 0x71e00000,
1192 .idreg_base
= 0x78000000,
1193 .dma_base
= 0x78400000,
1194 .esp_base
= 0x78800000,
1195 .le_base
= 0x78c00000,
1196 .apc_base
= 0x71300000, // pmc
1197 .aux1_base
= 0x71900000,
1198 .aux2_base
= 0x71910000,
1199 .nvram_machine_id
= 0x80,
1200 .machine_id
= vger_id
,
1201 .iommu_version
= 0x05000000,
1202 .max_mem
= 0x10000000,
1203 .default_cpu_model
= "Fujitsu MB86904",
1207 .iommu_base
= 0x10000000,
1208 .iommu_pad_base
= 0x10004000,
1209 .iommu_pad_len
= 0x0fffb000,
1210 .tcx_base
= 0x50000000,
1211 .slavio_base
= 0x70000000,
1212 .ms_kb_base
= 0x71000000,
1213 .serial_base
= 0x71100000,
1214 .nvram_base
= 0x71200000,
1215 .fd_base
= 0x71400000,
1216 .counter_base
= 0x71d00000,
1217 .intctl_base
= 0x71e00000,
1218 .idreg_base
= 0x78000000,
1219 .dma_base
= 0x78400000,
1220 .esp_base
= 0x78800000,
1221 .le_base
= 0x78c00000,
1222 .aux1_base
= 0x71900000,
1223 .aux2_base
= 0x71910000,
1224 .nvram_machine_id
= 0x80,
1225 .machine_id
= lx_id
,
1226 .iommu_version
= 0x04000000,
1227 .max_mem
= 0x10000000,
1228 .default_cpu_model
= "TI MicroSparc I",
1232 .iommu_base
= 0x10000000,
1233 .tcx_base
= 0x50000000,
1234 .cs_base
= 0x6c000000,
1235 .slavio_base
= 0x70000000,
1236 .ms_kb_base
= 0x71000000,
1237 .serial_base
= 0x71100000,
1238 .nvram_base
= 0x71200000,
1239 .fd_base
= 0x71400000,
1240 .counter_base
= 0x71d00000,
1241 .intctl_base
= 0x71e00000,
1242 .idreg_base
= 0x78000000,
1243 .dma_base
= 0x78400000,
1244 .esp_base
= 0x78800000,
1245 .le_base
= 0x78c00000,
1246 .apc_base
= 0x6a000000,
1247 .aux1_base
= 0x71900000,
1248 .aux2_base
= 0x71910000,
1249 .nvram_machine_id
= 0x80,
1250 .machine_id
= ss4_id
,
1251 .iommu_version
= 0x05000000,
1252 .max_mem
= 0x10000000,
1253 .default_cpu_model
= "Fujitsu MB86904",
1257 .iommu_base
= 0x10000000,
1258 .tcx_base
= 0x50000000,
1259 .slavio_base
= 0x70000000,
1260 .ms_kb_base
= 0x71000000,
1261 .serial_base
= 0x71100000,
1262 .nvram_base
= 0x71200000,
1263 .fd_base
= 0x71400000,
1264 .counter_base
= 0x71d00000,
1265 .intctl_base
= 0x71e00000,
1266 .idreg_base
= 0x78000000,
1267 .dma_base
= 0x78400000,
1268 .esp_base
= 0x78800000,
1269 .le_base
= 0x78c00000,
1270 .apc_base
= 0x6a000000,
1271 .aux1_base
= 0x71900000,
1272 .aux2_base
= 0x71910000,
1273 .nvram_machine_id
= 0x80,
1274 .machine_id
= scls_id
,
1275 .iommu_version
= 0x05000000,
1276 .max_mem
= 0x10000000,
1277 .default_cpu_model
= "TI MicroSparc I",
1281 .iommu_base
= 0x10000000,
1282 .tcx_base
= 0x50000000, // XXX
1283 .slavio_base
= 0x70000000,
1284 .ms_kb_base
= 0x71000000,
1285 .serial_base
= 0x71100000,
1286 .nvram_base
= 0x71200000,
1287 .fd_base
= 0x71400000,
1288 .counter_base
= 0x71d00000,
1289 .intctl_base
= 0x71e00000,
1290 .idreg_base
= 0x78000000,
1291 .dma_base
= 0x78400000,
1292 .esp_base
= 0x78800000,
1293 .le_base
= 0x78c00000,
1294 .apc_base
= 0x6a000000,
1295 .aux1_base
= 0x71900000,
1296 .aux2_base
= 0x71910000,
1297 .nvram_machine_id
= 0x80,
1298 .machine_id
= sbook_id
,
1299 .iommu_version
= 0x05000000,
1300 .max_mem
= 0x10000000,
1301 .default_cpu_model
= "TI MicroSparc I",
1305 /* SPARCstation 5 hardware initialisation */
1306 static void ss5_init(ram_addr_t RAM_size
,
1307 const char *boot_device
,
1308 const char *kernel_filename
, const char *kernel_cmdline
,
1309 const char *initrd_filename
, const char *cpu_model
)
1311 sun4m_hw_init(&sun4m_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1312 kernel_cmdline
, initrd_filename
, cpu_model
);
1315 /* SPARCstation 10 hardware initialisation */
1316 static void ss10_init(ram_addr_t RAM_size
,
1317 const char *boot_device
,
1318 const char *kernel_filename
, const char *kernel_cmdline
,
1319 const char *initrd_filename
, const char *cpu_model
)
1321 sun4m_hw_init(&sun4m_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1322 kernel_cmdline
, initrd_filename
, cpu_model
);
1325 /* SPARCserver 600MP hardware initialisation */
1326 static void ss600mp_init(ram_addr_t RAM_size
,
1327 const char *boot_device
,
1328 const char *kernel_filename
,
1329 const char *kernel_cmdline
,
1330 const char *initrd_filename
, const char *cpu_model
)
1332 sun4m_hw_init(&sun4m_hwdefs
[2], RAM_size
, boot_device
, kernel_filename
,
1333 kernel_cmdline
, initrd_filename
, cpu_model
);
1336 /* SPARCstation 20 hardware initialisation */
1337 static void ss20_init(ram_addr_t RAM_size
,
1338 const char *boot_device
,
1339 const char *kernel_filename
, const char *kernel_cmdline
,
1340 const char *initrd_filename
, const char *cpu_model
)
1342 sun4m_hw_init(&sun4m_hwdefs
[3], RAM_size
, boot_device
, kernel_filename
,
1343 kernel_cmdline
, initrd_filename
, cpu_model
);
1346 /* SPARCstation Voyager hardware initialisation */
1347 static void vger_init(ram_addr_t RAM_size
,
1348 const char *boot_device
,
1349 const char *kernel_filename
, const char *kernel_cmdline
,
1350 const char *initrd_filename
, const char *cpu_model
)
1352 sun4m_hw_init(&sun4m_hwdefs
[4], RAM_size
, boot_device
, kernel_filename
,
1353 kernel_cmdline
, initrd_filename
, cpu_model
);
1356 /* SPARCstation LX hardware initialisation */
1357 static void ss_lx_init(ram_addr_t RAM_size
,
1358 const char *boot_device
,
1359 const char *kernel_filename
, const char *kernel_cmdline
,
1360 const char *initrd_filename
, const char *cpu_model
)
1362 sun4m_hw_init(&sun4m_hwdefs
[5], RAM_size
, boot_device
, kernel_filename
,
1363 kernel_cmdline
, initrd_filename
, cpu_model
);
1366 /* SPARCstation 4 hardware initialisation */
1367 static void ss4_init(ram_addr_t RAM_size
,
1368 const char *boot_device
,
1369 const char *kernel_filename
, const char *kernel_cmdline
,
1370 const char *initrd_filename
, const char *cpu_model
)
1372 sun4m_hw_init(&sun4m_hwdefs
[6], RAM_size
, boot_device
, kernel_filename
,
1373 kernel_cmdline
, initrd_filename
, cpu_model
);
1376 /* SPARCClassic hardware initialisation */
1377 static void scls_init(ram_addr_t RAM_size
,
1378 const char *boot_device
,
1379 const char *kernel_filename
, const char *kernel_cmdline
,
1380 const char *initrd_filename
, const char *cpu_model
)
1382 sun4m_hw_init(&sun4m_hwdefs
[7], RAM_size
, boot_device
, kernel_filename
,
1383 kernel_cmdline
, initrd_filename
, cpu_model
);
1386 /* SPARCbook hardware initialisation */
1387 static void sbook_init(ram_addr_t RAM_size
,
1388 const char *boot_device
,
1389 const char *kernel_filename
, const char *kernel_cmdline
,
1390 const char *initrd_filename
, const char *cpu_model
)
1392 sun4m_hw_init(&sun4m_hwdefs
[8], RAM_size
, boot_device
, kernel_filename
,
1393 kernel_cmdline
, initrd_filename
, cpu_model
);
1396 static QEMUMachine ss5_machine
= {
1398 .desc
= "Sun4m platform, SPARCstation 5",
1404 static QEMUMachine ss10_machine
= {
1406 .desc
= "Sun4m platform, SPARCstation 10",
1412 static QEMUMachine ss600mp_machine
= {
1414 .desc
= "Sun4m platform, SPARCserver 600MP",
1415 .init
= ss600mp_init
,
1420 static QEMUMachine ss20_machine
= {
1422 .desc
= "Sun4m platform, SPARCstation 20",
1428 static QEMUMachine voyager_machine
= {
1430 .desc
= "Sun4m platform, SPARCstation Voyager",
1435 static QEMUMachine ss_lx_machine
= {
1437 .desc
= "Sun4m platform, SPARCstation LX",
1442 static QEMUMachine ss4_machine
= {
1444 .desc
= "Sun4m platform, SPARCstation 4",
1449 static QEMUMachine scls_machine
= {
1450 .name
= "SPARCClassic",
1451 .desc
= "Sun4m platform, SPARCClassic",
1456 static QEMUMachine sbook_machine
= {
1457 .name
= "SPARCbook",
1458 .desc
= "Sun4m platform, SPARCbook",
1463 static const struct sun4d_hwdef sun4d_hwdefs
[] = {
1473 .tcx_base
= 0x820000000ULL
,
1474 .slavio_base
= 0xf00000000ULL
,
1475 .ms_kb_base
= 0xf00240000ULL
,
1476 .serial_base
= 0xf00200000ULL
,
1477 .nvram_base
= 0xf00280000ULL
,
1478 .counter_base
= 0xf00300000ULL
,
1479 .espdma_base
= 0x800081000ULL
,
1480 .esp_base
= 0x800080000ULL
,
1481 .ledma_base
= 0x800040000ULL
,
1482 .le_base
= 0x800060000ULL
,
1483 .sbi_base
= 0xf02800000ULL
,
1484 .nvram_machine_id
= 0x80,
1485 .machine_id
= ss1000_id
,
1486 .iounit_version
= 0x03000000,
1487 .max_mem
= 0xf00000000ULL
,
1488 .default_cpu_model
= "TI SuperSparc II",
1499 .tcx_base
= 0x820000000ULL
,
1500 .slavio_base
= 0xf00000000ULL
,
1501 .ms_kb_base
= 0xf00240000ULL
,
1502 .serial_base
= 0xf00200000ULL
,
1503 .nvram_base
= 0xf00280000ULL
,
1504 .counter_base
= 0xf00300000ULL
,
1505 .espdma_base
= 0x800081000ULL
,
1506 .esp_base
= 0x800080000ULL
,
1507 .ledma_base
= 0x800040000ULL
,
1508 .le_base
= 0x800060000ULL
,
1509 .sbi_base
= 0xf02800000ULL
,
1510 .nvram_machine_id
= 0x80,
1511 .machine_id
= ss2000_id
,
1512 .iounit_version
= 0x03000000,
1513 .max_mem
= 0xf00000000ULL
,
1514 .default_cpu_model
= "TI SuperSparc II",
1518 static DeviceState
*sbi_init(target_phys_addr_t addr
, qemu_irq
**parent_irq
)
1524 dev
= qdev_create(NULL
, "sbi");
1525 qdev_init_nofail(dev
);
1527 s
= sysbus_from_qdev(dev
);
1529 for (i
= 0; i
< MAX_CPUS
; i
++) {
1530 sysbus_connect_irq(s
, i
, *parent_irq
[i
]);
1533 sysbus_mmio_map(s
, 0, addr
);
1538 static void sun4d_hw_init(const struct sun4d_hwdef
*hwdef
, ram_addr_t RAM_size
,
1539 const char *boot_device
,
1540 const char *kernel_filename
,
1541 const char *kernel_cmdline
,
1542 const char *initrd_filename
, const char *cpu_model
)
1545 void *iounits
[MAX_IOUNITS
], *espdma
, *ledma
, *nvram
;
1546 qemu_irq
*cpu_irqs
[MAX_CPUS
], sbi_irq
[32], sbi_cpu_irq
[MAX_CPUS
],
1547 espdma_irq
, ledma_irq
;
1548 qemu_irq esp_reset
, dma_enable
;
1549 unsigned long kernel_size
;
1555 cpu_model
= hwdef
->default_cpu_model
;
1557 for(i
= 0; i
< smp_cpus
; i
++) {
1558 cpu_devinit(cpu_model
, i
, hwdef
->slavio_base
, &cpu_irqs
[i
]);
1561 for (i
= smp_cpus
; i
< MAX_CPUS
; i
++)
1562 cpu_irqs
[i
] = qemu_allocate_irqs(dummy_cpu_set_irq
, NULL
, MAX_PILS
);
1564 /* set up devices */
1565 ram_init(0, RAM_size
, hwdef
->max_mem
);
1567 prom_init(hwdef
->slavio_base
, bios_name
);
1569 dev
= sbi_init(hwdef
->sbi_base
, cpu_irqs
);
1571 for (i
= 0; i
< 32; i
++) {
1572 sbi_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1574 for (i
= 0; i
< MAX_CPUS
; i
++) {
1575 sbi_cpu_irq
[i
] = qdev_get_gpio_in(dev
, 32 + i
);
1578 for (i
= 0; i
< MAX_IOUNITS
; i
++)
1579 if (hwdef
->iounit_bases
[i
] != (target_phys_addr_t
)-1)
1580 iounits
[i
] = iommu_init(hwdef
->iounit_bases
[i
],
1581 hwdef
->iounit_version
,
1584 espdma
= sparc32_dma_init(hwdef
->espdma_base
, sbi_irq
[3],
1585 iounits
[0], &espdma_irq
, 0);
1587 /* should be lebuffer instead */
1588 ledma
= sparc32_dma_init(hwdef
->ledma_base
, sbi_irq
[4],
1589 iounits
[0], &ledma_irq
, 0);
1591 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1592 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1595 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1598 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1600 nvram
= m48t59_init(sbi_irq
[0], hwdef
->nvram_base
, 0, 0x2000, 8);
1602 slavio_timer_init_all(hwdef
->counter_base
, sbi_irq
[10], sbi_cpu_irq
, smp_cpus
);
1604 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, sbi_irq
[12],
1605 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1606 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1607 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1608 escc_init(hwdef
->serial_base
, sbi_irq
[12], sbi_irq
[12],
1609 serial_hds
[0], serial_hds
[1], ESCC_CLOCK
, 1);
1611 if (drive_get_max_bus(IF_SCSI
) > 0) {
1612 fprintf(stderr
, "qemu: too many SCSI bus\n");
1616 esp_init(hwdef
->esp_base
, 2,
1617 espdma_memory_read
, espdma_memory_write
,
1618 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
1620 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
1621 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
1623 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1626 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1627 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1628 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1631 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1632 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1633 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1634 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1635 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1636 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1637 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1638 if (kernel_cmdline
) {
1639 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1640 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1641 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1642 (uint8_t*)strdup(kernel_cmdline
),
1643 strlen(kernel_cmdline
) + 1);
1645 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1647 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1648 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1649 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1650 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1653 /* SPARCserver 1000 hardware initialisation */
1654 static void ss1000_init(ram_addr_t RAM_size
,
1655 const char *boot_device
,
1656 const char *kernel_filename
, const char *kernel_cmdline
,
1657 const char *initrd_filename
, const char *cpu_model
)
1659 sun4d_hw_init(&sun4d_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1660 kernel_cmdline
, initrd_filename
, cpu_model
);
1663 /* SPARCcenter 2000 hardware initialisation */
1664 static void ss2000_init(ram_addr_t RAM_size
,
1665 const char *boot_device
,
1666 const char *kernel_filename
, const char *kernel_cmdline
,
1667 const char *initrd_filename
, const char *cpu_model
)
1669 sun4d_hw_init(&sun4d_hwdefs
[1], RAM_size
, boot_device
, kernel_filename
,
1670 kernel_cmdline
, initrd_filename
, cpu_model
);
1673 static QEMUMachine ss1000_machine
= {
1675 .desc
= "Sun4d platform, SPARCserver 1000",
1676 .init
= ss1000_init
,
1681 static QEMUMachine ss2000_machine
= {
1683 .desc
= "Sun4d platform, SPARCcenter 2000",
1684 .init
= ss2000_init
,
1689 static const struct sun4c_hwdef sun4c_hwdefs
[] = {
1692 .iommu_base
= 0xf8000000,
1693 .tcx_base
= 0xfe000000,
1694 .slavio_base
= 0xf6000000,
1695 .intctl_base
= 0xf5000000,
1696 .counter_base
= 0xf3000000,
1697 .ms_kb_base
= 0xf0000000,
1698 .serial_base
= 0xf1000000,
1699 .nvram_base
= 0xf2000000,
1700 .fd_base
= 0xf7200000,
1701 .dma_base
= 0xf8400000,
1702 .esp_base
= 0xf8800000,
1703 .le_base
= 0xf8c00000,
1704 .aux1_base
= 0xf7400003,
1705 .nvram_machine_id
= 0x55,
1706 .machine_id
= ss2_id
,
1707 .max_mem
= 0x10000000,
1708 .default_cpu_model
= "Cypress CY7C601",
1712 static DeviceState
*sun4c_intctl_init(target_phys_addr_t addr
,
1713 qemu_irq
*parent_irq
)
1719 dev
= qdev_create(NULL
, "sun4c_intctl");
1720 qdev_init_nofail(dev
);
1722 s
= sysbus_from_qdev(dev
);
1724 for (i
= 0; i
< MAX_PILS
; i
++) {
1725 sysbus_connect_irq(s
, i
, parent_irq
[i
]);
1727 sysbus_mmio_map(s
, 0, addr
);
1732 static void sun4c_hw_init(const struct sun4c_hwdef
*hwdef
, ram_addr_t RAM_size
,
1733 const char *boot_device
,
1734 const char *kernel_filename
,
1735 const char *kernel_cmdline
,
1736 const char *initrd_filename
, const char *cpu_model
)
1738 void *iommu
, *espdma
, *ledma
, *nvram
;
1739 qemu_irq
*cpu_irqs
, slavio_irq
[8], espdma_irq
, ledma_irq
;
1740 qemu_irq esp_reset
, dma_enable
;
1742 unsigned long kernel_size
;
1743 DriveInfo
*fd
[MAX_FD
];
1750 cpu_model
= hwdef
->default_cpu_model
;
1752 cpu_devinit(cpu_model
, 0, hwdef
->slavio_base
, &cpu_irqs
);
1754 /* set up devices */
1755 ram_init(0, RAM_size
, hwdef
->max_mem
);
1757 prom_init(hwdef
->slavio_base
, bios_name
);
1759 dev
= sun4c_intctl_init(hwdef
->intctl_base
, cpu_irqs
);
1761 for (i
= 0; i
< 8; i
++) {
1762 slavio_irq
[i
] = qdev_get_gpio_in(dev
, i
);
1765 iommu
= iommu_init(hwdef
->iommu_base
, hwdef
->iommu_version
,
1768 espdma
= sparc32_dma_init(hwdef
->dma_base
, slavio_irq
[2],
1769 iommu
, &espdma_irq
, 0);
1771 ledma
= sparc32_dma_init(hwdef
->dma_base
+ 16ULL,
1772 slavio_irq
[3], iommu
, &ledma_irq
, 1);
1774 if (graphic_depth
!= 8 && graphic_depth
!= 24) {
1775 fprintf(stderr
, "qemu: Unsupported depth: %d\n", graphic_depth
);
1778 tcx_init(hwdef
->tcx_base
, 0x00100000, graphic_width
, graphic_height
,
1781 lance_init(&nd_table
[0], hwdef
->le_base
, ledma
, ledma_irq
);
1783 nvram
= m48t59_init(slavio_irq
[0], hwdef
->nvram_base
, 0, 0x800, 2);
1785 slavio_serial_ms_kbd_init(hwdef
->ms_kb_base
, slavio_irq
[1],
1786 display_type
== DT_NOGRAPHIC
, ESCC_CLOCK
, 1);
1787 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1788 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1789 escc_init(hwdef
->serial_base
, slavio_irq
[1],
1790 slavio_irq
[1], serial_hds
[0], serial_hds
[1],
1793 slavio_misc_init(0, hwdef
->aux1_base
, 0, slavio_irq
[1], fdc_tc
);
1795 if (hwdef
->fd_base
!= (target_phys_addr_t
)-1) {
1796 /* there is zero or one floppy drive */
1797 memset(fd
, 0, sizeof(fd
));
1798 fd
[0] = drive_get(IF_FLOPPY
, 0, 0);
1799 sun4m_fdctrl_init(slavio_irq
[1], hwdef
->fd_base
, fd
,
1803 if (drive_get_max_bus(IF_SCSI
) > 0) {
1804 fprintf(stderr
, "qemu: too many SCSI bus\n");
1808 esp_init(hwdef
->esp_base
, 2,
1809 espdma_memory_read
, espdma_memory_write
,
1810 espdma
, espdma_irq
, &esp_reset
, &dma_enable
);
1812 qdev_connect_gpio_out(espdma
, 0, esp_reset
);
1813 qdev_connect_gpio_out(espdma
, 1, dma_enable
);
1815 kernel_size
= sun4m_load_kernel(kernel_filename
, initrd_filename
,
1818 nvram_init(nvram
, (uint8_t *)&nd_table
[0].macaddr
, kernel_cmdline
,
1819 boot_device
, RAM_size
, kernel_size
, graphic_width
,
1820 graphic_height
, graphic_depth
, hwdef
->nvram_machine_id
,
1823 fw_cfg
= fw_cfg_init(0, 0, CFG_ADDR
, CFG_ADDR
+ 2);
1824 fw_cfg_add_i32(fw_cfg
, FW_CFG_ID
, 1);
1825 fw_cfg_add_i64(fw_cfg
, FW_CFG_RAM_SIZE
, (uint64_t)ram_size
);
1826 fw_cfg_add_i16(fw_cfg
, FW_CFG_MACHINE_ID
, hwdef
->machine_id
);
1827 fw_cfg_add_i16(fw_cfg
, FW_CFG_SUN4M_DEPTH
, graphic_depth
);
1828 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_ADDR
, KERNEL_LOAD_ADDR
);
1829 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_SIZE
, kernel_size
);
1830 if (kernel_cmdline
) {
1831 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, CMDLINE_ADDR
);
1832 pstrcpy_targphys("cmdline", CMDLINE_ADDR
, TARGET_PAGE_SIZE
, kernel_cmdline
);
1833 fw_cfg_add_bytes(fw_cfg
, FW_CFG_CMDLINE_DATA
,
1834 (uint8_t*)strdup(kernel_cmdline
),
1835 strlen(kernel_cmdline
) + 1);
1837 fw_cfg_add_i32(fw_cfg
, FW_CFG_KERNEL_CMDLINE
, 0);
1839 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_ADDR
, INITRD_LOAD_ADDR
);
1840 fw_cfg_add_i32(fw_cfg
, FW_CFG_INITRD_SIZE
, 0); // not used
1841 fw_cfg_add_i16(fw_cfg
, FW_CFG_BOOT_DEVICE
, boot_device
[0]);
1842 qemu_register_boot_set(fw_cfg_boot_set
, fw_cfg
);
1845 /* SPARCstation 2 hardware initialisation */
1846 static void ss2_init(ram_addr_t RAM_size
,
1847 const char *boot_device
,
1848 const char *kernel_filename
, const char *kernel_cmdline
,
1849 const char *initrd_filename
, const char *cpu_model
)
1851 sun4c_hw_init(&sun4c_hwdefs
[0], RAM_size
, boot_device
, kernel_filename
,
1852 kernel_cmdline
, initrd_filename
, cpu_model
);
1855 static QEMUMachine ss2_machine
= {
1857 .desc
= "Sun4c platform, SPARCstation 2",
1862 static void ss2_machine_init(void)
1864 qemu_register_machine(&ss5_machine
);
1865 qemu_register_machine(&ss10_machine
);
1866 qemu_register_machine(&ss600mp_machine
);
1867 qemu_register_machine(&ss20_machine
);
1868 qemu_register_machine(&voyager_machine
);
1869 qemu_register_machine(&ss_lx_machine
);
1870 qemu_register_machine(&ss4_machine
);
1871 qemu_register_machine(&scls_machine
);
1872 qemu_register_machine(&sbook_machine
);
1873 qemu_register_machine(&ss1000_machine
);
1874 qemu_register_machine(&ss2000_machine
);
1875 qemu_register_machine(&ss2_machine
);
1878 machine_init(ss2_machine_init
);