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Sparc32: use qemu_irq for system_powerdown
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40
41 //#define DEBUG_IRQ
42
43 /*
44 * Sun4m architecture was used in the following machines:
45 *
46 * SPARCserver 6xxMP/xx
47 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
48 * SPARCclassic X (4/10)
49 * SPARCstation LX/ZX (4/30)
50 * SPARCstation Voyager
51 * SPARCstation 10/xx, SPARCserver 10/xx
52 * SPARCstation 5, SPARCserver 5
53 * SPARCstation 20/xx, SPARCserver 20
54 * SPARCstation 4
55 *
56 * Sun4d architecture was used in the following machines:
57 *
58 * SPARCcenter 2000
59 * SPARCserver 1000
60 *
61 * Sun4c architecture was used in the following machines:
62 * SPARCstation 1/1+, SPARCserver 1/1+
63 * SPARCstation SLC
64 * SPARCstation IPC
65 * SPARCstation ELC
66 * SPARCstation IPX
67 *
68 * See for example: http://www.sunhelp.org/faq/sunref1.html
69 */
70
71 #ifdef DEBUG_IRQ
72 #define DPRINTF(fmt, ...) \
73 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
74 #else
75 #define DPRINTF(fmt, ...)
76 #endif
77
78 #define KERNEL_LOAD_ADDR 0x00004000
79 #define CMDLINE_ADDR 0x007ff000
80 #define INITRD_LOAD_ADDR 0x00800000
81 #define PROM_SIZE_MAX (1024 * 1024)
82 #define PROM_VADDR 0xffd00000
83 #define PROM_FILENAME "openbios-sparc32"
84 #define CFG_ADDR 0xd00000510ULL
85 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
86
87 #define MAX_CPUS 16
88 #define MAX_PILS 16
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 target_phys_addr_t iommu_base, slavio_base;
94 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
95 target_phys_addr_t serial_base, fd_base;
96 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
97 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 target_phys_addr_t ecc_base;
99 uint32_t ecc_version;
100 uint8_t nvram_machine_id;
101 uint16_t machine_id;
102 uint32_t iommu_version;
103 uint64_t max_mem;
104 const char * const default_cpu_model;
105 };
106
107 #define MAX_IOUNITS 5
108
109 struct sun4d_hwdef {
110 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
111 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
112 target_phys_addr_t serial_base;
113 target_phys_addr_t espdma_base, esp_base;
114 target_phys_addr_t ledma_base, le_base;
115 target_phys_addr_t tcx_base;
116 target_phys_addr_t sbi_base;
117 uint8_t nvram_machine_id;
118 uint16_t machine_id;
119 uint32_t iounit_version;
120 uint64_t max_mem;
121 const char * const default_cpu_model;
122 };
123
124 struct sun4c_hwdef {
125 target_phys_addr_t iommu_base, slavio_base;
126 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
127 target_phys_addr_t serial_base, fd_base;
128 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
129 target_phys_addr_t tcx_base, aux1_base;
130 uint8_t nvram_machine_id;
131 uint16_t machine_id;
132 uint32_t iommu_version;
133 uint64_t max_mem;
134 const char * const default_cpu_model;
135 };
136
137 int DMA_get_channel_mode (int nchan)
138 {
139 return 0;
140 }
141 int DMA_read_memory (int nchan, void *buf, int pos, int size)
142 {
143 return 0;
144 }
145 int DMA_write_memory (int nchan, void *buf, int pos, int size)
146 {
147 return 0;
148 }
149 void DMA_hold_DREQ (int nchan) {}
150 void DMA_release_DREQ (int nchan) {}
151 void DMA_schedule(int nchan) {}
152 void DMA_init (int high_page_enable) {}
153 void DMA_register_channel (int nchan,
154 DMA_transfer_handler transfer_handler,
155 void *opaque)
156 {
157 }
158
159 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
160 {
161 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
162 return 0;
163 }
164
165 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
166 const char *boot_devices, ram_addr_t RAM_size,
167 uint32_t kernel_size,
168 int width, int height, int depth,
169 int nvram_machine_id, const char *arch)
170 {
171 unsigned int i;
172 uint32_t start, end;
173 uint8_t image[0x1ff0];
174 struct OpenBIOS_nvpart_v1 *part_header;
175
176 memset(image, '\0', sizeof(image));
177
178 start = 0;
179
180 // OpenBIOS nvram variables
181 // Variable partition
182 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
183 part_header->signature = OPENBIOS_PART_SYSTEM;
184 pstrcpy(part_header->name, sizeof(part_header->name), "system");
185
186 end = start + sizeof(struct OpenBIOS_nvpart_v1);
187 for (i = 0; i < nb_prom_envs; i++)
188 end = OpenBIOS_set_var(image, end, prom_envs[i]);
189
190 // End marker
191 image[end++] = '\0';
192
193 end = start + ((end - start + 15) & ~15);
194 OpenBIOS_finish_partition(part_header, end - start);
195
196 // free partition
197 start = end;
198 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
199 part_header->signature = OPENBIOS_PART_FREE;
200 pstrcpy(part_header->name, sizeof(part_header->name), "free");
201
202 end = 0x1fd0;
203 OpenBIOS_finish_partition(part_header, end - start);
204
205 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
206 nvram_machine_id);
207
208 for (i = 0; i < sizeof(image); i++)
209 m48t59_write(nvram, i, image[i]);
210 }
211
212 static void *slavio_intctl;
213
214 void pic_info(Monitor *mon)
215 {
216 if (slavio_intctl)
217 slavio_pic_info(mon, slavio_intctl);
218 }
219
220 void irq_info(Monitor *mon)
221 {
222 if (slavio_intctl)
223 slavio_irq_info(mon, slavio_intctl);
224 }
225
226 void cpu_check_irqs(CPUState *env)
227 {
228 if (env->pil_in && (env->interrupt_index == 0 ||
229 (env->interrupt_index & ~15) == TT_EXTINT)) {
230 unsigned int i;
231
232 for (i = 15; i > 0; i--) {
233 if (env->pil_in & (1 << i)) {
234 int old_interrupt = env->interrupt_index;
235
236 env->interrupt_index = TT_EXTINT | i;
237 if (old_interrupt != env->interrupt_index) {
238 DPRINTF("Set CPU IRQ %d\n", i);
239 cpu_interrupt(env, CPU_INTERRUPT_HARD);
240 }
241 break;
242 }
243 }
244 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
245 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
246 env->interrupt_index = 0;
247 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
248 }
249 }
250
251 static void cpu_set_irq(void *opaque, int irq, int level)
252 {
253 CPUState *env = opaque;
254
255 if (level) {
256 DPRINTF("Raise CPU IRQ %d\n", irq);
257 env->halted = 0;
258 env->pil_in |= 1 << irq;
259 cpu_check_irqs(env);
260 } else {
261 DPRINTF("Lower CPU IRQ %d\n", irq);
262 env->pil_in &= ~(1 << irq);
263 cpu_check_irqs(env);
264 }
265 }
266
267 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
268 {
269 }
270
271 static void main_cpu_reset(void *opaque)
272 {
273 CPUState *env = opaque;
274
275 cpu_reset(env);
276 env->halted = 0;
277 }
278
279 static void secondary_cpu_reset(void *opaque)
280 {
281 CPUState *env = opaque;
282
283 cpu_reset(env);
284 env->halted = 1;
285 }
286
287 static void cpu_halt_signal(void *opaque, int irq, int level)
288 {
289 if (level && cpu_single_env)
290 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
291 }
292
293 static unsigned long sun4m_load_kernel(const char *kernel_filename,
294 const char *initrd_filename,
295 ram_addr_t RAM_size)
296 {
297 int linux_boot;
298 unsigned int i;
299 long initrd_size, kernel_size;
300
301 linux_boot = (kernel_filename != NULL);
302
303 kernel_size = 0;
304 if (linux_boot) {
305 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
306 NULL);
307 if (kernel_size < 0)
308 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
309 RAM_size - KERNEL_LOAD_ADDR);
310 if (kernel_size < 0)
311 kernel_size = load_image_targphys(kernel_filename,
312 KERNEL_LOAD_ADDR,
313 RAM_size - KERNEL_LOAD_ADDR);
314 if (kernel_size < 0) {
315 fprintf(stderr, "qemu: could not load kernel '%s'\n",
316 kernel_filename);
317 exit(1);
318 }
319
320 /* load initrd */
321 initrd_size = 0;
322 if (initrd_filename) {
323 initrd_size = load_image_targphys(initrd_filename,
324 INITRD_LOAD_ADDR,
325 RAM_size - INITRD_LOAD_ADDR);
326 if (initrd_size < 0) {
327 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
328 initrd_filename);
329 exit(1);
330 }
331 }
332 if (initrd_size > 0) {
333 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
334 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
335 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
336 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
337 break;
338 }
339 }
340 }
341 }
342 return kernel_size;
343 }
344
345 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
346 {
347 DeviceState *dev;
348 SysBusDevice *s;
349
350 dev = qdev_create(NULL, "iommu");
351 qdev_prop_set_uint32(dev, "version", version);
352 qdev_init(dev);
353 s = sysbus_from_qdev(dev);
354 sysbus_connect_irq(s, 0, irq);
355 sysbus_mmio_map(s, 0, addr);
356
357 return s;
358 }
359
360 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
361 void *iommu, qemu_irq *dev_irq)
362 {
363 DeviceState *dev;
364 SysBusDevice *s;
365
366 dev = qdev_create(NULL, "sparc32_dma");
367 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
368 qdev_init(dev);
369 s = sysbus_from_qdev(dev);
370 sysbus_connect_irq(s, 0, parent_irq);
371 *dev_irq = qdev_get_gpio_in(dev, 0);
372 sysbus_mmio_map(s, 0, daddr);
373
374 return s;
375 }
376
377 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
378 void *dma_opaque, qemu_irq irq)
379 {
380 DeviceState *dev;
381 SysBusDevice *s;
382 qemu_irq reset;
383
384 qemu_check_nic_model(&nd_table[0], "lance");
385
386 dev = qdev_create(NULL, "lance");
387 dev->nd = nd;
388 qdev_prop_set_ptr(dev, "dma", dma_opaque);
389 qdev_init(dev);
390 s = sysbus_from_qdev(dev);
391 sysbus_mmio_map(s, 0, leaddr);
392 sysbus_connect_irq(s, 0, irq);
393 reset = qdev_get_gpio_in(dev, 0);
394 qdev_connect_gpio_out(dma_opaque, 0, reset);
395 }
396
397 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
398 target_phys_addr_t addrg,
399 qemu_irq **parent_irq,
400 unsigned int cputimer)
401 {
402 DeviceState *dev;
403 SysBusDevice *s;
404 unsigned int i, j;
405
406 dev = qdev_create(NULL, "slavio_intctl");
407 qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
408 qdev_init(dev);
409
410 s = sysbus_from_qdev(dev);
411
412 for (i = 0; i < MAX_CPUS; i++) {
413 for (j = 0; j < MAX_PILS; j++) {
414 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
415 }
416 }
417 sysbus_mmio_map(s, 0, addrg);
418 for (i = 0; i < MAX_CPUS; i++) {
419 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
420 }
421
422 return dev;
423 }
424
425 #define SYS_TIMER_OFFSET 0x10000ULL
426 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
427
428 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
429 qemu_irq *cpu_irqs, unsigned int num_cpus)
430 {
431 DeviceState *dev;
432 SysBusDevice *s;
433 unsigned int i;
434
435 dev = qdev_create(NULL, "slavio_timer");
436 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
437 qdev_init(dev);
438 s = sysbus_from_qdev(dev);
439 sysbus_connect_irq(s, 0, master_irq);
440 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
441
442 for (i = 0; i < MAX_CPUS; i++) {
443 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
444 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
445 }
446 }
447
448 #define MISC_LEDS 0x01600000
449 #define MISC_CFG 0x01800000
450 #define MISC_DIAG 0x01a00000
451 #define MISC_MDM 0x01b00000
452 #define MISC_SYS 0x01f00000
453
454 static qemu_irq slavio_powerdown;
455
456 void qemu_system_powerdown(void)
457 {
458 qemu_irq_raise(slavio_powerdown);
459 }
460
461 static void slavio_misc_init(target_phys_addr_t base,
462 target_phys_addr_t aux1_base,
463 target_phys_addr_t aux2_base, qemu_irq irq,
464 qemu_irq fdc_tc)
465 {
466 DeviceState *dev;
467 SysBusDevice *s;
468
469 dev = qdev_create(NULL, "slavio_misc");
470 qdev_init(dev);
471 s = sysbus_from_qdev(dev);
472 if (base) {
473 /* 8 bit registers */
474 /* Slavio control */
475 sysbus_mmio_map(s, 0, base + MISC_CFG);
476 /* Diagnostics */
477 sysbus_mmio_map(s, 1, base + MISC_DIAG);
478 /* Modem control */
479 sysbus_mmio_map(s, 2, base + MISC_MDM);
480 /* 16 bit registers */
481 /* ss600mp diag LEDs */
482 sysbus_mmio_map(s, 3, base + MISC_LEDS);
483 /* 32 bit registers */
484 /* System control */
485 sysbus_mmio_map(s, 4, base + MISC_SYS);
486 }
487 if (aux1_base) {
488 /* AUX 1 (Misc System Functions) */
489 sysbus_mmio_map(s, 5, aux1_base);
490 }
491 if (aux2_base) {
492 /* AUX 2 (Software Powerdown Control) */
493 sysbus_mmio_map(s, 6, aux2_base);
494 }
495 sysbus_connect_irq(s, 0, irq);
496 sysbus_connect_irq(s, 1, fdc_tc);
497 slavio_powerdown = qdev_get_gpio_in(dev, 0);
498 }
499
500 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
501 {
502 DeviceState *dev;
503 SysBusDevice *s;
504
505 dev = qdev_create(NULL, "eccmemctl");
506 qdev_prop_set_uint32(dev, "version", version);
507 qdev_init(dev);
508 s = sysbus_from_qdev(dev);
509 sysbus_connect_irq(s, 0, irq);
510 sysbus_mmio_map(s, 0, base);
511 if (version == 0) { // SS-600MP only
512 sysbus_mmio_map(s, 1, base + 0x1000);
513 }
514 }
515
516 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
517 {
518 DeviceState *dev;
519 SysBusDevice *s;
520
521 dev = qdev_create(NULL, "apc");
522 qdev_init(dev);
523 s = sysbus_from_qdev(dev);
524 /* Power management (APC) XXX: not a Slavio device */
525 sysbus_mmio_map(s, 0, power_base);
526 sysbus_connect_irq(s, 0, cpu_halt);
527 }
528
529 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
530 int height, int depth)
531 {
532 DeviceState *dev;
533 SysBusDevice *s;
534
535 dev = qdev_create(NULL, "SUNW,tcx");
536 qdev_prop_set_taddr(dev, "addr", addr);
537 qdev_prop_set_uint32(dev, "vram_size", vram_size);
538 qdev_prop_set_uint16(dev, "width", width);
539 qdev_prop_set_uint16(dev, "height", height);
540 qdev_prop_set_uint16(dev, "depth", depth);
541 qdev_init(dev);
542 s = sysbus_from_qdev(dev);
543 /* 8-bit plane */
544 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
545 /* DAC */
546 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
547 /* TEC (dummy) */
548 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
549 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
550 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
551 if (depth == 24) {
552 /* 24-bit plane */
553 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
554 /* Control plane */
555 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
556 } else {
557 /* THC 8 bit (dummy) */
558 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
559 }
560 }
561
562 /* NCR89C100/MACIO Internal ID register */
563 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
564
565 static void idreg_init(target_phys_addr_t addr)
566 {
567 DeviceState *dev;
568 SysBusDevice *s;
569
570 dev = qdev_create(NULL, "macio_idreg");
571 qdev_init(dev);
572 s = sysbus_from_qdev(dev);
573
574 sysbus_mmio_map(s, 0, addr);
575 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
576 }
577
578 static void idreg_init1(SysBusDevice *dev)
579 {
580 ram_addr_t idreg_offset;
581
582 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
583 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
584 }
585
586 static SysBusDeviceInfo idreg_info = {
587 .init = idreg_init1,
588 .qdev.name = "macio_idreg",
589 .qdev.size = sizeof(SysBusDevice),
590 };
591
592 static void idreg_register_devices(void)
593 {
594 sysbus_register_withprop(&idreg_info);
595 }
596
597 device_init(idreg_register_devices);
598
599 /* Boot PROM (OpenBIOS) */
600 static void prom_init(target_phys_addr_t addr, const char *bios_name)
601 {
602 DeviceState *dev;
603 SysBusDevice *s;
604 char *filename;
605 int ret;
606
607 dev = qdev_create(NULL, "openprom");
608 qdev_init(dev);
609 s = sysbus_from_qdev(dev);
610
611 sysbus_mmio_map(s, 0, addr);
612
613 /* load boot prom */
614 if (bios_name == NULL) {
615 bios_name = PROM_FILENAME;
616 }
617 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
618 if (filename) {
619 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
620 if (ret < 0 || ret > PROM_SIZE_MAX) {
621 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
622 }
623 qemu_free(filename);
624 } else {
625 ret = -1;
626 }
627 if (ret < 0 || ret > PROM_SIZE_MAX) {
628 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
629 exit(1);
630 }
631 }
632
633 static void prom_init1(SysBusDevice *dev)
634 {
635 ram_addr_t prom_offset;
636
637 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
638 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
639 }
640
641 static SysBusDeviceInfo prom_info = {
642 .init = prom_init1,
643 .qdev.name = "openprom",
644 .qdev.size = sizeof(SysBusDevice),
645 .qdev.props = (Property[]) {
646 {/* end of property list */}
647 }
648 };
649
650 static void prom_register_devices(void)
651 {
652 sysbus_register_withprop(&prom_info);
653 }
654
655 device_init(prom_register_devices);
656
657 typedef struct RamDevice
658 {
659 SysBusDevice busdev;
660 uint64_t size;
661 } RamDevice;
662
663 /* System RAM */
664 static void ram_init1(SysBusDevice *dev)
665 {
666 ram_addr_t RAM_size, ram_offset;
667 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
668
669 RAM_size = d->size;
670
671 ram_offset = qemu_ram_alloc(RAM_size);
672 sysbus_init_mmio(dev, RAM_size, ram_offset);
673 }
674
675 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
676 uint64_t max_mem)
677 {
678 DeviceState *dev;
679 SysBusDevice *s;
680 RamDevice *d;
681
682 /* allocate RAM */
683 if ((uint64_t)RAM_size > max_mem) {
684 fprintf(stderr,
685 "qemu: Too much memory for this machine: %d, maximum %d\n",
686 (unsigned int)(RAM_size / (1024 * 1024)),
687 (unsigned int)(max_mem / (1024 * 1024)));
688 exit(1);
689 }
690 dev = qdev_create(NULL, "memory");
691 s = sysbus_from_qdev(dev);
692
693 d = FROM_SYSBUS(RamDevice, s);
694 d->size = RAM_size;
695 qdev_init(dev);
696
697 sysbus_mmio_map(s, 0, addr);
698 }
699
700 static SysBusDeviceInfo ram_info = {
701 .init = ram_init1,
702 .qdev.name = "memory",
703 .qdev.size = sizeof(RamDevice),
704 .qdev.props = (Property[]) {
705 {
706 .name = "size",
707 .info = &qdev_prop_uint64,
708 .offset = offsetof(RamDevice, size),
709 },
710 {/* end of property list */}
711 }
712 };
713
714 static void ram_register_devices(void)
715 {
716 sysbus_register_withprop(&ram_info);
717 }
718
719 device_init(ram_register_devices);
720
721 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
722 uint64_t prom_addr, qemu_irq **cpu_irqs)
723 {
724 CPUState *env;
725
726 env = cpu_init(cpu_model);
727 if (!env) {
728 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
729 exit(1);
730 }
731
732 cpu_sparc_set_id(env, id);
733 if (id == 0) {
734 qemu_register_reset(main_cpu_reset, env);
735 } else {
736 qemu_register_reset(secondary_cpu_reset, env);
737 env->halted = 1;
738 }
739 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
740 env->prom_addr = prom_addr;
741
742 return env;
743 }
744
745 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
746 const char *boot_device,
747 const char *kernel_filename,
748 const char *kernel_cmdline,
749 const char *initrd_filename, const char *cpu_model)
750 {
751 CPUState *envs[MAX_CPUS];
752 unsigned int i;
753 void *iommu, *espdma, *ledma, *nvram;
754 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
755 espdma_irq, ledma_irq;
756 qemu_irq esp_reset;
757 qemu_irq fdc_tc;
758 qemu_irq *cpu_halt;
759 unsigned long kernel_size;
760 BlockDriverState *fd[MAX_FD];
761 void *fw_cfg;
762 DeviceState *dev;
763 DriveInfo *dinfo;
764
765 /* init CPUs */
766 if (!cpu_model)
767 cpu_model = hwdef->default_cpu_model;
768
769 for(i = 0; i < smp_cpus; i++) {
770 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
771 }
772
773 for (i = smp_cpus; i < MAX_CPUS; i++)
774 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
775
776
777 /* set up devices */
778 ram_init(0, RAM_size, hwdef->max_mem);
779
780 prom_init(hwdef->slavio_base, bios_name);
781
782 dev = slavio_intctl_init(hwdef->intctl_base,
783 hwdef->intctl_base + 0x10000ULL,
784 cpu_irqs,
785 7);
786
787 for (i = 0; i < 32; i++) {
788 slavio_irq[i] = qdev_get_gpio_in(dev, i);
789 }
790 for (i = 0; i < MAX_CPUS; i++) {
791 slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
792 }
793
794 if (hwdef->idreg_base) {
795 idreg_init(hwdef->idreg_base);
796 }
797
798 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
799 slavio_irq[30]);
800
801 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
802 iommu, &espdma_irq);
803
804 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
805 slavio_irq[16], iommu, &ledma_irq);
806
807 if (graphic_depth != 8 && graphic_depth != 24) {
808 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
809 exit (1);
810 }
811 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
812 graphic_depth);
813
814 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
815
816 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
817
818 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
819
820 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
821 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
822 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
823 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
824 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
825 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
826
827 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
828 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
829 slavio_irq[30], fdc_tc);
830
831 if (hwdef->apc_base) {
832 apc_init(hwdef->apc_base, cpu_halt[0]);
833 }
834
835 if (hwdef->fd_base) {
836 /* there is zero or one floppy drive */
837 memset(fd, 0, sizeof(fd));
838 dinfo = drive_get(IF_FLOPPY, 0, 0);
839 if (dinfo)
840 fd[0] = dinfo->bdrv;
841
842 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
843 &fdc_tc);
844 }
845
846 if (drive_get_max_bus(IF_SCSI) > 0) {
847 fprintf(stderr, "qemu: too many SCSI bus\n");
848 exit(1);
849 }
850
851 esp_reset = qdev_get_gpio_in(espdma, 0);
852 esp_init(hwdef->esp_base, 2,
853 espdma_memory_read, espdma_memory_write,
854 espdma, espdma_irq, &esp_reset);
855
856
857 if (hwdef->cs_base) {
858 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
859 slavio_irq[5]);
860 }
861
862 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
863 RAM_size);
864
865 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
866 boot_device, RAM_size, kernel_size, graphic_width,
867 graphic_height, graphic_depth, hwdef->nvram_machine_id,
868 "Sun4m");
869
870 if (hwdef->ecc_base)
871 ecc_init(hwdef->ecc_base, slavio_irq[28],
872 hwdef->ecc_version);
873
874 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
875 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
876 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
877 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
878 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
879 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
880 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
881 if (kernel_cmdline) {
882 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
883 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
884 } else {
885 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
886 }
887 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
888 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
889 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
890 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
891 }
892
893 enum {
894 ss2_id = 0,
895 ss5_id = 32,
896 vger_id,
897 lx_id,
898 ss4_id,
899 scls_id,
900 sbook_id,
901 ss10_id = 64,
902 ss20_id,
903 ss600mp_id,
904 ss1000_id = 96,
905 ss2000_id,
906 };
907
908 static const struct sun4m_hwdef sun4m_hwdefs[] = {
909 /* SS-5 */
910 {
911 .iommu_base = 0x10000000,
912 .tcx_base = 0x50000000,
913 .cs_base = 0x6c000000,
914 .slavio_base = 0x70000000,
915 .ms_kb_base = 0x71000000,
916 .serial_base = 0x71100000,
917 .nvram_base = 0x71200000,
918 .fd_base = 0x71400000,
919 .counter_base = 0x71d00000,
920 .intctl_base = 0x71e00000,
921 .idreg_base = 0x78000000,
922 .dma_base = 0x78400000,
923 .esp_base = 0x78800000,
924 .le_base = 0x78c00000,
925 .apc_base = 0x6a000000,
926 .aux1_base = 0x71900000,
927 .aux2_base = 0x71910000,
928 .nvram_machine_id = 0x80,
929 .machine_id = ss5_id,
930 .iommu_version = 0x05000000,
931 .max_mem = 0x10000000,
932 .default_cpu_model = "Fujitsu MB86904",
933 },
934 /* SS-10 */
935 {
936 .iommu_base = 0xfe0000000ULL,
937 .tcx_base = 0xe20000000ULL,
938 .slavio_base = 0xff0000000ULL,
939 .ms_kb_base = 0xff1000000ULL,
940 .serial_base = 0xff1100000ULL,
941 .nvram_base = 0xff1200000ULL,
942 .fd_base = 0xff1700000ULL,
943 .counter_base = 0xff1300000ULL,
944 .intctl_base = 0xff1400000ULL,
945 .idreg_base = 0xef0000000ULL,
946 .dma_base = 0xef0400000ULL,
947 .esp_base = 0xef0800000ULL,
948 .le_base = 0xef0c00000ULL,
949 .apc_base = 0xefa000000ULL, // XXX should not exist
950 .aux1_base = 0xff1800000ULL,
951 .aux2_base = 0xff1a01000ULL,
952 .ecc_base = 0xf00000000ULL,
953 .ecc_version = 0x10000000, // version 0, implementation 1
954 .nvram_machine_id = 0x72,
955 .machine_id = ss10_id,
956 .iommu_version = 0x03000000,
957 .max_mem = 0xf00000000ULL,
958 .default_cpu_model = "TI SuperSparc II",
959 },
960 /* SS-600MP */
961 {
962 .iommu_base = 0xfe0000000ULL,
963 .tcx_base = 0xe20000000ULL,
964 .slavio_base = 0xff0000000ULL,
965 .ms_kb_base = 0xff1000000ULL,
966 .serial_base = 0xff1100000ULL,
967 .nvram_base = 0xff1200000ULL,
968 .counter_base = 0xff1300000ULL,
969 .intctl_base = 0xff1400000ULL,
970 .dma_base = 0xef0081000ULL,
971 .esp_base = 0xef0080000ULL,
972 .le_base = 0xef0060000ULL,
973 .apc_base = 0xefa000000ULL, // XXX should not exist
974 .aux1_base = 0xff1800000ULL,
975 .aux2_base = 0xff1a01000ULL, // XXX should not exist
976 .ecc_base = 0xf00000000ULL,
977 .ecc_version = 0x00000000, // version 0, implementation 0
978 .nvram_machine_id = 0x71,
979 .machine_id = ss600mp_id,
980 .iommu_version = 0x01000000,
981 .max_mem = 0xf00000000ULL,
982 .default_cpu_model = "TI SuperSparc II",
983 },
984 /* SS-20 */
985 {
986 .iommu_base = 0xfe0000000ULL,
987 .tcx_base = 0xe20000000ULL,
988 .slavio_base = 0xff0000000ULL,
989 .ms_kb_base = 0xff1000000ULL,
990 .serial_base = 0xff1100000ULL,
991 .nvram_base = 0xff1200000ULL,
992 .fd_base = 0xff1700000ULL,
993 .counter_base = 0xff1300000ULL,
994 .intctl_base = 0xff1400000ULL,
995 .idreg_base = 0xef0000000ULL,
996 .dma_base = 0xef0400000ULL,
997 .esp_base = 0xef0800000ULL,
998 .le_base = 0xef0c00000ULL,
999 .apc_base = 0xefa000000ULL, // XXX should not exist
1000 .aux1_base = 0xff1800000ULL,
1001 .aux2_base = 0xff1a01000ULL,
1002 .ecc_base = 0xf00000000ULL,
1003 .ecc_version = 0x20000000, // version 0, implementation 2
1004 .nvram_machine_id = 0x72,
1005 .machine_id = ss20_id,
1006 .iommu_version = 0x13000000,
1007 .max_mem = 0xf00000000ULL,
1008 .default_cpu_model = "TI SuperSparc II",
1009 },
1010 /* Voyager */
1011 {
1012 .iommu_base = 0x10000000,
1013 .tcx_base = 0x50000000,
1014 .slavio_base = 0x70000000,
1015 .ms_kb_base = 0x71000000,
1016 .serial_base = 0x71100000,
1017 .nvram_base = 0x71200000,
1018 .fd_base = 0x71400000,
1019 .counter_base = 0x71d00000,
1020 .intctl_base = 0x71e00000,
1021 .idreg_base = 0x78000000,
1022 .dma_base = 0x78400000,
1023 .esp_base = 0x78800000,
1024 .le_base = 0x78c00000,
1025 .apc_base = 0x71300000, // pmc
1026 .aux1_base = 0x71900000,
1027 .aux2_base = 0x71910000,
1028 .nvram_machine_id = 0x80,
1029 .machine_id = vger_id,
1030 .iommu_version = 0x05000000,
1031 .max_mem = 0x10000000,
1032 .default_cpu_model = "Fujitsu MB86904",
1033 },
1034 /* LX */
1035 {
1036 .iommu_base = 0x10000000,
1037 .tcx_base = 0x50000000,
1038 .slavio_base = 0x70000000,
1039 .ms_kb_base = 0x71000000,
1040 .serial_base = 0x71100000,
1041 .nvram_base = 0x71200000,
1042 .fd_base = 0x71400000,
1043 .counter_base = 0x71d00000,
1044 .intctl_base = 0x71e00000,
1045 .idreg_base = 0x78000000,
1046 .dma_base = 0x78400000,
1047 .esp_base = 0x78800000,
1048 .le_base = 0x78c00000,
1049 .aux1_base = 0x71900000,
1050 .aux2_base = 0x71910000,
1051 .nvram_machine_id = 0x80,
1052 .machine_id = lx_id,
1053 .iommu_version = 0x04000000,
1054 .max_mem = 0x10000000,
1055 .default_cpu_model = "TI MicroSparc I",
1056 },
1057 /* SS-4 */
1058 {
1059 .iommu_base = 0x10000000,
1060 .tcx_base = 0x50000000,
1061 .cs_base = 0x6c000000,
1062 .slavio_base = 0x70000000,
1063 .ms_kb_base = 0x71000000,
1064 .serial_base = 0x71100000,
1065 .nvram_base = 0x71200000,
1066 .fd_base = 0x71400000,
1067 .counter_base = 0x71d00000,
1068 .intctl_base = 0x71e00000,
1069 .idreg_base = 0x78000000,
1070 .dma_base = 0x78400000,
1071 .esp_base = 0x78800000,
1072 .le_base = 0x78c00000,
1073 .apc_base = 0x6a000000,
1074 .aux1_base = 0x71900000,
1075 .aux2_base = 0x71910000,
1076 .nvram_machine_id = 0x80,
1077 .machine_id = ss4_id,
1078 .iommu_version = 0x05000000,
1079 .max_mem = 0x10000000,
1080 .default_cpu_model = "Fujitsu MB86904",
1081 },
1082 /* SPARCClassic */
1083 {
1084 .iommu_base = 0x10000000,
1085 .tcx_base = 0x50000000,
1086 .slavio_base = 0x70000000,
1087 .ms_kb_base = 0x71000000,
1088 .serial_base = 0x71100000,
1089 .nvram_base = 0x71200000,
1090 .fd_base = 0x71400000,
1091 .counter_base = 0x71d00000,
1092 .intctl_base = 0x71e00000,
1093 .idreg_base = 0x78000000,
1094 .dma_base = 0x78400000,
1095 .esp_base = 0x78800000,
1096 .le_base = 0x78c00000,
1097 .apc_base = 0x6a000000,
1098 .aux1_base = 0x71900000,
1099 .aux2_base = 0x71910000,
1100 .nvram_machine_id = 0x80,
1101 .machine_id = scls_id,
1102 .iommu_version = 0x05000000,
1103 .max_mem = 0x10000000,
1104 .default_cpu_model = "TI MicroSparc I",
1105 },
1106 /* SPARCbook */
1107 {
1108 .iommu_base = 0x10000000,
1109 .tcx_base = 0x50000000, // XXX
1110 .slavio_base = 0x70000000,
1111 .ms_kb_base = 0x71000000,
1112 .serial_base = 0x71100000,
1113 .nvram_base = 0x71200000,
1114 .fd_base = 0x71400000,
1115 .counter_base = 0x71d00000,
1116 .intctl_base = 0x71e00000,
1117 .idreg_base = 0x78000000,
1118 .dma_base = 0x78400000,
1119 .esp_base = 0x78800000,
1120 .le_base = 0x78c00000,
1121 .apc_base = 0x6a000000,
1122 .aux1_base = 0x71900000,
1123 .aux2_base = 0x71910000,
1124 .nvram_machine_id = 0x80,
1125 .machine_id = sbook_id,
1126 .iommu_version = 0x05000000,
1127 .max_mem = 0x10000000,
1128 .default_cpu_model = "TI MicroSparc I",
1129 },
1130 };
1131
1132 /* SPARCstation 5 hardware initialisation */
1133 static void ss5_init(ram_addr_t RAM_size,
1134 const char *boot_device,
1135 const char *kernel_filename, const char *kernel_cmdline,
1136 const char *initrd_filename, const char *cpu_model)
1137 {
1138 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1139 kernel_cmdline, initrd_filename, cpu_model);
1140 }
1141
1142 /* SPARCstation 10 hardware initialisation */
1143 static void ss10_init(ram_addr_t RAM_size,
1144 const char *boot_device,
1145 const char *kernel_filename, const char *kernel_cmdline,
1146 const char *initrd_filename, const char *cpu_model)
1147 {
1148 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1149 kernel_cmdline, initrd_filename, cpu_model);
1150 }
1151
1152 /* SPARCserver 600MP hardware initialisation */
1153 static void ss600mp_init(ram_addr_t RAM_size,
1154 const char *boot_device,
1155 const char *kernel_filename,
1156 const char *kernel_cmdline,
1157 const char *initrd_filename, const char *cpu_model)
1158 {
1159 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1160 kernel_cmdline, initrd_filename, cpu_model);
1161 }
1162
1163 /* SPARCstation 20 hardware initialisation */
1164 static void ss20_init(ram_addr_t RAM_size,
1165 const char *boot_device,
1166 const char *kernel_filename, const char *kernel_cmdline,
1167 const char *initrd_filename, const char *cpu_model)
1168 {
1169 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1170 kernel_cmdline, initrd_filename, cpu_model);
1171 }
1172
1173 /* SPARCstation Voyager hardware initialisation */
1174 static void vger_init(ram_addr_t RAM_size,
1175 const char *boot_device,
1176 const char *kernel_filename, const char *kernel_cmdline,
1177 const char *initrd_filename, const char *cpu_model)
1178 {
1179 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1180 kernel_cmdline, initrd_filename, cpu_model);
1181 }
1182
1183 /* SPARCstation LX hardware initialisation */
1184 static void ss_lx_init(ram_addr_t RAM_size,
1185 const char *boot_device,
1186 const char *kernel_filename, const char *kernel_cmdline,
1187 const char *initrd_filename, const char *cpu_model)
1188 {
1189 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1190 kernel_cmdline, initrd_filename, cpu_model);
1191 }
1192
1193 /* SPARCstation 4 hardware initialisation */
1194 static void ss4_init(ram_addr_t RAM_size,
1195 const char *boot_device,
1196 const char *kernel_filename, const char *kernel_cmdline,
1197 const char *initrd_filename, const char *cpu_model)
1198 {
1199 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1200 kernel_cmdline, initrd_filename, cpu_model);
1201 }
1202
1203 /* SPARCClassic hardware initialisation */
1204 static void scls_init(ram_addr_t RAM_size,
1205 const char *boot_device,
1206 const char *kernel_filename, const char *kernel_cmdline,
1207 const char *initrd_filename, const char *cpu_model)
1208 {
1209 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1210 kernel_cmdline, initrd_filename, cpu_model);
1211 }
1212
1213 /* SPARCbook hardware initialisation */
1214 static void sbook_init(ram_addr_t RAM_size,
1215 const char *boot_device,
1216 const char *kernel_filename, const char *kernel_cmdline,
1217 const char *initrd_filename, const char *cpu_model)
1218 {
1219 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1220 kernel_cmdline, initrd_filename, cpu_model);
1221 }
1222
1223 static QEMUMachine ss5_machine = {
1224 .name = "SS-5",
1225 .desc = "Sun4m platform, SPARCstation 5",
1226 .init = ss5_init,
1227 .use_scsi = 1,
1228 .is_default = 1,
1229 };
1230
1231 static QEMUMachine ss10_machine = {
1232 .name = "SS-10",
1233 .desc = "Sun4m platform, SPARCstation 10",
1234 .init = ss10_init,
1235 .use_scsi = 1,
1236 .max_cpus = 4,
1237 };
1238
1239 static QEMUMachine ss600mp_machine = {
1240 .name = "SS-600MP",
1241 .desc = "Sun4m platform, SPARCserver 600MP",
1242 .init = ss600mp_init,
1243 .use_scsi = 1,
1244 .max_cpus = 4,
1245 };
1246
1247 static QEMUMachine ss20_machine = {
1248 .name = "SS-20",
1249 .desc = "Sun4m platform, SPARCstation 20",
1250 .init = ss20_init,
1251 .use_scsi = 1,
1252 .max_cpus = 4,
1253 };
1254
1255 static QEMUMachine voyager_machine = {
1256 .name = "Voyager",
1257 .desc = "Sun4m platform, SPARCstation Voyager",
1258 .init = vger_init,
1259 .use_scsi = 1,
1260 };
1261
1262 static QEMUMachine ss_lx_machine = {
1263 .name = "LX",
1264 .desc = "Sun4m platform, SPARCstation LX",
1265 .init = ss_lx_init,
1266 .use_scsi = 1,
1267 };
1268
1269 static QEMUMachine ss4_machine = {
1270 .name = "SS-4",
1271 .desc = "Sun4m platform, SPARCstation 4",
1272 .init = ss4_init,
1273 .use_scsi = 1,
1274 };
1275
1276 static QEMUMachine scls_machine = {
1277 .name = "SPARCClassic",
1278 .desc = "Sun4m platform, SPARCClassic",
1279 .init = scls_init,
1280 .use_scsi = 1,
1281 };
1282
1283 static QEMUMachine sbook_machine = {
1284 .name = "SPARCbook",
1285 .desc = "Sun4m platform, SPARCbook",
1286 .init = sbook_init,
1287 .use_scsi = 1,
1288 };
1289
1290 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1291 /* SS-1000 */
1292 {
1293 .iounit_bases = {
1294 0xfe0200000ULL,
1295 0xfe1200000ULL,
1296 0xfe2200000ULL,
1297 0xfe3200000ULL,
1298 -1,
1299 },
1300 .tcx_base = 0x820000000ULL,
1301 .slavio_base = 0xf00000000ULL,
1302 .ms_kb_base = 0xf00240000ULL,
1303 .serial_base = 0xf00200000ULL,
1304 .nvram_base = 0xf00280000ULL,
1305 .counter_base = 0xf00300000ULL,
1306 .espdma_base = 0x800081000ULL,
1307 .esp_base = 0x800080000ULL,
1308 .ledma_base = 0x800040000ULL,
1309 .le_base = 0x800060000ULL,
1310 .sbi_base = 0xf02800000ULL,
1311 .nvram_machine_id = 0x80,
1312 .machine_id = ss1000_id,
1313 .iounit_version = 0x03000000,
1314 .max_mem = 0xf00000000ULL,
1315 .default_cpu_model = "TI SuperSparc II",
1316 },
1317 /* SS-2000 */
1318 {
1319 .iounit_bases = {
1320 0xfe0200000ULL,
1321 0xfe1200000ULL,
1322 0xfe2200000ULL,
1323 0xfe3200000ULL,
1324 0xfe4200000ULL,
1325 },
1326 .tcx_base = 0x820000000ULL,
1327 .slavio_base = 0xf00000000ULL,
1328 .ms_kb_base = 0xf00240000ULL,
1329 .serial_base = 0xf00200000ULL,
1330 .nvram_base = 0xf00280000ULL,
1331 .counter_base = 0xf00300000ULL,
1332 .espdma_base = 0x800081000ULL,
1333 .esp_base = 0x800080000ULL,
1334 .ledma_base = 0x800040000ULL,
1335 .le_base = 0x800060000ULL,
1336 .sbi_base = 0xf02800000ULL,
1337 .nvram_machine_id = 0x80,
1338 .machine_id = ss2000_id,
1339 .iounit_version = 0x03000000,
1340 .max_mem = 0xf00000000ULL,
1341 .default_cpu_model = "TI SuperSparc II",
1342 },
1343 };
1344
1345 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1346 {
1347 DeviceState *dev;
1348 SysBusDevice *s;
1349 unsigned int i;
1350
1351 dev = qdev_create(NULL, "sbi");
1352 qdev_init(dev);
1353
1354 s = sysbus_from_qdev(dev);
1355
1356 for (i = 0; i < MAX_CPUS; i++) {
1357 sysbus_connect_irq(s, i, *parent_irq[i]);
1358 }
1359
1360 sysbus_mmio_map(s, 0, addr);
1361
1362 return dev;
1363 }
1364
1365 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1366 const char *boot_device,
1367 const char *kernel_filename,
1368 const char *kernel_cmdline,
1369 const char *initrd_filename, const char *cpu_model)
1370 {
1371 CPUState *envs[MAX_CPUS];
1372 unsigned int i;
1373 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1374 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1375 espdma_irq, ledma_irq;
1376 qemu_irq esp_reset;
1377 unsigned long kernel_size;
1378 void *fw_cfg;
1379 DeviceState *dev;
1380
1381 /* init CPUs */
1382 if (!cpu_model)
1383 cpu_model = hwdef->default_cpu_model;
1384
1385 for(i = 0; i < smp_cpus; i++) {
1386 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1387 }
1388
1389 for (i = smp_cpus; i < MAX_CPUS; i++)
1390 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1391
1392 /* set up devices */
1393 ram_init(0, RAM_size, hwdef->max_mem);
1394
1395 prom_init(hwdef->slavio_base, bios_name);
1396
1397 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1398
1399 for (i = 0; i < 32; i++) {
1400 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1401 }
1402 for (i = 0; i < MAX_CPUS; i++) {
1403 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1404 }
1405
1406 for (i = 0; i < MAX_IOUNITS; i++)
1407 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1408 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1409 hwdef->iounit_version,
1410 sbi_irq[0]);
1411
1412 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1413 iounits[0], &espdma_irq);
1414
1415 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1416 iounits[0], &ledma_irq);
1417
1418 if (graphic_depth != 8 && graphic_depth != 24) {
1419 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1420 exit (1);
1421 }
1422 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1423 graphic_depth);
1424
1425 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1426
1427 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1428
1429 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1430
1431 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1432 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1433 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1434 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1435 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1436 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1437
1438 if (drive_get_max_bus(IF_SCSI) > 0) {
1439 fprintf(stderr, "qemu: too many SCSI bus\n");
1440 exit(1);
1441 }
1442
1443 esp_reset = qdev_get_gpio_in(espdma, 0);
1444 esp_init(hwdef->esp_base, 2,
1445 espdma_memory_read, espdma_memory_write,
1446 espdma, espdma_irq, &esp_reset);
1447
1448 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1449 RAM_size);
1450
1451 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1452 boot_device, RAM_size, kernel_size, graphic_width,
1453 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1454 "Sun4d");
1455
1456 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1457 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1458 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1459 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1460 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1461 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1462 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1463 if (kernel_cmdline) {
1464 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1465 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1466 } else {
1467 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1468 }
1469 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1470 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1471 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1472 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1473 }
1474
1475 /* SPARCserver 1000 hardware initialisation */
1476 static void ss1000_init(ram_addr_t RAM_size,
1477 const char *boot_device,
1478 const char *kernel_filename, const char *kernel_cmdline,
1479 const char *initrd_filename, const char *cpu_model)
1480 {
1481 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1482 kernel_cmdline, initrd_filename, cpu_model);
1483 }
1484
1485 /* SPARCcenter 2000 hardware initialisation */
1486 static void ss2000_init(ram_addr_t RAM_size,
1487 const char *boot_device,
1488 const char *kernel_filename, const char *kernel_cmdline,
1489 const char *initrd_filename, const char *cpu_model)
1490 {
1491 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1492 kernel_cmdline, initrd_filename, cpu_model);
1493 }
1494
1495 static QEMUMachine ss1000_machine = {
1496 .name = "SS-1000",
1497 .desc = "Sun4d platform, SPARCserver 1000",
1498 .init = ss1000_init,
1499 .use_scsi = 1,
1500 .max_cpus = 8,
1501 };
1502
1503 static QEMUMachine ss2000_machine = {
1504 .name = "SS-2000",
1505 .desc = "Sun4d platform, SPARCcenter 2000",
1506 .init = ss2000_init,
1507 .use_scsi = 1,
1508 .max_cpus = 20,
1509 };
1510
1511 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1512 /* SS-2 */
1513 {
1514 .iommu_base = 0xf8000000,
1515 .tcx_base = 0xfe000000,
1516 .slavio_base = 0xf6000000,
1517 .intctl_base = 0xf5000000,
1518 .counter_base = 0xf3000000,
1519 .ms_kb_base = 0xf0000000,
1520 .serial_base = 0xf1000000,
1521 .nvram_base = 0xf2000000,
1522 .fd_base = 0xf7200000,
1523 .dma_base = 0xf8400000,
1524 .esp_base = 0xf8800000,
1525 .le_base = 0xf8c00000,
1526 .aux1_base = 0xf7400003,
1527 .nvram_machine_id = 0x55,
1528 .machine_id = ss2_id,
1529 .max_mem = 0x10000000,
1530 .default_cpu_model = "Cypress CY7C601",
1531 },
1532 };
1533
1534 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1535 qemu_irq *parent_irq)
1536 {
1537 DeviceState *dev;
1538 SysBusDevice *s;
1539 unsigned int i;
1540
1541 dev = qdev_create(NULL, "sun4c_intctl");
1542 qdev_init(dev);
1543
1544 s = sysbus_from_qdev(dev);
1545
1546 for (i = 0; i < MAX_PILS; i++) {
1547 sysbus_connect_irq(s, i, parent_irq[i]);
1548 }
1549 sysbus_mmio_map(s, 0, addr);
1550
1551 return dev;
1552 }
1553
1554 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1555 const char *boot_device,
1556 const char *kernel_filename,
1557 const char *kernel_cmdline,
1558 const char *initrd_filename, const char *cpu_model)
1559 {
1560 CPUState *env;
1561 void *iommu, *espdma, *ledma, *nvram;
1562 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1563 qemu_irq esp_reset;
1564 qemu_irq fdc_tc;
1565 unsigned long kernel_size;
1566 BlockDriverState *fd[MAX_FD];
1567 void *fw_cfg;
1568 DeviceState *dev;
1569 unsigned int i;
1570 DriveInfo *dinfo;
1571
1572 /* init CPU */
1573 if (!cpu_model)
1574 cpu_model = hwdef->default_cpu_model;
1575
1576 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1577
1578 /* set up devices */
1579 ram_init(0, RAM_size, hwdef->max_mem);
1580
1581 prom_init(hwdef->slavio_base, bios_name);
1582
1583 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1584
1585 for (i = 0; i < 8; i++) {
1586 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1587 }
1588
1589 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1590 slavio_irq[1]);
1591
1592 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1593 iommu, &espdma_irq);
1594
1595 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1596 slavio_irq[3], iommu, &ledma_irq);
1597
1598 if (graphic_depth != 8 && graphic_depth != 24) {
1599 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1600 exit (1);
1601 }
1602 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1603 graphic_depth);
1604
1605 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1606
1607 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1608
1609 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1610 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1611 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1612 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1613 escc_init(hwdef->serial_base, slavio_irq[1],
1614 slavio_irq[1], serial_hds[0], serial_hds[1],
1615 ESCC_CLOCK, 1);
1616
1617 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1618
1619 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1620 /* there is zero or one floppy drive */
1621 memset(fd, 0, sizeof(fd));
1622 dinfo = drive_get(IF_FLOPPY, 0, 0);
1623 if (dinfo)
1624 fd[0] = dinfo->bdrv;
1625
1626 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1627 &fdc_tc);
1628 }
1629
1630 if (drive_get_max_bus(IF_SCSI) > 0) {
1631 fprintf(stderr, "qemu: too many SCSI bus\n");
1632 exit(1);
1633 }
1634
1635 esp_reset = qdev_get_gpio_in(espdma, 0);
1636 esp_init(hwdef->esp_base, 2,
1637 espdma_memory_read, espdma_memory_write,
1638 espdma, espdma_irq, &esp_reset);
1639
1640 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1641 RAM_size);
1642
1643 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1644 boot_device, RAM_size, kernel_size, graphic_width,
1645 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1646 "Sun4c");
1647
1648 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1649 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1650 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1651 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1652 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1653 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1654 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1655 if (kernel_cmdline) {
1656 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1657 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1658 } else {
1659 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1660 }
1661 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1662 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1663 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1664 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1665 }
1666
1667 /* SPARCstation 2 hardware initialisation */
1668 static void ss2_init(ram_addr_t RAM_size,
1669 const char *boot_device,
1670 const char *kernel_filename, const char *kernel_cmdline,
1671 const char *initrd_filename, const char *cpu_model)
1672 {
1673 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1674 kernel_cmdline, initrd_filename, cpu_model);
1675 }
1676
1677 static QEMUMachine ss2_machine = {
1678 .name = "SS-2",
1679 .desc = "Sun4c platform, SPARCstation 2",
1680 .init = ss2_init,
1681 .use_scsi = 1,
1682 };
1683
1684 static void ss2_machine_init(void)
1685 {
1686 qemu_register_machine(&ss5_machine);
1687 qemu_register_machine(&ss10_machine);
1688 qemu_register_machine(&ss600mp_machine);
1689 qemu_register_machine(&ss20_machine);
1690 qemu_register_machine(&voyager_machine);
1691 qemu_register_machine(&ss_lx_machine);
1692 qemu_register_machine(&ss4_machine);
1693 qemu_register_machine(&scls_machine);
1694 qemu_register_machine(&sbook_machine);
1695 qemu_register_machine(&ss1000_machine);
1696 qemu_register_machine(&ss2000_machine);
1697 qemu_register_machine(&ss2_machine);
1698 }
1699
1700 machine_init(ss2_machine_init);
Qemu copy for testing