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Sparc32: remove IRQ numbers from hwdef
[qemu.git] / hw / sun4m.c
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "qdev-addr.h"
40
41 //#define DEBUG_IRQ
42
43 /*
44 * Sun4m architecture was used in the following machines:
45 *
46 * SPARCserver 6xxMP/xx
47 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
48 * SPARCclassic X (4/10)
49 * SPARCstation LX/ZX (4/30)
50 * SPARCstation Voyager
51 * SPARCstation 10/xx, SPARCserver 10/xx
52 * SPARCstation 5, SPARCserver 5
53 * SPARCstation 20/xx, SPARCserver 20
54 * SPARCstation 4
55 *
56 * Sun4d architecture was used in the following machines:
57 *
58 * SPARCcenter 2000
59 * SPARCserver 1000
60 *
61 * Sun4c architecture was used in the following machines:
62 * SPARCstation 1/1+, SPARCserver 1/1+
63 * SPARCstation SLC
64 * SPARCstation IPC
65 * SPARCstation ELC
66 * SPARCstation IPX
67 *
68 * See for example: http://www.sunhelp.org/faq/sunref1.html
69 */
70
71 #ifdef DEBUG_IRQ
72 #define DPRINTF(fmt, ...) \
73 do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
74 #else
75 #define DPRINTF(fmt, ...)
76 #endif
77
78 #define KERNEL_LOAD_ADDR 0x00004000
79 #define CMDLINE_ADDR 0x007ff000
80 #define INITRD_LOAD_ADDR 0x00800000
81 #define PROM_SIZE_MAX (1024 * 1024)
82 #define PROM_VADDR 0xffd00000
83 #define PROM_FILENAME "openbios-sparc32"
84 #define CFG_ADDR 0xd00000510ULL
85 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
86
87 #define MAX_CPUS 16
88 #define MAX_PILS 16
89
90 #define ESCC_CLOCK 4915200
91
92 struct sun4m_hwdef {
93 target_phys_addr_t iommu_base, slavio_base;
94 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
95 target_phys_addr_t serial_base, fd_base;
96 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
97 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
98 target_phys_addr_t ecc_base;
99 uint32_t ecc_version;
100 long vram_size, nvram_size;
101 uint8_t nvram_machine_id;
102 uint16_t machine_id;
103 uint32_t iommu_version;
104 uint64_t max_mem;
105 const char * const default_cpu_model;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 unsigned long vram_size, nvram_size;
119 uint8_t nvram_machine_id;
120 uint16_t machine_id;
121 uint32_t iounit_version;
122 uint64_t max_mem;
123 const char * const default_cpu_model;
124 };
125
126 struct sun4c_hwdef {
127 target_phys_addr_t iommu_base, slavio_base;
128 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
129 target_phys_addr_t serial_base, fd_base;
130 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
131 target_phys_addr_t tcx_base, aux1_base;
132 long vram_size, nvram_size;
133 uint8_t nvram_machine_id;
134 uint16_t machine_id;
135 uint32_t iommu_version;
136 uint64_t max_mem;
137 const char * const default_cpu_model;
138 };
139
140 int DMA_get_channel_mode (int nchan)
141 {
142 return 0;
143 }
144 int DMA_read_memory (int nchan, void *buf, int pos, int size)
145 {
146 return 0;
147 }
148 int DMA_write_memory (int nchan, void *buf, int pos, int size)
149 {
150 return 0;
151 }
152 void DMA_hold_DREQ (int nchan) {}
153 void DMA_release_DREQ (int nchan) {}
154 void DMA_schedule(int nchan) {}
155 void DMA_init (int high_page_enable) {}
156 void DMA_register_channel (int nchan,
157 DMA_transfer_handler transfer_handler,
158 void *opaque)
159 {
160 }
161
162 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
163 {
164 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
165 return 0;
166 }
167
168 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
169 const char *boot_devices, ram_addr_t RAM_size,
170 uint32_t kernel_size,
171 int width, int height, int depth,
172 int nvram_machine_id, const char *arch)
173 {
174 unsigned int i;
175 uint32_t start, end;
176 uint8_t image[0x1ff0];
177 struct OpenBIOS_nvpart_v1 *part_header;
178
179 memset(image, '\0', sizeof(image));
180
181 start = 0;
182
183 // OpenBIOS nvram variables
184 // Variable partition
185 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
186 part_header->signature = OPENBIOS_PART_SYSTEM;
187 pstrcpy(part_header->name, sizeof(part_header->name), "system");
188
189 end = start + sizeof(struct OpenBIOS_nvpart_v1);
190 for (i = 0; i < nb_prom_envs; i++)
191 end = OpenBIOS_set_var(image, end, prom_envs[i]);
192
193 // End marker
194 image[end++] = '\0';
195
196 end = start + ((end - start + 15) & ~15);
197 OpenBIOS_finish_partition(part_header, end - start);
198
199 // free partition
200 start = end;
201 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
202 part_header->signature = OPENBIOS_PART_FREE;
203 pstrcpy(part_header->name, sizeof(part_header->name), "free");
204
205 end = 0x1fd0;
206 OpenBIOS_finish_partition(part_header, end - start);
207
208 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
209 nvram_machine_id);
210
211 for (i = 0; i < sizeof(image); i++)
212 m48t59_write(nvram, i, image[i]);
213 }
214
215 static void *slavio_intctl;
216
217 void pic_info(Monitor *mon)
218 {
219 if (slavio_intctl)
220 slavio_pic_info(mon, slavio_intctl);
221 }
222
223 void irq_info(Monitor *mon)
224 {
225 if (slavio_intctl)
226 slavio_irq_info(mon, slavio_intctl);
227 }
228
229 void cpu_check_irqs(CPUState *env)
230 {
231 if (env->pil_in && (env->interrupt_index == 0 ||
232 (env->interrupt_index & ~15) == TT_EXTINT)) {
233 unsigned int i;
234
235 for (i = 15; i > 0; i--) {
236 if (env->pil_in & (1 << i)) {
237 int old_interrupt = env->interrupt_index;
238
239 env->interrupt_index = TT_EXTINT | i;
240 if (old_interrupt != env->interrupt_index) {
241 DPRINTF("Set CPU IRQ %d\n", i);
242 cpu_interrupt(env, CPU_INTERRUPT_HARD);
243 }
244 break;
245 }
246 }
247 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
248 DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
249 env->interrupt_index = 0;
250 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
251 }
252 }
253
254 static void cpu_set_irq(void *opaque, int irq, int level)
255 {
256 CPUState *env = opaque;
257
258 if (level) {
259 DPRINTF("Raise CPU IRQ %d\n", irq);
260 env->halted = 0;
261 env->pil_in |= 1 << irq;
262 cpu_check_irqs(env);
263 } else {
264 DPRINTF("Lower CPU IRQ %d\n", irq);
265 env->pil_in &= ~(1 << irq);
266 cpu_check_irqs(env);
267 }
268 }
269
270 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
271 {
272 }
273
274 static void *slavio_misc;
275
276 void qemu_system_powerdown(void)
277 {
278 slavio_set_power_fail(slavio_misc, 1);
279 }
280
281 static void main_cpu_reset(void *opaque)
282 {
283 CPUState *env = opaque;
284
285 cpu_reset(env);
286 env->halted = 0;
287 }
288
289 static void secondary_cpu_reset(void *opaque)
290 {
291 CPUState *env = opaque;
292
293 cpu_reset(env);
294 env->halted = 1;
295 }
296
297 static void cpu_halt_signal(void *opaque, int irq, int level)
298 {
299 if (level && cpu_single_env)
300 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
301 }
302
303 static unsigned long sun4m_load_kernel(const char *kernel_filename,
304 const char *initrd_filename,
305 ram_addr_t RAM_size)
306 {
307 int linux_boot;
308 unsigned int i;
309 long initrd_size, kernel_size;
310
311 linux_boot = (kernel_filename != NULL);
312
313 kernel_size = 0;
314 if (linux_boot) {
315 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
316 NULL);
317 if (kernel_size < 0)
318 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
319 RAM_size - KERNEL_LOAD_ADDR);
320 if (kernel_size < 0)
321 kernel_size = load_image_targphys(kernel_filename,
322 KERNEL_LOAD_ADDR,
323 RAM_size - KERNEL_LOAD_ADDR);
324 if (kernel_size < 0) {
325 fprintf(stderr, "qemu: could not load kernel '%s'\n",
326 kernel_filename);
327 exit(1);
328 }
329
330 /* load initrd */
331 initrd_size = 0;
332 if (initrd_filename) {
333 initrd_size = load_image_targphys(initrd_filename,
334 INITRD_LOAD_ADDR,
335 RAM_size - INITRD_LOAD_ADDR);
336 if (initrd_size < 0) {
337 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
338 initrd_filename);
339 exit(1);
340 }
341 }
342 if (initrd_size > 0) {
343 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
344 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
345 stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
346 stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
347 break;
348 }
349 }
350 }
351 }
352 return kernel_size;
353 }
354
355 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
356 {
357 DeviceState *dev;
358 SysBusDevice *s;
359
360 dev = qdev_create(NULL, "iommu");
361 qdev_prop_set_uint32(dev, "version", version);
362 qdev_init(dev);
363 s = sysbus_from_qdev(dev);
364 sysbus_connect_irq(s, 0, irq);
365 sysbus_mmio_map(s, 0, addr);
366
367 return s;
368 }
369
370 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
371 void *dma_opaque, qemu_irq irq, qemu_irq *reset)
372 {
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 qemu_check_nic_model(&nd_table[0], "lance");
377
378 dev = qdev_create(NULL, "lance");
379 dev->nd = nd;
380 qdev_prop_set_ptr(dev, "dma", dma_opaque);
381 qdev_init(dev);
382 s = sysbus_from_qdev(dev);
383 sysbus_mmio_map(s, 0, leaddr);
384 sysbus_connect_irq(s, 0, irq);
385 *reset = qdev_get_gpio_in(dev, 0);
386 }
387
388 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
389 target_phys_addr_t addrg,
390 qemu_irq **parent_irq,
391 unsigned int cputimer)
392 {
393 DeviceState *dev;
394 SysBusDevice *s;
395 unsigned int i, j;
396
397 dev = qdev_create(NULL, "slavio_intctl");
398 qdev_prop_set_uint32(dev, "cputimer_bit", cputimer);
399 qdev_init(dev);
400
401 s = sysbus_from_qdev(dev);
402
403 for (i = 0; i < MAX_CPUS; i++) {
404 for (j = 0; j < MAX_PILS; j++) {
405 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
406 }
407 }
408 sysbus_mmio_map(s, 0, addrg);
409 for (i = 0; i < MAX_CPUS; i++) {
410 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
411 }
412
413 return dev;
414 }
415
416 #define SYS_TIMER_OFFSET 0x10000ULL
417 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
418
419 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
420 qemu_irq *cpu_irqs, unsigned int num_cpus)
421 {
422 DeviceState *dev;
423 SysBusDevice *s;
424 unsigned int i;
425
426 dev = qdev_create(NULL, "slavio_timer");
427 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
428 qdev_init(dev);
429 s = sysbus_from_qdev(dev);
430 sysbus_connect_irq(s, 0, master_irq);
431 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
432
433 for (i = 0; i < MAX_CPUS; i++) {
434 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
435 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
436 }
437 }
438
439 #define MISC_LEDS 0x01600000
440 #define MISC_CFG 0x01800000
441 #define MISC_DIAG 0x01a00000
442 #define MISC_MDM 0x01b00000
443 #define MISC_SYS 0x01f00000
444
445 static void *slavio_misc_init(target_phys_addr_t base,
446 target_phys_addr_t aux1_base,
447 target_phys_addr_t aux2_base, qemu_irq irq,
448 qemu_irq fdc_tc)
449 {
450 DeviceState *dev;
451 SysBusDevice *s;
452
453 dev = qdev_create(NULL, "slavio_misc");
454 qdev_init(dev);
455 s = sysbus_from_qdev(dev);
456 if (base) {
457 /* 8 bit registers */
458 /* Slavio control */
459 sysbus_mmio_map(s, 0, base + MISC_CFG);
460 /* Diagnostics */
461 sysbus_mmio_map(s, 1, base + MISC_DIAG);
462 /* Modem control */
463 sysbus_mmio_map(s, 2, base + MISC_MDM);
464 /* 16 bit registers */
465 /* ss600mp diag LEDs */
466 sysbus_mmio_map(s, 3, base + MISC_LEDS);
467 /* 32 bit registers */
468 /* System control */
469 sysbus_mmio_map(s, 4, base + MISC_SYS);
470 }
471 if (aux1_base) {
472 /* AUX 1 (Misc System Functions) */
473 sysbus_mmio_map(s, 5, aux1_base);
474 }
475 if (aux2_base) {
476 /* AUX 2 (Software Powerdown Control) */
477 sysbus_mmio_map(s, 6, aux2_base);
478 }
479 sysbus_connect_irq(s, 0, irq);
480 sysbus_connect_irq(s, 1, fdc_tc);
481
482 return s;
483 }
484
485 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
486 {
487 DeviceState *dev;
488 SysBusDevice *s;
489
490 dev = qdev_create(NULL, "eccmemctl");
491 qdev_prop_set_uint32(dev, "version", version);
492 qdev_init(dev);
493 s = sysbus_from_qdev(dev);
494 sysbus_connect_irq(s, 0, irq);
495 sysbus_mmio_map(s, 0, base);
496 if (version == 0) { // SS-600MP only
497 sysbus_mmio_map(s, 1, base + 0x1000);
498 }
499 }
500
501 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
502 {
503 DeviceState *dev;
504 SysBusDevice *s;
505
506 dev = qdev_create(NULL, "apc");
507 qdev_init(dev);
508 s = sysbus_from_qdev(dev);
509 /* Power management (APC) XXX: not a Slavio device */
510 sysbus_mmio_map(s, 0, power_base);
511 sysbus_connect_irq(s, 0, cpu_halt);
512 }
513
514 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
515 int height, int depth)
516 {
517 DeviceState *dev;
518 SysBusDevice *s;
519
520 dev = qdev_create(NULL, "SUNW,tcx");
521 qdev_prop_set_taddr(dev, "addr", addr);
522 qdev_prop_set_uint32(dev, "vram_size", vram_size);
523 qdev_prop_set_uint16(dev, "width", width);
524 qdev_prop_set_uint16(dev, "height", height);
525 qdev_prop_set_uint16(dev, "depth", depth);
526 qdev_init(dev);
527 s = sysbus_from_qdev(dev);
528 /* 8-bit plane */
529 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
530 /* DAC */
531 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
532 /* TEC (dummy) */
533 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
534 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
535 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
536 if (depth == 24) {
537 /* 24-bit plane */
538 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
539 /* Control plane */
540 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
541 } else {
542 /* THC 8 bit (dummy) */
543 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
544 }
545 }
546
547 /* NCR89C100/MACIO Internal ID register */
548 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
549
550 static void idreg_init(target_phys_addr_t addr)
551 {
552 DeviceState *dev;
553 SysBusDevice *s;
554
555 dev = qdev_create(NULL, "macio_idreg");
556 qdev_init(dev);
557 s = sysbus_from_qdev(dev);
558
559 sysbus_mmio_map(s, 0, addr);
560 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
561 }
562
563 static void idreg_init1(SysBusDevice *dev)
564 {
565 ram_addr_t idreg_offset;
566
567 idreg_offset = qemu_ram_alloc(sizeof(idreg_data));
568 sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM);
569 }
570
571 static SysBusDeviceInfo idreg_info = {
572 .init = idreg_init1,
573 .qdev.name = "macio_idreg",
574 .qdev.size = sizeof(SysBusDevice),
575 };
576
577 static void idreg_register_devices(void)
578 {
579 sysbus_register_withprop(&idreg_info);
580 }
581
582 device_init(idreg_register_devices);
583
584 /* Boot PROM (OpenBIOS) */
585 static void prom_init(target_phys_addr_t addr, const char *bios_name)
586 {
587 DeviceState *dev;
588 SysBusDevice *s;
589 char *filename;
590 int ret;
591
592 dev = qdev_create(NULL, "openprom");
593 qdev_init(dev);
594 s = sysbus_from_qdev(dev);
595
596 sysbus_mmio_map(s, 0, addr);
597
598 /* load boot prom */
599 if (bios_name == NULL) {
600 bios_name = PROM_FILENAME;
601 }
602 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
603 if (filename) {
604 ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
605 if (ret < 0 || ret > PROM_SIZE_MAX) {
606 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
607 }
608 qemu_free(filename);
609 } else {
610 ret = -1;
611 }
612 if (ret < 0 || ret > PROM_SIZE_MAX) {
613 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
614 exit(1);
615 }
616 }
617
618 static void prom_init1(SysBusDevice *dev)
619 {
620 ram_addr_t prom_offset;
621
622 prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
623 sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
624 }
625
626 static SysBusDeviceInfo prom_info = {
627 .init = prom_init1,
628 .qdev.name = "openprom",
629 .qdev.size = sizeof(SysBusDevice),
630 .qdev.props = (Property[]) {
631 {/* end of property list */}
632 }
633 };
634
635 static void prom_register_devices(void)
636 {
637 sysbus_register_withprop(&prom_info);
638 }
639
640 device_init(prom_register_devices);
641
642 typedef struct RamDevice
643 {
644 SysBusDevice busdev;
645 uint64_t size;
646 } RamDevice;
647
648 /* System RAM */
649 static void ram_init1(SysBusDevice *dev)
650 {
651 ram_addr_t RAM_size, ram_offset;
652 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
653
654 RAM_size = d->size;
655
656 ram_offset = qemu_ram_alloc(RAM_size);
657 sysbus_init_mmio(dev, RAM_size, ram_offset);
658 }
659
660 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
661 uint64_t max_mem)
662 {
663 DeviceState *dev;
664 SysBusDevice *s;
665 RamDevice *d;
666
667 /* allocate RAM */
668 if ((uint64_t)RAM_size > max_mem) {
669 fprintf(stderr,
670 "qemu: Too much memory for this machine: %d, maximum %d\n",
671 (unsigned int)(RAM_size / (1024 * 1024)),
672 (unsigned int)(max_mem / (1024 * 1024)));
673 exit(1);
674 }
675 dev = qdev_create(NULL, "memory");
676 s = sysbus_from_qdev(dev);
677
678 d = FROM_SYSBUS(RamDevice, s);
679 d->size = RAM_size;
680 qdev_init(dev);
681
682 sysbus_mmio_map(s, 0, addr);
683 }
684
685 static SysBusDeviceInfo ram_info = {
686 .init = ram_init1,
687 .qdev.name = "memory",
688 .qdev.size = sizeof(RamDevice),
689 .qdev.props = (Property[]) {
690 {
691 .name = "size",
692 .info = &qdev_prop_uint64,
693 .offset = offsetof(RamDevice, size),
694 },
695 {/* end of property list */}
696 }
697 };
698
699 static void ram_register_devices(void)
700 {
701 sysbus_register_withprop(&ram_info);
702 }
703
704 device_init(ram_register_devices);
705
706 static CPUState *cpu_devinit(const char *cpu_model, unsigned int id,
707 uint64_t prom_addr, qemu_irq **cpu_irqs)
708 {
709 CPUState *env;
710
711 env = cpu_init(cpu_model);
712 if (!env) {
713 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
714 exit(1);
715 }
716
717 cpu_sparc_set_id(env, id);
718 if (id == 0) {
719 qemu_register_reset(main_cpu_reset, env);
720 } else {
721 qemu_register_reset(secondary_cpu_reset, env);
722 env->halted = 1;
723 }
724 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
725 env->prom_addr = prom_addr;
726
727 return env;
728 }
729
730 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
731 const char *boot_device,
732 const char *kernel_filename,
733 const char *kernel_cmdline,
734 const char *initrd_filename, const char *cpu_model)
735 {
736 CPUState *envs[MAX_CPUS];
737 unsigned int i;
738 void *iommu, *espdma, *ledma, *nvram;
739 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
740 espdma_irq, ledma_irq;
741 qemu_irq *esp_reset, *le_reset;
742 qemu_irq fdc_tc;
743 qemu_irq *cpu_halt;
744 unsigned long kernel_size;
745 BlockDriverState *fd[MAX_FD];
746 void *fw_cfg;
747 DeviceState *dev;
748 DriveInfo *dinfo;
749
750 /* init CPUs */
751 if (!cpu_model)
752 cpu_model = hwdef->default_cpu_model;
753
754 for(i = 0; i < smp_cpus; i++) {
755 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
756 }
757
758 for (i = smp_cpus; i < MAX_CPUS; i++)
759 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
760
761
762 /* set up devices */
763 ram_init(0, RAM_size, hwdef->max_mem);
764
765 prom_init(hwdef->slavio_base, bios_name);
766
767 dev = slavio_intctl_init(hwdef->intctl_base,
768 hwdef->intctl_base + 0x10000ULL,
769 cpu_irqs,
770 7);
771
772 for (i = 0; i < 32; i++) {
773 slavio_irq[i] = qdev_get_gpio_in(dev, i);
774 }
775 for (i = 0; i < MAX_CPUS; i++) {
776 slavio_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
777 }
778
779 if (hwdef->idreg_base) {
780 idreg_init(hwdef->idreg_base);
781 }
782
783 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
784 slavio_irq[30]);
785
786 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
787 iommu, &espdma_irq, &esp_reset);
788
789 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
790 slavio_irq[16], iommu, &ledma_irq,
791 &le_reset);
792
793 if (graphic_depth != 8 && graphic_depth != 24) {
794 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
795 exit (1);
796 }
797 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
798 graphic_depth);
799
800 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
801
802 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
803 hwdef->nvram_size, 8);
804
805 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
806
807 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
808 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
809 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
810 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
811 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
812 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
813
814 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
815 slavio_misc = slavio_misc_init(hwdef->slavio_base,
816 hwdef->aux1_base, hwdef->aux2_base,
817 slavio_irq[30], fdc_tc);
818 if (hwdef->apc_base) {
819 apc_init(hwdef->apc_base, cpu_halt[0]);
820 }
821
822 if (hwdef->fd_base) {
823 /* there is zero or one floppy drive */
824 memset(fd, 0, sizeof(fd));
825 dinfo = drive_get(IF_FLOPPY, 0, 0);
826 if (dinfo)
827 fd[0] = dinfo->bdrv;
828
829 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
830 &fdc_tc);
831 }
832
833 if (drive_get_max_bus(IF_SCSI) > 0) {
834 fprintf(stderr, "qemu: too many SCSI bus\n");
835 exit(1);
836 }
837
838 esp_init(hwdef->esp_base, 2,
839 espdma_memory_read, espdma_memory_write,
840 espdma, espdma_irq, esp_reset);
841
842 if (hwdef->cs_base) {
843 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
844 slavio_irq[5]);
845 }
846
847 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
848 RAM_size);
849
850 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
851 boot_device, RAM_size, kernel_size, graphic_width,
852 graphic_height, graphic_depth, hwdef->nvram_machine_id,
853 "Sun4m");
854
855 if (hwdef->ecc_base)
856 ecc_init(hwdef->ecc_base, slavio_irq[28],
857 hwdef->ecc_version);
858
859 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
860 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
861 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
862 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
863 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
864 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
865 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
866 if (kernel_cmdline) {
867 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
868 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
869 } else {
870 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
871 }
872 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
873 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
874 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
875 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
876 }
877
878 enum {
879 ss2_id = 0,
880 ss5_id = 32,
881 vger_id,
882 lx_id,
883 ss4_id,
884 scls_id,
885 sbook_id,
886 ss10_id = 64,
887 ss20_id,
888 ss600mp_id,
889 ss1000_id = 96,
890 ss2000_id,
891 };
892
893 static const struct sun4m_hwdef sun4m_hwdefs[] = {
894 /* SS-5 */
895 {
896 .iommu_base = 0x10000000,
897 .tcx_base = 0x50000000,
898 .cs_base = 0x6c000000,
899 .slavio_base = 0x70000000,
900 .ms_kb_base = 0x71000000,
901 .serial_base = 0x71100000,
902 .nvram_base = 0x71200000,
903 .fd_base = 0x71400000,
904 .counter_base = 0x71d00000,
905 .intctl_base = 0x71e00000,
906 .idreg_base = 0x78000000,
907 .dma_base = 0x78400000,
908 .esp_base = 0x78800000,
909 .le_base = 0x78c00000,
910 .apc_base = 0x6a000000,
911 .aux1_base = 0x71900000,
912 .aux2_base = 0x71910000,
913 .vram_size = 0x00100000,
914 .nvram_size = 0x2000,
915 .nvram_machine_id = 0x80,
916 .machine_id = ss5_id,
917 .iommu_version = 0x05000000,
918 .max_mem = 0x10000000,
919 .default_cpu_model = "Fujitsu MB86904",
920 },
921 /* SS-10 */
922 {
923 .iommu_base = 0xfe0000000ULL,
924 .tcx_base = 0xe20000000ULL,
925 .slavio_base = 0xff0000000ULL,
926 .ms_kb_base = 0xff1000000ULL,
927 .serial_base = 0xff1100000ULL,
928 .nvram_base = 0xff1200000ULL,
929 .fd_base = 0xff1700000ULL,
930 .counter_base = 0xff1300000ULL,
931 .intctl_base = 0xff1400000ULL,
932 .idreg_base = 0xef0000000ULL,
933 .dma_base = 0xef0400000ULL,
934 .esp_base = 0xef0800000ULL,
935 .le_base = 0xef0c00000ULL,
936 .apc_base = 0xefa000000ULL, // XXX should not exist
937 .aux1_base = 0xff1800000ULL,
938 .aux2_base = 0xff1a01000ULL,
939 .ecc_base = 0xf00000000ULL,
940 .ecc_version = 0x10000000, // version 0, implementation 1
941 .vram_size = 0x00100000,
942 .nvram_size = 0x2000,
943 .nvram_machine_id = 0x72,
944 .machine_id = ss10_id,
945 .iommu_version = 0x03000000,
946 .max_mem = 0xf00000000ULL,
947 .default_cpu_model = "TI SuperSparc II",
948 },
949 /* SS-600MP */
950 {
951 .iommu_base = 0xfe0000000ULL,
952 .tcx_base = 0xe20000000ULL,
953 .slavio_base = 0xff0000000ULL,
954 .ms_kb_base = 0xff1000000ULL,
955 .serial_base = 0xff1100000ULL,
956 .nvram_base = 0xff1200000ULL,
957 .counter_base = 0xff1300000ULL,
958 .intctl_base = 0xff1400000ULL,
959 .dma_base = 0xef0081000ULL,
960 .esp_base = 0xef0080000ULL,
961 .le_base = 0xef0060000ULL,
962 .apc_base = 0xefa000000ULL, // XXX should not exist
963 .aux1_base = 0xff1800000ULL,
964 .aux2_base = 0xff1a01000ULL, // XXX should not exist
965 .ecc_base = 0xf00000000ULL,
966 .ecc_version = 0x00000000, // version 0, implementation 0
967 .vram_size = 0x00100000,
968 .nvram_size = 0x2000,
969 .nvram_machine_id = 0x71,
970 .machine_id = ss600mp_id,
971 .iommu_version = 0x01000000,
972 .max_mem = 0xf00000000ULL,
973 .default_cpu_model = "TI SuperSparc II",
974 },
975 /* SS-20 */
976 {
977 .iommu_base = 0xfe0000000ULL,
978 .tcx_base = 0xe20000000ULL,
979 .slavio_base = 0xff0000000ULL,
980 .ms_kb_base = 0xff1000000ULL,
981 .serial_base = 0xff1100000ULL,
982 .nvram_base = 0xff1200000ULL,
983 .fd_base = 0xff1700000ULL,
984 .counter_base = 0xff1300000ULL,
985 .intctl_base = 0xff1400000ULL,
986 .idreg_base = 0xef0000000ULL,
987 .dma_base = 0xef0400000ULL,
988 .esp_base = 0xef0800000ULL,
989 .le_base = 0xef0c00000ULL,
990 .apc_base = 0xefa000000ULL, // XXX should not exist
991 .aux1_base = 0xff1800000ULL,
992 .aux2_base = 0xff1a01000ULL,
993 .ecc_base = 0xf00000000ULL,
994 .ecc_version = 0x20000000, // version 0, implementation 2
995 .vram_size = 0x00100000,
996 .nvram_size = 0x2000,
997 .nvram_machine_id = 0x72,
998 .machine_id = ss20_id,
999 .iommu_version = 0x13000000,
1000 .max_mem = 0xf00000000ULL,
1001 .default_cpu_model = "TI SuperSparc II",
1002 },
1003 /* Voyager */
1004 {
1005 .iommu_base = 0x10000000,
1006 .tcx_base = 0x50000000,
1007 .slavio_base = 0x70000000,
1008 .ms_kb_base = 0x71000000,
1009 .serial_base = 0x71100000,
1010 .nvram_base = 0x71200000,
1011 .fd_base = 0x71400000,
1012 .counter_base = 0x71d00000,
1013 .intctl_base = 0x71e00000,
1014 .idreg_base = 0x78000000,
1015 .dma_base = 0x78400000,
1016 .esp_base = 0x78800000,
1017 .le_base = 0x78c00000,
1018 .apc_base = 0x71300000, // pmc
1019 .aux1_base = 0x71900000,
1020 .aux2_base = 0x71910000,
1021 .vram_size = 0x00100000,
1022 .nvram_size = 0x2000,
1023 .nvram_machine_id = 0x80,
1024 .machine_id = vger_id,
1025 .iommu_version = 0x05000000,
1026 .max_mem = 0x10000000,
1027 .default_cpu_model = "Fujitsu MB86904",
1028 },
1029 /* LX */
1030 {
1031 .iommu_base = 0x10000000,
1032 .tcx_base = 0x50000000,
1033 .slavio_base = 0x70000000,
1034 .ms_kb_base = 0x71000000,
1035 .serial_base = 0x71100000,
1036 .nvram_base = 0x71200000,
1037 .fd_base = 0x71400000,
1038 .counter_base = 0x71d00000,
1039 .intctl_base = 0x71e00000,
1040 .idreg_base = 0x78000000,
1041 .dma_base = 0x78400000,
1042 .esp_base = 0x78800000,
1043 .le_base = 0x78c00000,
1044 .aux1_base = 0x71900000,
1045 .aux2_base = 0x71910000,
1046 .vram_size = 0x00100000,
1047 .nvram_size = 0x2000,
1048 .nvram_machine_id = 0x80,
1049 .machine_id = lx_id,
1050 .iommu_version = 0x04000000,
1051 .max_mem = 0x10000000,
1052 .default_cpu_model = "TI MicroSparc I",
1053 },
1054 /* SS-4 */
1055 {
1056 .iommu_base = 0x10000000,
1057 .tcx_base = 0x50000000,
1058 .cs_base = 0x6c000000,
1059 .slavio_base = 0x70000000,
1060 .ms_kb_base = 0x71000000,
1061 .serial_base = 0x71100000,
1062 .nvram_base = 0x71200000,
1063 .fd_base = 0x71400000,
1064 .counter_base = 0x71d00000,
1065 .intctl_base = 0x71e00000,
1066 .idreg_base = 0x78000000,
1067 .dma_base = 0x78400000,
1068 .esp_base = 0x78800000,
1069 .le_base = 0x78c00000,
1070 .apc_base = 0x6a000000,
1071 .aux1_base = 0x71900000,
1072 .aux2_base = 0x71910000,
1073 .vram_size = 0x00100000,
1074 .nvram_size = 0x2000,
1075 .nvram_machine_id = 0x80,
1076 .machine_id = ss4_id,
1077 .iommu_version = 0x05000000,
1078 .max_mem = 0x10000000,
1079 .default_cpu_model = "Fujitsu MB86904",
1080 },
1081 /* SPARCClassic */
1082 {
1083 .iommu_base = 0x10000000,
1084 .tcx_base = 0x50000000,
1085 .slavio_base = 0x70000000,
1086 .ms_kb_base = 0x71000000,
1087 .serial_base = 0x71100000,
1088 .nvram_base = 0x71200000,
1089 .fd_base = 0x71400000,
1090 .counter_base = 0x71d00000,
1091 .intctl_base = 0x71e00000,
1092 .idreg_base = 0x78000000,
1093 .dma_base = 0x78400000,
1094 .esp_base = 0x78800000,
1095 .le_base = 0x78c00000,
1096 .apc_base = 0x6a000000,
1097 .aux1_base = 0x71900000,
1098 .aux2_base = 0x71910000,
1099 .vram_size = 0x00100000,
1100 .nvram_size = 0x2000,
1101 .nvram_machine_id = 0x80,
1102 .machine_id = scls_id,
1103 .iommu_version = 0x05000000,
1104 .max_mem = 0x10000000,
1105 .default_cpu_model = "TI MicroSparc I",
1106 },
1107 /* SPARCbook */
1108 {
1109 .iommu_base = 0x10000000,
1110 .tcx_base = 0x50000000, // XXX
1111 .slavio_base = 0x70000000,
1112 .ms_kb_base = 0x71000000,
1113 .serial_base = 0x71100000,
1114 .nvram_base = 0x71200000,
1115 .fd_base = 0x71400000,
1116 .counter_base = 0x71d00000,
1117 .intctl_base = 0x71e00000,
1118 .idreg_base = 0x78000000,
1119 .dma_base = 0x78400000,
1120 .esp_base = 0x78800000,
1121 .le_base = 0x78c00000,
1122 .apc_base = 0x6a000000,
1123 .aux1_base = 0x71900000,
1124 .aux2_base = 0x71910000,
1125 .vram_size = 0x00100000,
1126 .nvram_size = 0x2000,
1127 .nvram_machine_id = 0x80,
1128 .machine_id = sbook_id,
1129 .iommu_version = 0x05000000,
1130 .max_mem = 0x10000000,
1131 .default_cpu_model = "TI MicroSparc I",
1132 },
1133 };
1134
1135 /* SPARCstation 5 hardware initialisation */
1136 static void ss5_init(ram_addr_t RAM_size,
1137 const char *boot_device,
1138 const char *kernel_filename, const char *kernel_cmdline,
1139 const char *initrd_filename, const char *cpu_model)
1140 {
1141 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1142 kernel_cmdline, initrd_filename, cpu_model);
1143 }
1144
1145 /* SPARCstation 10 hardware initialisation */
1146 static void ss10_init(ram_addr_t RAM_size,
1147 const char *boot_device,
1148 const char *kernel_filename, const char *kernel_cmdline,
1149 const char *initrd_filename, const char *cpu_model)
1150 {
1151 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1152 kernel_cmdline, initrd_filename, cpu_model);
1153 }
1154
1155 /* SPARCserver 600MP hardware initialisation */
1156 static void ss600mp_init(ram_addr_t RAM_size,
1157 const char *boot_device,
1158 const char *kernel_filename,
1159 const char *kernel_cmdline,
1160 const char *initrd_filename, const char *cpu_model)
1161 {
1162 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1163 kernel_cmdline, initrd_filename, cpu_model);
1164 }
1165
1166 /* SPARCstation 20 hardware initialisation */
1167 static void ss20_init(ram_addr_t RAM_size,
1168 const char *boot_device,
1169 const char *kernel_filename, const char *kernel_cmdline,
1170 const char *initrd_filename, const char *cpu_model)
1171 {
1172 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1173 kernel_cmdline, initrd_filename, cpu_model);
1174 }
1175
1176 /* SPARCstation Voyager hardware initialisation */
1177 static void vger_init(ram_addr_t RAM_size,
1178 const char *boot_device,
1179 const char *kernel_filename, const char *kernel_cmdline,
1180 const char *initrd_filename, const char *cpu_model)
1181 {
1182 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1183 kernel_cmdline, initrd_filename, cpu_model);
1184 }
1185
1186 /* SPARCstation LX hardware initialisation */
1187 static void ss_lx_init(ram_addr_t RAM_size,
1188 const char *boot_device,
1189 const char *kernel_filename, const char *kernel_cmdline,
1190 const char *initrd_filename, const char *cpu_model)
1191 {
1192 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1193 kernel_cmdline, initrd_filename, cpu_model);
1194 }
1195
1196 /* SPARCstation 4 hardware initialisation */
1197 static void ss4_init(ram_addr_t RAM_size,
1198 const char *boot_device,
1199 const char *kernel_filename, const char *kernel_cmdline,
1200 const char *initrd_filename, const char *cpu_model)
1201 {
1202 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1203 kernel_cmdline, initrd_filename, cpu_model);
1204 }
1205
1206 /* SPARCClassic hardware initialisation */
1207 static void scls_init(ram_addr_t RAM_size,
1208 const char *boot_device,
1209 const char *kernel_filename, const char *kernel_cmdline,
1210 const char *initrd_filename, const char *cpu_model)
1211 {
1212 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1213 kernel_cmdline, initrd_filename, cpu_model);
1214 }
1215
1216 /* SPARCbook hardware initialisation */
1217 static void sbook_init(ram_addr_t RAM_size,
1218 const char *boot_device,
1219 const char *kernel_filename, const char *kernel_cmdline,
1220 const char *initrd_filename, const char *cpu_model)
1221 {
1222 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1223 kernel_cmdline, initrd_filename, cpu_model);
1224 }
1225
1226 static QEMUMachine ss5_machine = {
1227 .name = "SS-5",
1228 .desc = "Sun4m platform, SPARCstation 5",
1229 .init = ss5_init,
1230 .use_scsi = 1,
1231 .is_default = 1,
1232 };
1233
1234 static QEMUMachine ss10_machine = {
1235 .name = "SS-10",
1236 .desc = "Sun4m platform, SPARCstation 10",
1237 .init = ss10_init,
1238 .use_scsi = 1,
1239 .max_cpus = 4,
1240 };
1241
1242 static QEMUMachine ss600mp_machine = {
1243 .name = "SS-600MP",
1244 .desc = "Sun4m platform, SPARCserver 600MP",
1245 .init = ss600mp_init,
1246 .use_scsi = 1,
1247 .max_cpus = 4,
1248 };
1249
1250 static QEMUMachine ss20_machine = {
1251 .name = "SS-20",
1252 .desc = "Sun4m platform, SPARCstation 20",
1253 .init = ss20_init,
1254 .use_scsi = 1,
1255 .max_cpus = 4,
1256 };
1257
1258 static QEMUMachine voyager_machine = {
1259 .name = "Voyager",
1260 .desc = "Sun4m platform, SPARCstation Voyager",
1261 .init = vger_init,
1262 .use_scsi = 1,
1263 };
1264
1265 static QEMUMachine ss_lx_machine = {
1266 .name = "LX",
1267 .desc = "Sun4m platform, SPARCstation LX",
1268 .init = ss_lx_init,
1269 .use_scsi = 1,
1270 };
1271
1272 static QEMUMachine ss4_machine = {
1273 .name = "SS-4",
1274 .desc = "Sun4m platform, SPARCstation 4",
1275 .init = ss4_init,
1276 .use_scsi = 1,
1277 };
1278
1279 static QEMUMachine scls_machine = {
1280 .name = "SPARCClassic",
1281 .desc = "Sun4m platform, SPARCClassic",
1282 .init = scls_init,
1283 .use_scsi = 1,
1284 };
1285
1286 static QEMUMachine sbook_machine = {
1287 .name = "SPARCbook",
1288 .desc = "Sun4m platform, SPARCbook",
1289 .init = sbook_init,
1290 .use_scsi = 1,
1291 };
1292
1293 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1294 /* SS-1000 */
1295 {
1296 .iounit_bases = {
1297 0xfe0200000ULL,
1298 0xfe1200000ULL,
1299 0xfe2200000ULL,
1300 0xfe3200000ULL,
1301 -1,
1302 },
1303 .tcx_base = 0x820000000ULL,
1304 .slavio_base = 0xf00000000ULL,
1305 .ms_kb_base = 0xf00240000ULL,
1306 .serial_base = 0xf00200000ULL,
1307 .nvram_base = 0xf00280000ULL,
1308 .counter_base = 0xf00300000ULL,
1309 .espdma_base = 0x800081000ULL,
1310 .esp_base = 0x800080000ULL,
1311 .ledma_base = 0x800040000ULL,
1312 .le_base = 0x800060000ULL,
1313 .sbi_base = 0xf02800000ULL,
1314 .vram_size = 0x00100000,
1315 .nvram_size = 0x2000,
1316 .nvram_machine_id = 0x80,
1317 .machine_id = ss1000_id,
1318 .iounit_version = 0x03000000,
1319 .max_mem = 0xf00000000ULL,
1320 .default_cpu_model = "TI SuperSparc II",
1321 },
1322 /* SS-2000 */
1323 {
1324 .iounit_bases = {
1325 0xfe0200000ULL,
1326 0xfe1200000ULL,
1327 0xfe2200000ULL,
1328 0xfe3200000ULL,
1329 0xfe4200000ULL,
1330 },
1331 .tcx_base = 0x820000000ULL,
1332 .slavio_base = 0xf00000000ULL,
1333 .ms_kb_base = 0xf00240000ULL,
1334 .serial_base = 0xf00200000ULL,
1335 .nvram_base = 0xf00280000ULL,
1336 .counter_base = 0xf00300000ULL,
1337 .espdma_base = 0x800081000ULL,
1338 .esp_base = 0x800080000ULL,
1339 .ledma_base = 0x800040000ULL,
1340 .le_base = 0x800060000ULL,
1341 .sbi_base = 0xf02800000ULL,
1342 .vram_size = 0x00100000,
1343 .nvram_size = 0x2000,
1344 .nvram_machine_id = 0x80,
1345 .machine_id = ss2000_id,
1346 .iounit_version = 0x03000000,
1347 .max_mem = 0xf00000000ULL,
1348 .default_cpu_model = "TI SuperSparc II",
1349 },
1350 };
1351
1352 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1353 {
1354 DeviceState *dev;
1355 SysBusDevice *s;
1356 unsigned int i;
1357
1358 dev = qdev_create(NULL, "sbi");
1359 qdev_init(dev);
1360
1361 s = sysbus_from_qdev(dev);
1362
1363 for (i = 0; i < MAX_CPUS; i++) {
1364 sysbus_connect_irq(s, i, *parent_irq[i]);
1365 }
1366
1367 sysbus_mmio_map(s, 0, addr);
1368
1369 return dev;
1370 }
1371
1372 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1373 const char *boot_device,
1374 const char *kernel_filename,
1375 const char *kernel_cmdline,
1376 const char *initrd_filename, const char *cpu_model)
1377 {
1378 CPUState *envs[MAX_CPUS];
1379 unsigned int i;
1380 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1381 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1382 espdma_irq, ledma_irq;
1383 qemu_irq *esp_reset, *le_reset;
1384 unsigned long kernel_size;
1385 void *fw_cfg;
1386 DeviceState *dev;
1387
1388 /* init CPUs */
1389 if (!cpu_model)
1390 cpu_model = hwdef->default_cpu_model;
1391
1392 for(i = 0; i < smp_cpus; i++) {
1393 envs[i] = cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1394 }
1395
1396 for (i = smp_cpus; i < MAX_CPUS; i++)
1397 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1398
1399 /* set up devices */
1400 ram_init(0, RAM_size, hwdef->max_mem);
1401
1402 prom_init(hwdef->slavio_base, bios_name);
1403
1404 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1405
1406 for (i = 0; i < 32; i++) {
1407 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1408 }
1409 for (i = 0; i < MAX_CPUS; i++) {
1410 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1411 }
1412
1413 for (i = 0; i < MAX_IOUNITS; i++)
1414 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1415 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1416 hwdef->iounit_version,
1417 sbi_irq[0]);
1418
1419 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1420 iounits[0], &espdma_irq, &esp_reset);
1421
1422 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1423 iounits[0], &ledma_irq, &le_reset);
1424
1425 if (graphic_depth != 8 && graphic_depth != 24) {
1426 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1427 exit (1);
1428 }
1429 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1430 graphic_depth);
1431
1432 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1433
1434 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1435 hwdef->nvram_size, 8);
1436
1437 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1438
1439 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1440 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1441 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1442 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1443 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1444 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1445
1446 if (drive_get_max_bus(IF_SCSI) > 0) {
1447 fprintf(stderr, "qemu: too many SCSI bus\n");
1448 exit(1);
1449 }
1450
1451 esp_init(hwdef->esp_base, 2,
1452 espdma_memory_read, espdma_memory_write,
1453 espdma, espdma_irq, esp_reset);
1454
1455 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1456 RAM_size);
1457
1458 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1459 boot_device, RAM_size, kernel_size, graphic_width,
1460 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1461 "Sun4d");
1462
1463 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1464 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1465 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1466 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1467 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1468 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1469 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1470 if (kernel_cmdline) {
1471 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1472 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1473 } else {
1474 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1475 }
1476 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1477 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1478 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1479 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1480 }
1481
1482 /* SPARCserver 1000 hardware initialisation */
1483 static void ss1000_init(ram_addr_t RAM_size,
1484 const char *boot_device,
1485 const char *kernel_filename, const char *kernel_cmdline,
1486 const char *initrd_filename, const char *cpu_model)
1487 {
1488 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1489 kernel_cmdline, initrd_filename, cpu_model);
1490 }
1491
1492 /* SPARCcenter 2000 hardware initialisation */
1493 static void ss2000_init(ram_addr_t RAM_size,
1494 const char *boot_device,
1495 const char *kernel_filename, const char *kernel_cmdline,
1496 const char *initrd_filename, const char *cpu_model)
1497 {
1498 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1499 kernel_cmdline, initrd_filename, cpu_model);
1500 }
1501
1502 static QEMUMachine ss1000_machine = {
1503 .name = "SS-1000",
1504 .desc = "Sun4d platform, SPARCserver 1000",
1505 .init = ss1000_init,
1506 .use_scsi = 1,
1507 .max_cpus = 8,
1508 };
1509
1510 static QEMUMachine ss2000_machine = {
1511 .name = "SS-2000",
1512 .desc = "Sun4d platform, SPARCcenter 2000",
1513 .init = ss2000_init,
1514 .use_scsi = 1,
1515 .max_cpus = 20,
1516 };
1517
1518 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1519 /* SS-2 */
1520 {
1521 .iommu_base = 0xf8000000,
1522 .tcx_base = 0xfe000000,
1523 .slavio_base = 0xf6000000,
1524 .intctl_base = 0xf5000000,
1525 .counter_base = 0xf3000000,
1526 .ms_kb_base = 0xf0000000,
1527 .serial_base = 0xf1000000,
1528 .nvram_base = 0xf2000000,
1529 .fd_base = 0xf7200000,
1530 .dma_base = 0xf8400000,
1531 .esp_base = 0xf8800000,
1532 .le_base = 0xf8c00000,
1533 .aux1_base = 0xf7400003,
1534 .vram_size = 0x00100000,
1535 .nvram_size = 0x800,
1536 .nvram_machine_id = 0x55,
1537 .machine_id = ss2_id,
1538 .max_mem = 0x10000000,
1539 .default_cpu_model = "Cypress CY7C601",
1540 },
1541 };
1542
1543 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1544 qemu_irq *parent_irq)
1545 {
1546 DeviceState *dev;
1547 SysBusDevice *s;
1548 unsigned int i;
1549
1550 dev = qdev_create(NULL, "sun4c_intctl");
1551 qdev_init(dev);
1552
1553 s = sysbus_from_qdev(dev);
1554
1555 for (i = 0; i < MAX_PILS; i++) {
1556 sysbus_connect_irq(s, i, parent_irq[i]);
1557 }
1558 sysbus_mmio_map(s, 0, addr);
1559
1560 return dev;
1561 }
1562
1563 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1564 const char *boot_device,
1565 const char *kernel_filename,
1566 const char *kernel_cmdline,
1567 const char *initrd_filename, const char *cpu_model)
1568 {
1569 CPUState *env;
1570 void *iommu, *espdma, *ledma, *nvram;
1571 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1572 qemu_irq *esp_reset, *le_reset;
1573 qemu_irq fdc_tc;
1574 unsigned long kernel_size;
1575 BlockDriverState *fd[MAX_FD];
1576 void *fw_cfg;
1577 DeviceState *dev;
1578 unsigned int i;
1579 DriveInfo *dinfo;
1580
1581 /* init CPU */
1582 if (!cpu_model)
1583 cpu_model = hwdef->default_cpu_model;
1584
1585 env = cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1586
1587 /* set up devices */
1588 ram_init(0, RAM_size, hwdef->max_mem);
1589
1590 prom_init(hwdef->slavio_base, bios_name);
1591
1592 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1593
1594 for (i = 0; i < 8; i++) {
1595 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1596 }
1597
1598 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1599 slavio_irq[1]);
1600
1601 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1602 iommu, &espdma_irq, &esp_reset);
1603
1604 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1605 slavio_irq[3], iommu, &ledma_irq,
1606 &le_reset);
1607
1608 if (graphic_depth != 8 && graphic_depth != 24) {
1609 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1610 exit (1);
1611 }
1612 tcx_init(hwdef->tcx_base, hwdef->vram_size, graphic_width, graphic_height,
1613 graphic_depth);
1614
1615 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq, le_reset);
1616
1617 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
1618 hwdef->nvram_size, 2);
1619
1620 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1621 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1622 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1623 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1624 escc_init(hwdef->serial_base, slavio_irq[1],
1625 slavio_irq[1], serial_hds[0], serial_hds[1],
1626 ESCC_CLOCK, 1);
1627
1628 slavio_misc = slavio_misc_init(0, hwdef->aux1_base, 0,
1629 slavio_irq[1], fdc_tc);
1630
1631 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1632 /* there is zero or one floppy drive */
1633 memset(fd, 0, sizeof(fd));
1634 dinfo = drive_get(IF_FLOPPY, 0, 0);
1635 if (dinfo)
1636 fd[0] = dinfo->bdrv;
1637
1638 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1639 &fdc_tc);
1640 }
1641
1642 if (drive_get_max_bus(IF_SCSI) > 0) {
1643 fprintf(stderr, "qemu: too many SCSI bus\n");
1644 exit(1);
1645 }
1646
1647 esp_init(hwdef->esp_base, 2,
1648 espdma_memory_read, espdma_memory_write,
1649 espdma, espdma_irq, esp_reset);
1650
1651 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1652 RAM_size);
1653
1654 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1655 boot_device, RAM_size, kernel_size, graphic_width,
1656 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1657 "Sun4c");
1658
1659 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1660 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1661 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1662 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1663 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1664 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1665 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1666 if (kernel_cmdline) {
1667 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1668 pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1669 } else {
1670 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1671 }
1672 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1673 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1674 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1675 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1676 }
1677
1678 /* SPARCstation 2 hardware initialisation */
1679 static void ss2_init(ram_addr_t RAM_size,
1680 const char *boot_device,
1681 const char *kernel_filename, const char *kernel_cmdline,
1682 const char *initrd_filename, const char *cpu_model)
1683 {
1684 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1685 kernel_cmdline, initrd_filename, cpu_model);
1686 }
1687
1688 static QEMUMachine ss2_machine = {
1689 .name = "SS-2",
1690 .desc = "Sun4c platform, SPARCstation 2",
1691 .init = ss2_init,
1692 .use_scsi = 1,
1693 };
1694
1695 static void ss2_machine_init(void)
1696 {
1697 qemu_register_machine(&ss5_machine);
1698 qemu_register_machine(&ss10_machine);
1699 qemu_register_machine(&ss600mp_machine);
1700 qemu_register_machine(&ss20_machine);
1701 qemu_register_machine(&voyager_machine);
1702 qemu_register_machine(&ss_lx_machine);
1703 qemu_register_machine(&ss4_machine);
1704 qemu_register_machine(&scls_machine);
1705 qemu_register_machine(&sbook_machine);
1706 qemu_register_machine(&ss1000_machine);
1707 qemu_register_machine(&ss2000_machine);
1708 qemu_register_machine(&ss2_machine);
1709 }
1710
1711 machine_init(ss2_machine_init);
Qemu copy for testing