hw/sun4m.h

   1 #ifndef SUN4M_H
   2 #define SUN4M_H
   3
   4 /* Devices used by sparc32 system.  */
   5
   6 /* iommu.c */
   7 void *iommu_init(target_phys_addr_t addr, uint32_t version);
   8 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
   9                                  uint8_t *buf, int len, int is_write);
  10 static inline void sparc_iommu_memory_read(void *opaque,
  11                                            target_phys_addr_t addr,
  12                                            uint8_t *buf, int len)
  13 {
  14     sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
  15 }
  16
  17 static inline void sparc_iommu_memory_write(void *opaque,
  18                                             target_phys_addr_t addr,
  19                                             uint8_t *buf, int len)
  20 {
  21     sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
  22 }
  23
  24 /* tcx.c */
  25 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
  26               unsigned long vram_offset, int vram_size, int width, int height,
  27               int depth);
  28
  29 /* slavio_intctl.c */
  30 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
  31                          const uint32_t *intbit_to_level,
  32                          qemu_irq **irq, qemu_irq **cpu_irq,
  33                          qemu_irq **parent_irq, unsigned int cputimer);
  34 void slavio_pic_info(void *opaque);
  35 void slavio_irq_info(void *opaque);
  36
  37 /* slavio_timer.c */
  38 void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
  39                            qemu_irq *cpu_irqs);
  40
  41 /* slavio_serial.c */
  42 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
  43                                 CharDriverState *chr1, CharDriverState *chr2);
  44 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
  45
  46 /* slavio_misc.c */
  47 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
  48                        qemu_irq irq);
  49 void slavio_set_power_fail(void *opaque, int power_failing);
  50
  51 /* esp.c */
  52 #define ESP_MAX_DEVS 7
  53 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
  54 void *esp_init(target_phys_addr_t espaddr,
  55                void *dma_opaque, qemu_irq irq, qemu_irq *reset);
  56
  57 /* cs4231.c */
  58 void cs_init(target_phys_addr_t base, int irq, void *intctl);
  59
  60 /* sparc32_dma.c */
  61 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
  62                        void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
  63 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
  64                        uint8_t *buf, int len, int do_bswap);
  65 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
  66                         uint8_t *buf, int len, int do_bswap);
  67 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
  68 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
  69
  70 /* pcnet.c */
  71 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
  72                 qemu_irq irq, qemu_irq *reset);
  73
  74 #endif