hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35 #include "sysbus.h"
  36 #include "ide.h"
  37 #include "loader.h"
  38 #include "elf.h"
  39
  40 //#define DEBUG_IRQ
  41
  42 #ifdef DEBUG_IRQ
  43 #define DPRINTF(fmt, ...)                                       \
  44     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  45 #else
  46 #define DPRINTF(fmt, ...)
  47 #endif
  48
  49 #define KERNEL_LOAD_ADDR     0x00404000
  50 #define CMDLINE_ADDR         0x003ff000
  51 #define INITRD_LOAD_ADDR     0x00300000
  52 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  53 #define PROM_VADDR           0x000ffd00000ULL
  54 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  55 #define APB_MEM_BASE         0x1ff00000000ULL
  56 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  57 #define PROM_FILENAME        "openbios-sparc64"
  58 #define NVRAM_SIZE           0x2000
  59 #define MAX_IDE_BUS          2
  60 #define BIOS_CFG_IOPORT      0x510
  61 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  62 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  63 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  64
  65 #define MAX_PILS 16
  66
  67 #define TICK_INT_DIS         0x8000000000000000ULL
  68 #define TICK_MAX             0x7fffffffffffffffULL
  69
  70 struct hwdef {
  71     const char * const default_cpu_model;
  72     uint16_t machine_id;
  73     uint64_t prom_addr;
  74     uint64_t console_serial_base;
  75 };
  76
  77 int DMA_get_channel_mode (int nchan)
  78 {
  79     return 0;
  80 }
  81 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  82 {
  83     return 0;
  84 }
  85 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  86 {
  87     return 0;
  88 }
  89 void DMA_hold_DREQ (int nchan) {}
  90 void DMA_release_DREQ (int nchan) {}
  91 void DMA_schedule(int nchan) {}
  92 void DMA_init (int high_page_enable) {}
  93 void DMA_register_channel (int nchan,
  94                            DMA_transfer_handler transfer_handler,
  95                            void *opaque)
  96 {
  97 }
  98
  99 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 100 {
 101     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 102     return 0;
 103 }
 104
 105 static int sun4u_NVRAM_set_params (a_m48t59 *nvram, uint16_t NVRAM_size,
 106                                    const char *arch,
 107                                    a_ram_addr RAM_size,
 108                                    const char *boot_devices,
 109                                    uint32_t kernel_image, uint32_t kernel_size,
 110                                    const char *cmdline,
 111                                    uint32_t initrd_image, uint32_t initrd_size,
 112                                    uint32_t NVRAM_image,
 113                                    int width, int height, int depth,
 114                                    const uint8_t *macaddr)
 115 {
 116     unsigned int i;
 117     uint32_t start, end;
 118     uint8_t image[0x1ff0];
 119     struct OpenBIOS_nvpart_v1 *part_header;
 120
 121     memset(image, '\0', sizeof(image));
 122
 123     start = 0;
 124
 125     // OpenBIOS nvram variables
 126     // Variable partition
 127     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 128     part_header->signature = OPENBIOS_PART_SYSTEM;
 129     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 130
 131     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 132     for (i = 0; i < nb_prom_envs; i++)
 133         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 134
 135     // End marker
 136     image[end++] = '\0';
 137
 138     end = start + ((end - start + 15) & ~15);
 139     OpenBIOS_finish_partition(part_header, end - start);
 140
 141     // free partition
 142     start = end;
 143     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 144     part_header->signature = OPENBIOS_PART_FREE;
 145     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 146
 147     end = 0x1fd0;
 148     OpenBIOS_finish_partition(part_header, end - start);
 149
 150     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 151
 152     for (i = 0; i < sizeof(image); i++)
 153         m48t59_write(nvram, i, image[i]);
 154
 155     return 0;
 156 }
 157 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 158                                        const char *initrd_filename,
 159                                        a_ram_addr RAM_size, long *initrd_size)
 160 {
 161     int linux_boot;
 162     unsigned int i;
 163     long kernel_size;
 164
 165     linux_boot = (kernel_filename != NULL);
 166
 167     kernel_size = 0;
 168     if (linux_boot) {
 169         int bswap_needed;
 170
 171 #ifdef BSWAP_NEEDED
 172         bswap_needed = 1;
 173 #else
 174         bswap_needed = 0;
 175 #endif
 176         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
 177                                1, ELF_MACHINE, 0);
 178         if (kernel_size < 0)
 179             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 180                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 181                                     TARGET_PAGE_SIZE);
 182         if (kernel_size < 0)
 183             kernel_size = load_image_targphys(kernel_filename,
 184                                               KERNEL_LOAD_ADDR,
 185                                               RAM_size - KERNEL_LOAD_ADDR);
 186         if (kernel_size < 0) {
 187             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 188                     kernel_filename);
 189             exit(1);
 190         }
 191
 192         /* load initrd */
 193         *initrd_size = 0;
 194         if (initrd_filename) {
 195             *initrd_size = load_image_targphys(initrd_filename,
 196                                                INITRD_LOAD_ADDR,
 197                                                RAM_size - INITRD_LOAD_ADDR);
 198             if (*initrd_size < 0) {
 199                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 200                         initrd_filename);
 201                 exit(1);
 202             }
 203         }
 204         if (*initrd_size > 0) {
 205             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 206                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 207                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 208                     stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
 209                     break;
 210                 }
 211             }
 212         }
 213     }
 214     return kernel_size;
 215 }
 216
 217 void pic_info(Monitor *mon)
 218 {
 219 }
 220
 221 void irq_info(Monitor *mon)
 222 {
 223 }
 224
 225 void cpu_check_irqs(CPUState *env)
 226 {
 227     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 228         ((env->softint & SOFTINT_TIMER) << 14);
 229
 230     if (pil && (env->interrupt_index == 0 ||
 231                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 232         unsigned int i;
 233
 234         for (i = 15; i > 0; i--) {
 235             if (pil & (1 << i)) {
 236                 int old_interrupt = env->interrupt_index;
 237
 238                 env->interrupt_index = TT_EXTINT | i;
 239                 if (old_interrupt != env->interrupt_index) {
 240                     DPRINTF("Set CPU IRQ %d\n", i);
 241                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 242                 }
 243                 break;
 244             }
 245         }
 246     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 247         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 248         env->interrupt_index = 0;
 249         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 250     }
 251 }
 252
 253 static void cpu_set_irq(void *opaque, int irq, int level)
 254 {
 255     CPUState *env = opaque;
 256
 257     if (level) {
 258         DPRINTF("Raise CPU IRQ %d\n", irq);
 259         env->halted = 0;
 260         env->pil_in |= 1 << irq;
 261         cpu_check_irqs(env);
 262     } else {
 263         DPRINTF("Lower CPU IRQ %d\n", irq);
 264         env->pil_in &= ~(1 << irq);
 265         cpu_check_irqs(env);
 266     }
 267 }
 268
 269 typedef struct ResetData {
 270     CPUState *env;
 271     uint64_t reset_addr;
 272 } ResetData;
 273
 274 static void main_cpu_reset(void *opaque)
 275 {
 276     ResetData *s = (ResetData *)opaque;
 277     CPUState *env = s->env;
 278
 279     cpu_reset(env);
 280     env->tick_cmpr = TICK_INT_DIS | 0;
 281     ptimer_set_limit(env->tick, TICK_MAX, 1);
 282     ptimer_run(env->tick, 1);
 283     env->stick_cmpr = TICK_INT_DIS | 0;
 284     ptimer_set_limit(env->stick, TICK_MAX, 1);
 285     ptimer_run(env->stick, 1);
 286     env->hstick_cmpr = TICK_INT_DIS | 0;
 287     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 288     ptimer_run(env->hstick, 1);
 289     env->gregs[1] = 0; // Memory start
 290     env->gregs[2] = ram_size; // Memory size
 291     env->gregs[3] = 0; // Machine description XXX
 292     env->pc = s->reset_addr;
 293     env->npc = env->pc + 4;
 294 }
 295
 296 static void tick_irq(void *opaque)
 297 {
 298     CPUState *env = opaque;
 299
 300     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 301         env->softint |= SOFTINT_TIMER;
 302         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 303     }
 304 }
 305
 306 static void stick_irq(void *opaque)
 307 {
 308     CPUState *env = opaque;
 309
 310     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 311         env->softint |= SOFTINT_STIMER;
 312         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 313     }
 314 }
 315
 316 static void hstick_irq(void *opaque)
 317 {
 318     CPUState *env = opaque;
 319
 320     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 321         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 322     }
 323 }
 324
 325 void cpu_tick_set_count(void *opaque, uint64_t count)
 326 {
 327     ptimer_set_count(opaque, -count);
 328 }
 329
 330 uint64_t cpu_tick_get_count(void *opaque)
 331 {
 332     return -ptimer_get_count(opaque);
 333 }
 334
 335 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 336 {
 337     ptimer_set_limit(opaque, -limit, 0);
 338 }
 339
 340 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 341 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 342
 343 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 344 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 345
 346 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 347                               uint32_t addr, uint32_t size, int type)
 348 {
 349     DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
 350     switch (region_num) {
 351     case 0:
 352         isa_mmio_init(addr, 0x1000000);
 353         break;
 354     case 1:
 355         isa_mmio_init(addr, 0x800000);
 356         break;
 357     }
 358 }
 359
 360 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 361 {
 362 }
 363
 364 /* EBUS (Eight bit bus) bridge */
 365 static void
 366 pci_ebus_init(PCIBus *bus, int devfn)
 367 {
 368     qemu_irq *isa_irq;
 369
 370     pci_create_simple(bus, devfn, "ebus");
 371     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 372     isa_bus_irqs(isa_irq);
 373 }
 374
 375 static int
 376 pci_ebus_init1(PCIDevice *s)
 377 {
 378     isa_bus_new(&s->qdev);
 379
 380     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 381     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 382     s->config[0x04] = 0x06; // command = bus master, pci mem
 383     s->config[0x05] = 0x00;
 384     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 385     s->config[0x07] = 0x03; // status = medium devsel
 386     s->config[0x08] = 0x01; // revision
 387     s->config[0x09] = 0x00; // programming i/f
 388     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 389     s->config[0x0D] = 0x0a; // latency_timer
 390     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 391
 392     pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
 393                            ebus_mmio_mapfunc);
 394     pci_register_bar(s, 1, 0x800000,  PCI_ADDRESS_SPACE_MEM,
 395                            ebus_mmio_mapfunc);
 396     return 0;
 397 }
 398
 399 static PCIDeviceInfo ebus_info = {
 400     .qdev.name = "ebus",
 401     .qdev.size = sizeof(PCIDevice),
 402     .init = pci_ebus_init1,
 403 };
 404
 405 static void pci_ebus_register(void)
 406 {
 407     pci_qdev_register(&ebus_info);
 408 }
 409
 410 device_init(pci_ebus_register);
 411
 412 /* Boot PROM (OpenBIOS) */
 413 static void prom_init(a_target_phys_addr addr, const char *bios_name)
 414 {
 415     DeviceState *dev;
 416     SysBusDevice *s;
 417     char *filename;
 418     int ret;
 419
 420     dev = qdev_create(NULL, "openprom");
 421     qdev_init(dev);
 422     s = sysbus_from_qdev(dev);
 423
 424     sysbus_mmio_map(s, 0, addr);
 425
 426     /* load boot prom */
 427     if (bios_name == NULL) {
 428         bios_name = PROM_FILENAME;
 429     }
 430     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 431     if (filename) {
 432         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
 433                        1, ELF_MACHINE, 0);
 434         if (ret < 0 || ret > PROM_SIZE_MAX) {
 435             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 436         }
 437         qemu_free(filename);
 438     } else {
 439         ret = -1;
 440     }
 441     if (ret < 0 || ret > PROM_SIZE_MAX) {
 442         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 443         exit(1);
 444     }
 445 }
 446
 447 static int prom_init1(SysBusDevice *dev)
 448 {
 449     a_ram_addr prom_offset;
 450
 451     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 452     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 453     return 0;
 454 }
 455
 456 static SysBusDeviceInfo prom_info = {
 457     .init = prom_init1,
 458     .qdev.name  = "openprom",
 459     .qdev.size  = sizeof(SysBusDevice),
 460     .qdev.props = (Property[]) {
 461         {/* end of property list */}
 462     }
 463 };
 464
 465 static void prom_register_devices(void)
 466 {
 467     sysbus_register_withprop(&prom_info);
 468 }
 469
 470 device_init(prom_register_devices);
 471
 472
 473 typedef struct RamDevice
 474 {
 475     SysBusDevice busdev;
 476     uint64_t size;
 477 } RamDevice;
 478
 479 /* System RAM */
 480 static int ram_init1(SysBusDevice *dev)
 481 {
 482     a_ram_addr RAM_size, ram_offset;
 483     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 484
 485     RAM_size = d->size;
 486
 487     ram_offset = qemu_ram_alloc(RAM_size);
 488     sysbus_init_mmio(dev, RAM_size, ram_offset);
 489     return 0;
 490 }
 491
 492 static void ram_init(a_target_phys_addr addr, a_ram_addr RAM_size)
 493 {
 494     DeviceState *dev;
 495     SysBusDevice *s;
 496     RamDevice *d;
 497
 498     /* allocate RAM */
 499     dev = qdev_create(NULL, "memory");
 500     s = sysbus_from_qdev(dev);
 501
 502     d = FROM_SYSBUS(RamDevice, s);
 503     d->size = RAM_size;
 504     qdev_init(dev);
 505
 506     sysbus_mmio_map(s, 0, addr);
 507 }
 508
 509 static SysBusDeviceInfo ram_info = {
 510     .init = ram_init1,
 511     .qdev.name  = "memory",
 512     .qdev.size  = sizeof(RamDevice),
 513     .qdev.props = (Property[]) {
 514         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 515         DEFINE_PROP_END_OF_LIST(),
 516     }
 517 };
 518
 519 static void ram_register_devices(void)
 520 {
 521     sysbus_register_withprop(&ram_info);
 522 }
 523
 524 device_init(ram_register_devices);
 525
 526 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 527 {
 528     CPUState *env;
 529     QEMUBH *bh;
 530     ResetData *reset_info;
 531
 532     if (!cpu_model)
 533         cpu_model = hwdef->default_cpu_model;
 534     env = cpu_init(cpu_model);
 535     if (!env) {
 536         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 537         exit(1);
 538     }
 539     bh = qemu_bh_new(tick_irq, env);
 540     env->tick = ptimer_init(bh);
 541     ptimer_set_period(env->tick, 1ULL);
 542
 543     bh = qemu_bh_new(stick_irq, env);
 544     env->stick = ptimer_init(bh);
 545     ptimer_set_period(env->stick, 1ULL);
 546
 547     bh = qemu_bh_new(hstick_irq, env);
 548     env->hstick = ptimer_init(bh);
 549     ptimer_set_period(env->hstick, 1ULL);
 550
 551     reset_info = qemu_mallocz(sizeof(ResetData));
 552     reset_info->env = env;
 553     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 554     qemu_register_reset(main_cpu_reset, reset_info);
 555     main_cpu_reset(reset_info);
 556     // Override warm reset address with cold start address
 557     env->pc = hwdef->prom_addr + 0x20ULL;
 558     env->npc = env->pc + 4;
 559
 560     return env;
 561 }
 562
 563 static void sun4uv_init(a_ram_addr RAM_size,
 564                         const char *boot_devices,
 565                         const char *kernel_filename, const char *kernel_cmdline,
 566                         const char *initrd_filename, const char *cpu_model,
 567                         const struct hwdef *hwdef)
 568 {
 569     CPUState *env;
 570     a_m48t59 *nvram;
 571     unsigned int i;
 572     long initrd_size, kernel_size;
 573     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 574     qemu_irq *irq;
 575     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 576     BlockDriverState *fd[MAX_FD];
 577     void *fw_cfg;
 578     DriveInfo *dinfo;
 579
 580     /* init CPUs */
 581     env = cpu_devinit(cpu_model, hwdef);
 582
 583     /* set up devices */
 584     ram_init(0, RAM_size);
 585
 586     prom_init(hwdef->prom_addr, bios_name);
 587
 588
 589     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 590     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 591                            &pci_bus3);
 592     isa_mem_base = VGA_BASE;
 593     pci_vga_init(pci_bus, 0, 0);
 594
 595     // XXX Should be pci_bus3
 596     pci_ebus_init(pci_bus, -1);
 597
 598     i = 0;
 599     if (hwdef->console_serial_base) {
 600         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 601                        serial_hds[i], 1);
 602         i++;
 603     }
 604     for(; i < MAX_SERIAL_PORTS; i++) {
 605         if (serial_hds[i]) {
 606             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 607                         serial_hds[i]);
 608         }
 609     }
 610
 611     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 612         if (parallel_hds[i]) {
 613             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 614                           parallel_hds[i]);
 615         }
 616     }
 617
 618     for(i = 0; i < nb_nics; i++)
 619         pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 620
 621     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 622         fprintf(stderr, "qemu: too many IDE bus\n");
 623         exit(1);
 624     }
 625     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 626         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 627                           i % MAX_IDE_DEVS);
 628     }
 629
 630     pci_cmd646_ide_init(pci_bus, hd, 1);
 631
 632     isa_create_simple("i8042");
 633     for(i = 0; i < MAX_FD; i++) {
 634         dinfo = drive_get(IF_FLOPPY, 0, i);
 635         fd[i] = dinfo ? dinfo->bdrv : NULL;
 636     }
 637     fdctrl_init_isa(fd);
 638     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 639
 640     initrd_size = 0;
 641     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 642                                     ram_size, &initrd_size);
 643
 644     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 645                            KERNEL_LOAD_ADDR, kernel_size,
 646                            kernel_cmdline,
 647                            INITRD_LOAD_ADDR, initrd_size,
 648                            /* XXX: need an option to load a NVRAM image */
 649                            0,
 650                            graphic_width, graphic_height, graphic_depth,
 651                            (uint8_t *)&nd_table[0].macaddr);
 652
 653     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 654     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 655     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 656     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 657     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 658     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 659     if (kernel_cmdline) {
 660         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 661         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 662     } else {
 663         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 664     }
 665     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 666     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 667     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 668
 669     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 670     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 671     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 672
 673     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 674 }
 675
 676 enum {
 677     sun4u_id = 0,
 678     sun4v_id = 64,
 679     niagara_id,
 680 };
 681
 682 static const struct hwdef hwdefs[] = {
 683     /* Sun4u generic PC-like machine */
 684     {
 685         .default_cpu_model = "TI UltraSparc II",
 686         .machine_id = sun4u_id,
 687         .prom_addr = 0x1fff0000000ULL,
 688         .console_serial_base = 0,
 689     },
 690     /* Sun4v generic PC-like machine */
 691     {
 692         .default_cpu_model = "Sun UltraSparc T1",
 693         .machine_id = sun4v_id,
 694         .prom_addr = 0x1fff0000000ULL,
 695         .console_serial_base = 0,
 696     },
 697     /* Sun4v generic Niagara machine */
 698     {
 699         .default_cpu_model = "Sun UltraSparc T1",
 700         .machine_id = niagara_id,
 701         .prom_addr = 0xfff0000000ULL,
 702         .console_serial_base = 0xfff0c2c000ULL,
 703     },
 704 };
 705
 706 /* Sun4u hardware initialisation */
 707 static void sun4u_init(a_ram_addr RAM_size,
 708                        const char *boot_devices,
 709                        const char *kernel_filename, const char *kernel_cmdline,
 710                        const char *initrd_filename, const char *cpu_model)
 711 {
 712     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 713                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 714 }
 715
 716 /* Sun4v hardware initialisation */
 717 static void sun4v_init(a_ram_addr RAM_size,
 718                        const char *boot_devices,
 719                        const char *kernel_filename, const char *kernel_cmdline,
 720                        const char *initrd_filename, const char *cpu_model)
 721 {
 722     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 723                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 724 }
 725
 726 /* Niagara hardware initialisation */
 727 static void niagara_init(a_ram_addr RAM_size,
 728                          const char *boot_devices,
 729                          const char *kernel_filename, const char *kernel_cmdline,
 730                          const char *initrd_filename, const char *cpu_model)
 731 {
 732     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 733                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 734 }
 735
 736 static QEMUMachine sun4u_machine = {
 737     .name = "sun4u",
 738     .desc = "Sun4u platform",
 739     .init = sun4u_init,
 740     .max_cpus = 1, // XXX for now
 741     .is_default = 1,
 742 };
 743
 744 static QEMUMachine sun4v_machine = {
 745     .name = "sun4v",
 746     .desc = "Sun4v platform",
 747     .init = sun4v_init,
 748     .max_cpus = 1, // XXX for now
 749 };
 750
 751 static QEMUMachine niagara_machine = {
 752     .name = "Niagara",
 753     .desc = "Sun4v platform, Niagara",
 754     .init = niagara_init,
 755     .max_cpus = 1, // XXX for now
 756 };
 757
 758 static void sun4u_machine_init(void)
 759 {
 760     qemu_register_machine(&sun4u_machine);
 761     qemu_register_machine(&sun4v_machine);
 762     qemu_register_machine(&niagara_machine);
 763 }
 764
 765 machine_init(sun4u_machine_init);