hw/tcx.c

   1 /*
   2  * QEMU TCX Frame buffer
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "console.h"
  26 #include "pixel_ops.h"
  27 #include "sysbus.h"
  28 #include "qdev-addr.h"
  29
  30 #define MAXX 1024
  31 #define MAXY 768
  32 #define TCX_DAC_NREGS 16
  33 #define TCX_THC_NREGS_8  0x081c
  34 #define TCX_THC_NREGS_24 0x1000
  35 #define TCX_TEC_NREGS    0x1000
  36
  37 typedef struct TCXState {
  38     SysBusDevice busdev;
  39     target_phys_addr_t addr;
  40     DisplayState *ds;
  41     uint8_t *vram;
  42     uint32_t *vram24, *cplane;
  43     MemoryRegion vram_mem;
  44     MemoryRegion vram_8bit;
  45     MemoryRegion vram_24bit;
  46     MemoryRegion vram_cplane;
  47     MemoryRegion dac;
  48     MemoryRegion tec;
  49     MemoryRegion thc24;
  50     MemoryRegion thc8;
  51     ram_addr_t vram24_offset, cplane_offset;
  52     uint32_t vram_size;
  53     uint32_t palette[256];
  54     uint8_t r[256], g[256], b[256];
  55     uint16_t width, height, depth;
  56     uint8_t dac_index, dac_state;
  57 } TCXState;
  58
  59 static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
  60                             Error **errp);
  61 static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
  62                             Error **errp);
  63
  64 static void tcx_set_dirty(TCXState *s)
  65 {
  66     memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
  67 }
  68
  69 static void tcx24_set_dirty(TCXState *s)
  70 {
  71     memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
  72     memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
  73 }
  74
  75 static void update_palette_entries(TCXState *s, int start, int end)
  76 {
  77     int i;
  78     for(i = start; i < end; i++) {
  79         switch(ds_get_bits_per_pixel(s->ds)) {
  80         default:
  81         case 8:
  82             s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
  83             break;
  84         case 15:
  85             s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
  86             break;
  87         case 16:
  88             s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
  89             break;
  90         case 32:
  91             if (is_surface_bgr(s->ds->surface))
  92                 s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
  93             else
  94                 s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
  95             break;
  96         }
  97     }
  98     if (s->depth == 24) {
  99         tcx24_set_dirty(s);
 100     } else {
 101         tcx_set_dirty(s);
 102     }
 103 }
 104
 105 static void tcx_draw_line32(TCXState *s1, uint8_t *d,
 106                             const uint8_t *s, int width)
 107 {
 108     int x;
 109     uint8_t val;
 110     uint32_t *p = (uint32_t *)d;
 111
 112     for(x = 0; x < width; x++) {
 113         val = *s++;
 114         *p++ = s1->palette[val];
 115     }
 116 }
 117
 118 static void tcx_draw_line16(TCXState *s1, uint8_t *d,
 119                             const uint8_t *s, int width)
 120 {
 121     int x;
 122     uint8_t val;
 123     uint16_t *p = (uint16_t *)d;
 124
 125     for(x = 0; x < width; x++) {
 126         val = *s++;
 127         *p++ = s1->palette[val];
 128     }
 129 }
 130
 131 static void tcx_draw_line8(TCXState *s1, uint8_t *d,
 132                            const uint8_t *s, int width)
 133 {
 134     int x;
 135     uint8_t val;
 136
 137     for(x = 0; x < width; x++) {
 138         val = *s++;
 139         *d++ = s1->palette[val];
 140     }
 141 }
 142
 143 /*
 144   XXX Could be much more optimal:
 145   * detect if line/page/whole screen is in 24 bit mode
 146   * if destination is also BGR, use memcpy
 147   */
 148 static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
 149                                      const uint8_t *s, int width,
 150                                      const uint32_t *cplane,
 151                                      const uint32_t *s24)
 152 {
 153     int x, bgr, r, g, b;
 154     uint8_t val, *p8;
 155     uint32_t *p = (uint32_t *)d;
 156     uint32_t dval;
 157
 158     bgr = is_surface_bgr(s1->ds->surface);
 159     for(x = 0; x < width; x++, s++, s24++) {
 160         if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
 161             // 24-bit direct, BGR order
 162             p8 = (uint8_t *)s24;
 163             p8++;
 164             b = *p8++;
 165             g = *p8++;
 166             r = *p8;
 167             if (bgr)
 168                 dval = rgb_to_pixel32bgr(r, g, b);
 169             else
 170                 dval = rgb_to_pixel32(r, g, b);
 171         } else {
 172             val = *s;
 173             dval = s1->palette[val];
 174         }
 175         *p++ = dval;
 176     }
 177 }
 178
 179 static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
 180                               ram_addr_t cpage)
 181 {
 182     int ret;
 183
 184     ret = memory_region_get_dirty(&s->vram_mem, page, TARGET_PAGE_SIZE,
 185                                   DIRTY_MEMORY_VGA);
 186     ret |= memory_region_get_dirty(&s->vram_mem, page24, TARGET_PAGE_SIZE * 4,
 187                                    DIRTY_MEMORY_VGA);
 188     ret |= memory_region_get_dirty(&s->vram_mem, cpage, TARGET_PAGE_SIZE * 4,
 189                                    DIRTY_MEMORY_VGA);
 190     return ret;
 191 }
 192
 193 static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
 194                                ram_addr_t page_max, ram_addr_t page24,
 195                               ram_addr_t cpage)
 196 {
 197     memory_region_reset_dirty(&ts->vram_mem,
 198                               page_min, page_max + TARGET_PAGE_SIZE,
 199                               DIRTY_MEMORY_VGA);
 200     memory_region_reset_dirty(&ts->vram_mem,
 201                               page24 + page_min * 4,
 202                               page24 + page_max * 4 + TARGET_PAGE_SIZE,
 203                               DIRTY_MEMORY_VGA);
 204     memory_region_reset_dirty(&ts->vram_mem,
 205                               cpage + page_min * 4,
 206                               cpage + page_max * 4 + TARGET_PAGE_SIZE,
 207                               DIRTY_MEMORY_VGA);
 208 }
 209
 210 /* Fixed line length 1024 allows us to do nice tricks not possible on
 211    VGA... */
 212 static void tcx_update_display(void *opaque)
 213 {
 214     TCXState *ts = opaque;
 215     ram_addr_t page, page_min, page_max;
 216     int y, y_start, dd, ds;
 217     uint8_t *d, *s;
 218     void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);
 219
 220     if (ds_get_bits_per_pixel(ts->ds) == 0)
 221         return;
 222     page = 0;
 223     y_start = -1;
 224     page_min = -1;
 225     page_max = 0;
 226     d = ds_get_data(ts->ds);
 227     s = ts->vram;
 228     dd = ds_get_linesize(ts->ds);
 229     ds = 1024;
 230
 231     switch (ds_get_bits_per_pixel(ts->ds)) {
 232     case 32:
 233         f = tcx_draw_line32;
 234         break;
 235     case 15:
 236     case 16:
 237         f = tcx_draw_line16;
 238         break;
 239     default:
 240     case 8:
 241         f = tcx_draw_line8;
 242         break;
 243     case 0:
 244         return;
 245     }
 246
 247     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
 248         if (memory_region_get_dirty(&ts->vram_mem, page, TARGET_PAGE_SIZE,
 249                                     DIRTY_MEMORY_VGA)) {
 250             if (y_start < 0)
 251                 y_start = y;
 252             if (page < page_min)
 253                 page_min = page;
 254             if (page > page_max)
 255                 page_max = page;
 256             f(ts, d, s, ts->width);
 257             d += dd;
 258             s += ds;
 259             f(ts, d, s, ts->width);
 260             d += dd;
 261             s += ds;
 262             f(ts, d, s, ts->width);
 263             d += dd;
 264             s += ds;
 265             f(ts, d, s, ts->width);
 266             d += dd;
 267             s += ds;
 268         } else {
 269             if (y_start >= 0) {
 270                 /* flush to display */
 271                 dpy_update(ts->ds, 0, y_start,
 272                            ts->width, y - y_start);
 273                 y_start = -1;
 274             }
 275             d += dd * 4;
 276             s += ds * 4;
 277         }
 278     }
 279     if (y_start >= 0) {
 280         /* flush to display */
 281         dpy_update(ts->ds, 0, y_start,
 282                    ts->width, y - y_start);
 283     }
 284     /* reset modified pages */
 285     if (page_max >= page_min) {
 286         memory_region_reset_dirty(&ts->vram_mem,
 287                                   page_min, page_max + TARGET_PAGE_SIZE,
 288                                   DIRTY_MEMORY_VGA);
 289     }
 290 }
 291
 292 static void tcx24_update_display(void *opaque)
 293 {
 294     TCXState *ts = opaque;
 295     ram_addr_t page, page_min, page_max, cpage, page24;
 296     int y, y_start, dd, ds;
 297     uint8_t *d, *s;
 298     uint32_t *cptr, *s24;
 299
 300     if (ds_get_bits_per_pixel(ts->ds) != 32)
 301             return;
 302     page = 0;
 303     page24 = ts->vram24_offset;
 304     cpage = ts->cplane_offset;
 305     y_start = -1;
 306     page_min = -1;
 307     page_max = 0;
 308     d = ds_get_data(ts->ds);
 309     s = ts->vram;
 310     s24 = ts->vram24;
 311     cptr = ts->cplane;
 312     dd = ds_get_linesize(ts->ds);
 313     ds = 1024;
 314
 315     for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
 316             page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
 317         if (check_dirty(ts, page, page24, cpage)) {
 318             if (y_start < 0)
 319                 y_start = y;
 320             if (page < page_min)
 321                 page_min = page;
 322             if (page > page_max)
 323                 page_max = page;
 324             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 325             d += dd;
 326             s += ds;
 327             cptr += ds;
 328             s24 += ds;
 329             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 330             d += dd;
 331             s += ds;
 332             cptr += ds;
 333             s24 += ds;
 334             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 335             d += dd;
 336             s += ds;
 337             cptr += ds;
 338             s24 += ds;
 339             tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
 340             d += dd;
 341             s += ds;
 342             cptr += ds;
 343             s24 += ds;
 344         } else {
 345             if (y_start >= 0) {
 346                 /* flush to display */
 347                 dpy_update(ts->ds, 0, y_start,
 348                            ts->width, y - y_start);
 349                 y_start = -1;
 350             }
 351             d += dd * 4;
 352             s += ds * 4;
 353             cptr += ds * 4;
 354             s24 += ds * 4;
 355         }
 356     }
 357     if (y_start >= 0) {
 358         /* flush to display */
 359         dpy_update(ts->ds, 0, y_start,
 360                    ts->width, y - y_start);
 361     }
 362     /* reset modified pages */
 363     if (page_max >= page_min) {
 364         reset_dirty(ts, page_min, page_max, page24, cpage);
 365     }
 366 }
 367
 368 static void tcx_invalidate_display(void *opaque)
 369 {
 370     TCXState *s = opaque;
 371
 372     tcx_set_dirty(s);
 373     qemu_console_resize(s->ds, s->width, s->height);
 374 }
 375
 376 static void tcx24_invalidate_display(void *opaque)
 377 {
 378     TCXState *s = opaque;
 379
 380     tcx_set_dirty(s);
 381     tcx24_set_dirty(s);
 382     qemu_console_resize(s->ds, s->width, s->height);
 383 }
 384
 385 static int vmstate_tcx_post_load(void *opaque, int version_id)
 386 {
 387     TCXState *s = opaque;
 388
 389     update_palette_entries(s, 0, 256);
 390     if (s->depth == 24) {
 391         tcx24_set_dirty(s);
 392     } else {
 393         tcx_set_dirty(s);
 394     }
 395
 396     return 0;
 397 }
 398
 399 static const VMStateDescription vmstate_tcx = {
 400     .name ="tcx",
 401     .version_id = 4,
 402     .minimum_version_id = 4,
 403     .minimum_version_id_old = 4,
 404     .post_load = vmstate_tcx_post_load,
 405     .fields      = (VMStateField []) {
 406         VMSTATE_UINT16(height, TCXState),
 407         VMSTATE_UINT16(width, TCXState),
 408         VMSTATE_UINT16(depth, TCXState),
 409         VMSTATE_BUFFER(r, TCXState),
 410         VMSTATE_BUFFER(g, TCXState),
 411         VMSTATE_BUFFER(b, TCXState),
 412         VMSTATE_UINT8(dac_index, TCXState),
 413         VMSTATE_UINT8(dac_state, TCXState),
 414         VMSTATE_END_OF_LIST()
 415     }
 416 };
 417
 418 static void tcx_reset(DeviceState *d)
 419 {
 420     TCXState *s = container_of(d, TCXState, busdev.qdev);
 421
 422     /* Initialize palette */
 423     memset(s->r, 0, 256);
 424     memset(s->g, 0, 256);
 425     memset(s->b, 0, 256);
 426     s->r[255] = s->g[255] = s->b[255] = 255;
 427     update_palette_entries(s, 0, 256);
 428     memset(s->vram, 0, MAXX*MAXY);
 429     memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
 430                               DIRTY_MEMORY_VGA);
 431     s->dac_index = 0;
 432     s->dac_state = 0;
 433 }
 434
 435 static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
 436                               unsigned size)
 437 {
 438     return 0;
 439 }
 440
 441 static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
 442                            unsigned size)
 443 {
 444     TCXState *s = opaque;
 445
 446     switch (addr) {
 447     case 0:
 448         s->dac_index = val >> 24;
 449         s->dac_state = 0;
 450         break;
 451     case 4:
 452         switch (s->dac_state) {
 453         case 0:
 454             s->r[s->dac_index] = val >> 24;
 455             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 456             s->dac_state++;
 457             break;
 458         case 1:
 459             s->g[s->dac_index] = val >> 24;
 460             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 461             s->dac_state++;
 462             break;
 463         case 2:
 464             s->b[s->dac_index] = val >> 24;
 465             update_palette_entries(s, s->dac_index, s->dac_index + 1);
 466             s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
 467         default:
 468             s->dac_state = 0;
 469             break;
 470         }
 471         break;
 472     default:
 473         break;
 474     }
 475     return;
 476 }
 477
 478 static const MemoryRegionOps tcx_dac_ops = {
 479     .read = tcx_dac_readl,
 480     .write = tcx_dac_writel,
 481     .endianness = DEVICE_NATIVE_ENDIAN,
 482     .valid = {
 483         .min_access_size = 4,
 484         .max_access_size = 4,
 485     },
 486 };
 487
 488 static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
 489                             unsigned size)
 490 {
 491     return 0;
 492 }
 493
 494 static void dummy_writel(void *opaque, target_phys_addr_t addr,
 495                          uint64_t val, unsigned size)
 496 {
 497 }
 498
 499 static const MemoryRegionOps dummy_ops = {
 500     .read = dummy_readl,
 501     .write = dummy_writel,
 502     .endianness = DEVICE_NATIVE_ENDIAN,
 503     .valid = {
 504         .min_access_size = 4,
 505         .max_access_size = 4,
 506     },
 507 };
 508
 509 static int tcx_init1(SysBusDevice *dev)
 510 {
 511     TCXState *s = FROM_SYSBUS(TCXState, dev);
 512     ram_addr_t vram_offset = 0;
 513     int size;
 514     uint8_t *vram_base;
 515
 516     memory_region_init_ram(&s->vram_mem, "tcx.vram",
 517                            s->vram_size * (1 + 4 + 4));
 518     vmstate_register_ram_global(&s->vram_mem);
 519     vram_base = memory_region_get_ram_ptr(&s->vram_mem);
 520
 521     /* 8-bit plane */
 522     s->vram = vram_base;
 523     size = s->vram_size;
 524     memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
 525                              &s->vram_mem, vram_offset, size);
 526     sysbus_init_mmio(dev, &s->vram_8bit);
 527     vram_offset += size;
 528     vram_base += size;
 529
 530     /* DAC */
 531     memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
 532     sysbus_init_mmio(dev, &s->dac);
 533
 534     /* TEC (dummy) */
 535     memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
 536     sysbus_init_mmio(dev, &s->tec);
 537     /* THC: NetBSD writes here even with 8-bit display: dummy */
 538     memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
 539                           TCX_THC_NREGS_24);
 540     sysbus_init_mmio(dev, &s->thc24);
 541
 542     if (s->depth == 24) {
 543         /* 24-bit plane */
 544         size = s->vram_size * 4;
 545         s->vram24 = (uint32_t *)vram_base;
 546         s->vram24_offset = vram_offset;
 547         memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
 548                                  &s->vram_mem, vram_offset, size);
 549         sysbus_init_mmio(dev, &s->vram_24bit);
 550         vram_offset += size;
 551         vram_base += size;
 552
 553         /* Control plane */
 554         size = s->vram_size * 4;
 555         s->cplane = (uint32_t *)vram_base;
 556         s->cplane_offset = vram_offset;
 557         memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
 558                                  &s->vram_mem, vram_offset, size);
 559         sysbus_init_mmio(dev, &s->vram_cplane);
 560
 561         s->ds = graphic_console_init(tcx24_update_display,
 562                                      tcx24_invalidate_display,
 563                                      tcx24_screen_dump, NULL, s);
 564     } else {
 565         /* THC 8 bit (dummy) */
 566         memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
 567                               TCX_THC_NREGS_8);
 568         sysbus_init_mmio(dev, &s->thc8);
 569
 570         s->ds = graphic_console_init(tcx_update_display,
 571                                      tcx_invalidate_display,
 572                                      tcx_screen_dump, NULL, s);
 573     }
 574
 575     qemu_console_resize(s->ds, s->width, s->height);
 576     return 0;
 577 }
 578
 579 static void tcx_screen_dump(void *opaque, const char *filename, bool cswitch,
 580                             Error **errp)
 581 {
 582     TCXState *s = opaque;
 583     FILE *f;
 584     uint8_t *d, *d1, v;
 585     int y, x;
 586
 587     f = fopen(filename, "wb");
 588     if (!f)
 589         return;
 590     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 591     d1 = s->vram;
 592     for(y = 0; y < s->height; y++) {
 593         d = d1;
 594         for(x = 0; x < s->width; x++) {
 595             v = *d;
 596             fputc(s->r[v], f);
 597             fputc(s->g[v], f);
 598             fputc(s->b[v], f);
 599             d++;
 600         }
 601         d1 += MAXX;
 602     }
 603     fclose(f);
 604     return;
 605 }
 606
 607 static void tcx24_screen_dump(void *opaque, const char *filename, bool cswitch,
 608                               Error **errp)
 609 {
 610     TCXState *s = opaque;
 611     FILE *f;
 612     uint8_t *d, *d1, v;
 613     uint32_t *s24, *cptr, dval;
 614     int y, x;
 615
 616     f = fopen(filename, "wb");
 617     if (!f)
 618         return;
 619     fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
 620     d1 = s->vram;
 621     s24 = s->vram24;
 622     cptr = s->cplane;
 623     for(y = 0; y < s->height; y++) {
 624         d = d1;
 625         for(x = 0; x < s->width; x++, d++, s24++) {
 626             if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
 627                 dval = *s24 & 0x00ffffff;
 628                 fputc((dval >> 16) & 0xff, f);
 629                 fputc((dval >> 8) & 0xff, f);
 630                 fputc(dval & 0xff, f);
 631             } else {
 632                 v = *d;
 633                 fputc(s->r[v], f);
 634                 fputc(s->g[v], f);
 635                 fputc(s->b[v], f);
 636             }
 637         }
 638         d1 += MAXX;
 639     }
 640     fclose(f);
 641     return;
 642 }
 643
 644 static Property tcx_properties[] = {
 645     DEFINE_PROP_TADDR("addr",      TCXState, addr,      -1),
 646     DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
 647     DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
 648     DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
 649     DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
 650     DEFINE_PROP_END_OF_LIST(),
 651 };
 652
 653 static void tcx_class_init(ObjectClass *klass, void *data)
 654 {
 655     DeviceClass *dc = DEVICE_CLASS(klass);
 656     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 657
 658     k->init = tcx_init1;
 659     dc->reset = tcx_reset;
 660     dc->vmsd = &vmstate_tcx;
 661     dc->props = tcx_properties;
 662 }
 663
 664 static TypeInfo tcx_info = {
 665     .name          = "SUNW,tcx",
 666     .parent        = TYPE_SYS_BUS_DEVICE,
 667     .instance_size = sizeof(TCXState),
 668     .class_init    = tcx_class_init,
 669 };
 670
 671 static void tcx_register_types(void)
 672 {
 673     type_register_static(&tcx_info);
 674 }
 675
 676 type_init(tcx_register_types)