hw/timer/i8254.c

   1 /*
   2  * QEMU 8253/8254 interval timer emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/i386/pc.h"
  26 #include "hw/isa/isa.h"
  27 #include "qemu/timer.h"
  28 #include "hw/timer/i8254.h"
  29 #include "hw/timer/i8254_internal.h"
  30
  31 //#define DEBUG_PIT
  32
  33 #define RW_STATE_LSB 1
  34 #define RW_STATE_MSB 2
  35 #define RW_STATE_WORD0 3
  36 #define RW_STATE_WORD1 4
  37
  38 #define PIT_CLASS(class) OBJECT_CLASS_CHECK(PITClass, (class), TYPE_I8254)
  39 #define PIT_GET_CLASS(obj) OBJECT_GET_CLASS(PITClass, (obj), TYPE_I8254)
  40
  41 typedef struct PITClass {
  42     PITCommonClass parent_class;
  43
  44     DeviceRealize parent_realize;
  45 } PITClass;
  46
  47 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
  48
  49 static int pit_get_count(PITChannelState *s)
  50 {
  51     uint64_t d;
  52     int counter;
  53
  54     d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
  55                  get_ticks_per_sec());
  56     switch(s->mode) {
  57     case 0:
  58     case 1:
  59     case 4:
  60     case 5:
  61         counter = (s->count - d) & 0xffff;
  62         break;
  63     case 3:
  64         /* XXX: may be incorrect for odd counts */
  65         counter = s->count - ((2 * d) % s->count);
  66         break;
  67     default:
  68         counter = s->count - (d % s->count);
  69         break;
  70     }
  71     return counter;
  72 }
  73
  74 /* val must be 0 or 1 */
  75 static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
  76                                  int val)
  77 {
  78     switch (sc->mode) {
  79     default:
  80     case 0:
  81     case 4:
  82         /* XXX: just disable/enable counting */
  83         break;
  84     case 1:
  85     case 5:
  86         if (sc->gate < val) {
  87             /* restart counting on rising edge */
  88             sc->count_load_time = qemu_get_clock_ns(vm_clock);
  89             pit_irq_timer_update(sc, sc->count_load_time);
  90         }
  91         break;
  92     case 2:
  93     case 3:
  94         if (sc->gate < val) {
  95             /* restart counting on rising edge */
  96             sc->count_load_time = qemu_get_clock_ns(vm_clock);
  97             pit_irq_timer_update(sc, sc->count_load_time);
  98         }
  99         /* XXX: disable/enable counting */
 100         break;
 101     }
 102     sc->gate = val;
 103 }
 104
 105 static inline void pit_load_count(PITChannelState *s, int val)
 106 {
 107     if (val == 0)
 108         val = 0x10000;
 109     s->count_load_time = qemu_get_clock_ns(vm_clock);
 110     s->count = val;
 111     pit_irq_timer_update(s, s->count_load_time);
 112 }
 113
 114 /* if already latched, do not latch again */
 115 static void pit_latch_count(PITChannelState *s)
 116 {
 117     if (!s->count_latched) {
 118         s->latched_count = pit_get_count(s);
 119         s->count_latched = s->rw_mode;
 120     }
 121 }
 122
 123 static void pit_ioport_write(void *opaque, hwaddr addr,
 124                              uint64_t val, unsigned size)
 125 {
 126     PITCommonState *pit = opaque;
 127     int channel, access;
 128     PITChannelState *s;
 129
 130     addr &= 3;
 131     if (addr == 3) {
 132         channel = val >> 6;
 133         if (channel == 3) {
 134             /* read back command */
 135             for(channel = 0; channel < 3; channel++) {
 136                 s = &pit->channels[channel];
 137                 if (val & (2 << channel)) {
 138                     if (!(val & 0x20)) {
 139                         pit_latch_count(s);
 140                     }
 141                     if (!(val & 0x10) && !s->status_latched) {
 142                         /* status latch */
 143                         /* XXX: add BCD and null count */
 144                         s->status =
 145                             (pit_get_out(s,
 146                                          qemu_get_clock_ns(vm_clock)) << 7) |
 147                             (s->rw_mode << 4) |
 148                             (s->mode << 1) |
 149                             s->bcd;
 150                         s->status_latched = 1;
 151                     }
 152                 }
 153             }
 154         } else {
 155             s = &pit->channels[channel];
 156             access = (val >> 4) & 3;
 157             if (access == 0) {
 158                 pit_latch_count(s);
 159             } else {
 160                 s->rw_mode = access;
 161                 s->read_state = access;
 162                 s->write_state = access;
 163
 164                 s->mode = (val >> 1) & 7;
 165                 s->bcd = val & 1;
 166                 /* XXX: update irq timer ? */
 167             }
 168         }
 169     } else {
 170         s = &pit->channels[addr];
 171         switch(s->write_state) {
 172         default:
 173         case RW_STATE_LSB:
 174             pit_load_count(s, val);
 175             break;
 176         case RW_STATE_MSB:
 177             pit_load_count(s, val << 8);
 178             break;
 179         case RW_STATE_WORD0:
 180             s->write_latch = val;
 181             s->write_state = RW_STATE_WORD1;
 182             break;
 183         case RW_STATE_WORD1:
 184             pit_load_count(s, s->write_latch | (val << 8));
 185             s->write_state = RW_STATE_WORD0;
 186             break;
 187         }
 188     }
 189 }
 190
 191 static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
 192                                 unsigned size)
 193 {
 194     PITCommonState *pit = opaque;
 195     int ret, count;
 196     PITChannelState *s;
 197
 198     addr &= 3;
 199     s = &pit->channels[addr];
 200     if (s->status_latched) {
 201         s->status_latched = 0;
 202         ret = s->status;
 203     } else if (s->count_latched) {
 204         switch(s->count_latched) {
 205         default:
 206         case RW_STATE_LSB:
 207             ret = s->latched_count & 0xff;
 208             s->count_latched = 0;
 209             break;
 210         case RW_STATE_MSB:
 211             ret = s->latched_count >> 8;
 212             s->count_latched = 0;
 213             break;
 214         case RW_STATE_WORD0:
 215             ret = s->latched_count & 0xff;
 216             s->count_latched = RW_STATE_MSB;
 217             break;
 218         }
 219     } else {
 220         switch(s->read_state) {
 221         default:
 222         case RW_STATE_LSB:
 223             count = pit_get_count(s);
 224             ret = count & 0xff;
 225             break;
 226         case RW_STATE_MSB:
 227             count = pit_get_count(s);
 228             ret = (count >> 8) & 0xff;
 229             break;
 230         case RW_STATE_WORD0:
 231             count = pit_get_count(s);
 232             ret = count & 0xff;
 233             s->read_state = RW_STATE_WORD1;
 234             break;
 235         case RW_STATE_WORD1:
 236             count = pit_get_count(s);
 237             ret = (count >> 8) & 0xff;
 238             s->read_state = RW_STATE_WORD0;
 239             break;
 240         }
 241     }
 242     return ret;
 243 }
 244
 245 static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
 246 {
 247     int64_t expire_time;
 248     int irq_level;
 249
 250     if (!s->irq_timer || s->irq_disabled) {
 251         return;
 252     }
 253     expire_time = pit_get_next_transition_time(s, current_time);
 254     irq_level = pit_get_out(s, current_time);
 255     qemu_set_irq(s->irq, irq_level);
 256 #ifdef DEBUG_PIT
 257     printf("irq_level=%d next_delay=%f\n",
 258            irq_level,
 259            (double)(expire_time - current_time) / get_ticks_per_sec());
 260 #endif
 261     s->next_transition_time = expire_time;
 262     if (expire_time != -1)
 263         qemu_mod_timer(s->irq_timer, expire_time);
 264     else
 265         qemu_del_timer(s->irq_timer);
 266 }
 267
 268 static void pit_irq_timer(void *opaque)
 269 {
 270     PITChannelState *s = opaque;
 271
 272     pit_irq_timer_update(s, s->next_transition_time);
 273 }
 274
 275 static void pit_reset(DeviceState *dev)
 276 {
 277     PITCommonState *pit = PIT_COMMON(dev);
 278     PITChannelState *s;
 279
 280     pit_reset_common(pit);
 281
 282     s = &pit->channels[0];
 283     if (!s->irq_disabled) {
 284         qemu_mod_timer(s->irq_timer, s->next_transition_time);
 285     }
 286 }
 287
 288 /* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
 289  * reenable it when legacy mode is left again. */
 290 static void pit_irq_control(void *opaque, int n, int enable)
 291 {
 292     PITCommonState *pit = opaque;
 293     PITChannelState *s = &pit->channels[0];
 294
 295     if (enable) {
 296         s->irq_disabled = 0;
 297         pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
 298     } else {
 299         s->irq_disabled = 1;
 300         qemu_del_timer(s->irq_timer);
 301     }
 302 }
 303
 304 static const MemoryRegionOps pit_ioport_ops = {
 305     .read = pit_ioport_read,
 306     .write = pit_ioport_write,
 307     .impl = {
 308         .min_access_size = 1,
 309         .max_access_size = 1,
 310     },
 311     .endianness = DEVICE_LITTLE_ENDIAN,
 312 };
 313
 314 static void pit_post_load(PITCommonState *s)
 315 {
 316     PITChannelState *sc = &s->channels[0];
 317
 318     if (sc->next_transition_time != -1) {
 319         qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
 320     } else {
 321         qemu_del_timer(sc->irq_timer);
 322     }
 323 }
 324
 325 static void pit_realizefn(DeviceState *dev, Error **err)
 326 {
 327     PITCommonState *pit = PIT_COMMON(dev);
 328     PITClass *pc = PIT_GET_CLASS(dev);
 329     PITChannelState *s;
 330
 331     s = &pit->channels[0];
 332     /* the timer 0 is connected to an IRQ */
 333     s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
 334     qdev_init_gpio_out(dev, &s->irq, 1);
 335
 336     memory_region_init_io(&pit->ioports, NULL, &pit_ioport_ops, pit, "pit", 4);
 337
 338     qdev_init_gpio_in(dev, pit_irq_control, 1);
 339
 340     pc->parent_realize(dev, err);
 341 }
 342
 343 static Property pit_properties[] = {
 344     DEFINE_PROP_HEX32("iobase", PITCommonState, iobase,  -1),
 345     DEFINE_PROP_END_OF_LIST(),
 346 };
 347
 348 static void pit_class_initfn(ObjectClass *klass, void *data)
 349 {
 350     PITClass *pc = PIT_CLASS(klass);
 351     PITCommonClass *k = PIT_COMMON_CLASS(klass);
 352     DeviceClass *dc = DEVICE_CLASS(klass);
 353
 354     pc->parent_realize = dc->realize;
 355     dc->realize = pit_realizefn;
 356     k->set_channel_gate = pit_set_channel_gate;
 357     k->get_channel_info = pit_get_channel_info_common;
 358     k->post_load = pit_post_load;
 359     dc->reset = pit_reset;
 360     dc->props = pit_properties;
 361 }
 362
 363 static const TypeInfo pit_info = {
 364     .name          = TYPE_I8254,
 365     .parent        = TYPE_PIT_COMMON,
 366     .instance_size = sizeof(PITCommonState),
 367     .class_init    = pit_class_initfn,
 368     .class_size    = sizeof(PITClass),
 369 };
 370
 371 static void pit_register_types(void)
 372 {
 373     type_register_static(&pit_info);
 374 }
 375
 376 type_init(pit_register_types)