hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw/hw.h"
  25 #include "hw/timer/m48t59.h"
  26 #include "qemu/timer.h"
  27 #include "sysemu/sysemu.h"
  28 #include "hw/sysbus.h"
  29 #include "hw/isa/isa.h"
  30 #include "exec/address-spaces.h"
  31
  32 //#define DEBUG_NVRAM
  33
  34 #if defined(DEBUG_NVRAM)
  35 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  36 #else
  37 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  38 #endif
  39
  40 /*
  41  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  42  * alarm and a watchdog timer and related control registers. In the
  43  * PPC platform there is also a nvram lock function.
  44  */
  45
  46 /*
  47  * Chipset docs:
  48  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  49  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  50  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  51  */
  52
  53 struct M48t59State {
  54     /* Hardware parameters */
  55     qemu_irq IRQ;
  56     MemoryRegion iomem;
  57     uint32_t io_base;
  58     uint32_t size;
  59     /* RTC management */
  60     time_t   time_offset;
  61     time_t   stop_time;
  62     /* Alarm & watchdog */
  63     struct tm alarm;
  64     struct QEMUTimer *alrm_timer;
  65     struct QEMUTimer *wd_timer;
  66     /* NVRAM storage */
  67     uint8_t *buffer;
  68     /* Model parameters */
  69     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  70     /* NVRAM storage */
  71     uint16_t addr;
  72     uint8_t  lock;
  73 };
  74
  75 #define TYPE_ISA_M48T59 "m48t59_isa"
  76 #define ISA_M48T59(obj) \
  77     OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59)
  78
  79 typedef struct M48t59ISAState {
  80     ISADevice parent_obj;
  81
  82     M48t59State state;
  83     MemoryRegion io;
  84 } M48t59ISAState;
  85
  86 typedef struct M48t59SysBusState {
  87     SysBusDevice busdev;
  88     M48t59State state;
  89     MemoryRegion io;
  90 } M48t59SysBusState;
  91
  92 /* Fake timer functions */
  93
  94 /* Alarm management */
  95 static void alarm_cb (void *opaque)
  96 {
  97     struct tm tm;
  98     uint64_t next_time;
  99     M48t59State *NVRAM = opaque;
 100
 101     qemu_set_irq(NVRAM->IRQ, 1);
 102     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
 103         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 104         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 105         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 106         /* Repeat once a month */
 107         qemu_get_timedate(&tm, NVRAM->time_offset);
 108         tm.tm_mon++;
 109         if (tm.tm_mon == 13) {
 110             tm.tm_mon = 1;
 111             tm.tm_year++;
 112         }
 113         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 114     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 115                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 116                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 117                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 118         /* Repeat once a day */
 119         next_time = 24 * 60 * 60;
 120     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 121                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 122                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 123                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 124         /* Repeat once an hour */
 125         next_time = 60 * 60;
 126     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 127                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 128                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 129                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 130         /* Repeat once a minute */
 131         next_time = 60;
 132     } else {
 133         /* Repeat once a second */
 134         next_time = 1;
 135     }
 136     qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(rtc_clock) +
 137                     next_time * 1000);
 138     qemu_set_irq(NVRAM->IRQ, 0);
 139 }
 140
 141 static void set_alarm(M48t59State *NVRAM)
 142 {
 143     int diff;
 144     if (NVRAM->alrm_timer != NULL) {
 145         qemu_del_timer(NVRAM->alrm_timer);
 146         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 147         if (diff > 0)
 148             qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
 149     }
 150 }
 151
 152 /* RTC management helpers */
 153 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 154 {
 155     qemu_get_timedate(tm, NVRAM->time_offset);
 156 }
 157
 158 static void set_time(M48t59State *NVRAM, struct tm *tm)
 159 {
 160     NVRAM->time_offset = qemu_timedate_diff(tm);
 161     set_alarm(NVRAM);
 162 }
 163
 164 /* Watchdog management */
 165 static void watchdog_cb (void *opaque)
 166 {
 167     M48t59State *NVRAM = opaque;
 168
 169     NVRAM->buffer[0x1FF0] |= 0x80;
 170     if (NVRAM->buffer[0x1FF7] & 0x80) {
 171         NVRAM->buffer[0x1FF7] = 0x00;
 172         NVRAM->buffer[0x1FFC] &= ~0x40;
 173         /* May it be a hw CPU Reset instead ? */
 174         qemu_system_reset_request();
 175     } else {
 176         qemu_set_irq(NVRAM->IRQ, 1);
 177         qemu_set_irq(NVRAM->IRQ, 0);
 178     }
 179 }
 180
 181 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 182 {
 183     uint64_t interval; /* in 1/16 seconds */
 184
 185     NVRAM->buffer[0x1FF0] &= ~0x80;
 186     if (NVRAM->wd_timer != NULL) {
 187         qemu_del_timer(NVRAM->wd_timer);
 188         if (value != 0) {
 189             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 190             qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 191                            ((interval * 1000) >> 4));
 192         }
 193     }
 194 }
 195
 196 /* Direct access to NVRAM */
 197 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     M48t59State *NVRAM = opaque;
 200     struct tm tm;
 201     int tmp;
 202
 203     if (addr > 0x1FF8 && addr < 0x2000)
 204         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 205
 206     /* check for NVRAM access */
 207     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 208         (NVRAM->model == 8 && addr < 0x1ff8) ||
 209         (NVRAM->model == 59 && addr < 0x1ff0)) {
 210         goto do_write;
 211     }
 212
 213     /* TOD access */
 214     switch (addr) {
 215     case 0x1FF0:
 216         /* flags register : read-only */
 217         break;
 218     case 0x1FF1:
 219         /* unused */
 220         break;
 221     case 0x1FF2:
 222         /* alarm seconds */
 223         tmp = from_bcd(val & 0x7F);
 224         if (tmp >= 0 && tmp <= 59) {
 225             NVRAM->alarm.tm_sec = tmp;
 226             NVRAM->buffer[0x1FF2] = val;
 227             set_alarm(NVRAM);
 228         }
 229         break;
 230     case 0x1FF3:
 231         /* alarm minutes */
 232         tmp = from_bcd(val & 0x7F);
 233         if (tmp >= 0 && tmp <= 59) {
 234             NVRAM->alarm.tm_min = tmp;
 235             NVRAM->buffer[0x1FF3] = val;
 236             set_alarm(NVRAM);
 237         }
 238         break;
 239     case 0x1FF4:
 240         /* alarm hours */
 241         tmp = from_bcd(val & 0x3F);
 242         if (tmp >= 0 && tmp <= 23) {
 243             NVRAM->alarm.tm_hour = tmp;
 244             NVRAM->buffer[0x1FF4] = val;
 245             set_alarm(NVRAM);
 246         }
 247         break;
 248     case 0x1FF5:
 249         /* alarm date */
 250         tmp = from_bcd(val & 0x3F);
 251         if (tmp != 0) {
 252             NVRAM->alarm.tm_mday = tmp;
 253             NVRAM->buffer[0x1FF5] = val;
 254             set_alarm(NVRAM);
 255         }
 256         break;
 257     case 0x1FF6:
 258         /* interrupts */
 259         NVRAM->buffer[0x1FF6] = val;
 260         break;
 261     case 0x1FF7:
 262         /* watchdog */
 263         NVRAM->buffer[0x1FF7] = val;
 264         set_up_watchdog(NVRAM, val);
 265         break;
 266     case 0x1FF8:
 267     case 0x07F8:
 268         /* control */
 269        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 270         break;
 271     case 0x1FF9:
 272     case 0x07F9:
 273         /* seconds (BCD) */
 274         tmp = from_bcd(val & 0x7F);
 275         if (tmp >= 0 && tmp <= 59) {
 276             get_time(NVRAM, &tm);
 277             tm.tm_sec = tmp;
 278             set_time(NVRAM, &tm);
 279         }
 280         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 281             if (val & 0x80) {
 282                 NVRAM->stop_time = time(NULL);
 283             } else {
 284                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 285                 NVRAM->stop_time = 0;
 286             }
 287         }
 288         NVRAM->buffer[addr] = val & 0x80;
 289         break;
 290     case 0x1FFA:
 291     case 0x07FA:
 292         /* minutes (BCD) */
 293         tmp = from_bcd(val & 0x7F);
 294         if (tmp >= 0 && tmp <= 59) {
 295             get_time(NVRAM, &tm);
 296             tm.tm_min = tmp;
 297             set_time(NVRAM, &tm);
 298         }
 299         break;
 300     case 0x1FFB:
 301     case 0x07FB:
 302         /* hours (BCD) */
 303         tmp = from_bcd(val & 0x3F);
 304         if (tmp >= 0 && tmp <= 23) {
 305             get_time(NVRAM, &tm);
 306             tm.tm_hour = tmp;
 307             set_time(NVRAM, &tm);
 308         }
 309         break;
 310     case 0x1FFC:
 311     case 0x07FC:
 312         /* day of the week / century */
 313         tmp = from_bcd(val & 0x07);
 314         get_time(NVRAM, &tm);
 315         tm.tm_wday = tmp;
 316         set_time(NVRAM, &tm);
 317         NVRAM->buffer[addr] = val & 0x40;
 318         break;
 319     case 0x1FFD:
 320     case 0x07FD:
 321         /* date (BCD) */
 322        tmp = from_bcd(val & 0x3F);
 323         if (tmp != 0) {
 324             get_time(NVRAM, &tm);
 325             tm.tm_mday = tmp;
 326             set_time(NVRAM, &tm);
 327         }
 328         break;
 329     case 0x1FFE:
 330     case 0x07FE:
 331         /* month */
 332         tmp = from_bcd(val & 0x1F);
 333         if (tmp >= 1 && tmp <= 12) {
 334             get_time(NVRAM, &tm);
 335             tm.tm_mon = tmp - 1;
 336             set_time(NVRAM, &tm);
 337         }
 338         break;
 339     case 0x1FFF:
 340     case 0x07FF:
 341         /* year */
 342         tmp = from_bcd(val);
 343         if (tmp >= 0 && tmp <= 99) {
 344             get_time(NVRAM, &tm);
 345             if (NVRAM->model == 8) {
 346                 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
 347             } else {
 348                 tm.tm_year = from_bcd(val);
 349             }
 350             set_time(NVRAM, &tm);
 351         }
 352         break;
 353     default:
 354         /* Check lock registers state */
 355         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 356             break;
 357         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 358             break;
 359     do_write:
 360         if (addr < NVRAM->size) {
 361             NVRAM->buffer[addr] = val & 0xFF;
 362         }
 363         break;
 364     }
 365 }
 366
 367 uint32_t m48t59_read (void *opaque, uint32_t addr)
 368 {
 369     M48t59State *NVRAM = opaque;
 370     struct tm tm;
 371     uint32_t retval = 0xFF;
 372
 373     /* check for NVRAM access */
 374     if ((NVRAM->model == 2 && addr < 0x078f) ||
 375         (NVRAM->model == 8 && addr < 0x1ff8) ||
 376         (NVRAM->model == 59 && addr < 0x1ff0)) {
 377         goto do_read;
 378     }
 379
 380     /* TOD access */
 381     switch (addr) {
 382     case 0x1FF0:
 383         /* flags register */
 384         goto do_read;
 385     case 0x1FF1:
 386         /* unused */
 387         retval = 0;
 388         break;
 389     case 0x1FF2:
 390         /* alarm seconds */
 391         goto do_read;
 392     case 0x1FF3:
 393         /* alarm minutes */
 394         goto do_read;
 395     case 0x1FF4:
 396         /* alarm hours */
 397         goto do_read;
 398     case 0x1FF5:
 399         /* alarm date */
 400         goto do_read;
 401     case 0x1FF6:
 402         /* interrupts */
 403         goto do_read;
 404     case 0x1FF7:
 405         /* A read resets the watchdog */
 406         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 407         goto do_read;
 408     case 0x1FF8:
 409     case 0x07F8:
 410         /* control */
 411         goto do_read;
 412     case 0x1FF9:
 413     case 0x07F9:
 414         /* seconds (BCD) */
 415         get_time(NVRAM, &tm);
 416         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 417         break;
 418     case 0x1FFA:
 419     case 0x07FA:
 420         /* minutes (BCD) */
 421         get_time(NVRAM, &tm);
 422         retval = to_bcd(tm.tm_min);
 423         break;
 424     case 0x1FFB:
 425     case 0x07FB:
 426         /* hours (BCD) */
 427         get_time(NVRAM, &tm);
 428         retval = to_bcd(tm.tm_hour);
 429         break;
 430     case 0x1FFC:
 431     case 0x07FC:
 432         /* day of the week / century */
 433         get_time(NVRAM, &tm);
 434         retval = NVRAM->buffer[addr] | tm.tm_wday;
 435         break;
 436     case 0x1FFD:
 437     case 0x07FD:
 438         /* date */
 439         get_time(NVRAM, &tm);
 440         retval = to_bcd(tm.tm_mday);
 441         break;
 442     case 0x1FFE:
 443     case 0x07FE:
 444         /* month */
 445         get_time(NVRAM, &tm);
 446         retval = to_bcd(tm.tm_mon + 1);
 447         break;
 448     case 0x1FFF:
 449     case 0x07FF:
 450         /* year */
 451         get_time(NVRAM, &tm);
 452         if (NVRAM->model == 8) {
 453             retval = to_bcd(tm.tm_year - 68); // Base year is 1968
 454         } else {
 455             retval = to_bcd(tm.tm_year);
 456         }
 457         break;
 458     default:
 459         /* Check lock registers state */
 460         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 461             break;
 462         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 463             break;
 464     do_read:
 465         if (addr < NVRAM->size) {
 466             retval = NVRAM->buffer[addr];
 467         }
 468         break;
 469     }
 470     if (addr > 0x1FF9 && addr < 0x2000)
 471        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 472
 473     return retval;
 474 }
 475
 476 void m48t59_toggle_lock (void *opaque, int lock)
 477 {
 478     M48t59State *NVRAM = opaque;
 479
 480     NVRAM->lock ^= 1 << lock;
 481 }
 482
 483 /* IO access to NVRAM */
 484 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 485                          unsigned size)
 486 {
 487     M48t59State *NVRAM = opaque;
 488
 489     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 490     switch (addr) {
 491     case 0:
 492         NVRAM->addr &= ~0x00FF;
 493         NVRAM->addr |= val;
 494         break;
 495     case 1:
 496         NVRAM->addr &= ~0xFF00;
 497         NVRAM->addr |= val << 8;
 498         break;
 499     case 3:
 500         m48t59_write(NVRAM, NVRAM->addr, val);
 501         NVRAM->addr = 0x0000;
 502         break;
 503     default:
 504         break;
 505     }
 506 }
 507
 508 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 509 {
 510     M48t59State *NVRAM = opaque;
 511     uint32_t retval;
 512
 513     switch (addr) {
 514     case 3:
 515         retval = m48t59_read(NVRAM, NVRAM->addr);
 516         break;
 517     default:
 518         retval = -1;
 519         break;
 520     }
 521     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 522
 523     return retval;
 524 }
 525
 526 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
 527 {
 528     M48t59State *NVRAM = opaque;
 529
 530     m48t59_write(NVRAM, addr, value & 0xff);
 531 }
 532
 533 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
 534 {
 535     M48t59State *NVRAM = opaque;
 536
 537     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 538     m48t59_write(NVRAM, addr + 1, value & 0xff);
 539 }
 540
 541 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
 542 {
 543     M48t59State *NVRAM = opaque;
 544
 545     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 546     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 547     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 548     m48t59_write(NVRAM, addr + 3, value & 0xff);
 549 }
 550
 551 static uint32_t nvram_readb (void *opaque, hwaddr addr)
 552 {
 553     M48t59State *NVRAM = opaque;
 554     uint32_t retval;
 555
 556     retval = m48t59_read(NVRAM, addr);
 557     return retval;
 558 }
 559
 560 static uint32_t nvram_readw (void *opaque, hwaddr addr)
 561 {
 562     M48t59State *NVRAM = opaque;
 563     uint32_t retval;
 564
 565     retval = m48t59_read(NVRAM, addr) << 8;
 566     retval |= m48t59_read(NVRAM, addr + 1);
 567     return retval;
 568 }
 569
 570 static uint32_t nvram_readl (void *opaque, hwaddr addr)
 571 {
 572     M48t59State *NVRAM = opaque;
 573     uint32_t retval;
 574
 575     retval = m48t59_read(NVRAM, addr) << 24;
 576     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 577     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 578     retval |= m48t59_read(NVRAM, addr + 3);
 579     return retval;
 580 }
 581
 582 static const MemoryRegionOps nvram_ops = {
 583     .old_mmio = {
 584         .read = { nvram_readb, nvram_readw, nvram_readl, },
 585         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 586     },
 587     .endianness = DEVICE_NATIVE_ENDIAN,
 588 };
 589
 590 static const VMStateDescription vmstate_m48t59 = {
 591     .name = "m48t59",
 592     .version_id = 1,
 593     .minimum_version_id = 1,
 594     .minimum_version_id_old = 1,
 595     .fields      = (VMStateField[]) {
 596         VMSTATE_UINT8(lock, M48t59State),
 597         VMSTATE_UINT16(addr, M48t59State),
 598         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 599         VMSTATE_END_OF_LIST()
 600     }
 601 };
 602
 603 static void m48t59_reset_common(M48t59State *NVRAM)
 604 {
 605     NVRAM->addr = 0;
 606     NVRAM->lock = 0;
 607     if (NVRAM->alrm_timer != NULL)
 608         qemu_del_timer(NVRAM->alrm_timer);
 609
 610     if (NVRAM->wd_timer != NULL)
 611         qemu_del_timer(NVRAM->wd_timer);
 612 }
 613
 614 static void m48t59_reset_isa(DeviceState *d)
 615 {
 616     M48t59ISAState *isa = ISA_M48T59(d);
 617     M48t59State *NVRAM = &isa->state;
 618
 619     m48t59_reset_common(NVRAM);
 620 }
 621
 622 static void m48t59_reset_sysbus(DeviceState *d)
 623 {
 624     M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
 625     M48t59State *NVRAM = &sys->state;
 626
 627     m48t59_reset_common(NVRAM);
 628 }
 629
 630 static const MemoryRegionOps m48t59_io_ops = {
 631     .read = NVRAM_readb,
 632     .write = NVRAM_writeb,
 633     .impl = {
 634         .min_access_size = 1,
 635         .max_access_size = 1,
 636     },
 637     .endianness = DEVICE_LITTLE_ENDIAN,
 638 };
 639
 640 /* Initialisation routine */
 641 M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 642                          uint32_t io_base, uint16_t size, int model)
 643 {
 644     DeviceState *dev;
 645     SysBusDevice *s;
 646     M48t59SysBusState *d;
 647     M48t59State *state;
 648
 649     dev = qdev_create(NULL, "m48t59");
 650     qdev_prop_set_uint32(dev, "model", model);
 651     qdev_prop_set_uint32(dev, "size", size);
 652     qdev_prop_set_uint32(dev, "io_base", io_base);
 653     qdev_init_nofail(dev);
 654     s = SYS_BUS_DEVICE(dev);
 655     d = FROM_SYSBUS(M48t59SysBusState, s);
 656     state = &d->state;
 657     sysbus_connect_irq(s, 0, IRQ);
 658     memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state,
 659                           "m48t59", 4);
 660     if (io_base != 0) {
 661         memory_region_add_subregion(get_system_io(), io_base, &d->io);
 662     }
 663     if (mem_base != 0) {
 664         sysbus_mmio_map(s, 0, mem_base);
 665     }
 666
 667     return state;
 668 }
 669
 670 M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
 671                              int model)
 672 {
 673     M48t59ISAState *d;
 674     ISADevice *isadev;
 675     DeviceState *dev;
 676     M48t59State *s;
 677
 678     isadev = isa_create(bus, TYPE_ISA_M48T59);
 679     dev = DEVICE(isadev);
 680     qdev_prop_set_uint32(dev, "model", model);
 681     qdev_prop_set_uint32(dev, "size", size);
 682     qdev_prop_set_uint32(dev, "io_base", io_base);
 683     qdev_init_nofail(dev);
 684     d = ISA_M48T59(isadev);
 685     s = &d->state;
 686
 687     memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4);
 688     if (io_base != 0) {
 689         isa_register_ioport(isadev, &d->io, io_base);
 690     }
 691
 692     return s;
 693 }
 694
 695 static void m48t59_realize_common(M48t59State *s, Error **errp)
 696 {
 697     s->buffer = g_malloc0(s->size);
 698     if (s->model == 59) {
 699         s->alrm_timer = qemu_new_timer_ns(rtc_clock, &alarm_cb, s);
 700         s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
 701     }
 702     qemu_get_timedate(&s->alarm, 0);
 703
 704     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 705 }
 706
 707 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 708 {
 709     ISADevice *isadev = ISA_DEVICE(dev);
 710     M48t59ISAState *d = ISA_M48T59(dev);
 711     M48t59State *s = &d->state;
 712
 713     isa_init_irq(isadev, &s->IRQ, 8);
 714     m48t59_realize_common(s, errp);
 715 }
 716
 717 static int m48t59_init1(SysBusDevice *dev)
 718 {
 719     M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
 720     M48t59State *s = &d->state;
 721     Error *err = NULL;
 722
 723     sysbus_init_irq(dev, &s->IRQ);
 724
 725     memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s,
 726                           "m48t59.nvram", s->size);
 727     sysbus_init_mmio(dev, &s->iomem);
 728     m48t59_realize_common(s, &err);
 729     if (err != NULL) {
 730         error_free(err);
 731         return -1;
 732     }
 733
 734     return 0;
 735 }
 736
 737 static Property m48t59_isa_properties[] = {
 738     DEFINE_PROP_UINT32("size",    M48t59ISAState, state.size,    -1),
 739     DEFINE_PROP_UINT32("model",   M48t59ISAState, state.model,   -1),
 740     DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base,  0),
 741     DEFINE_PROP_END_OF_LIST(),
 742 };
 743
 744 static void m48t59_isa_class_init(ObjectClass *klass, void *data)
 745 {
 746     DeviceClass *dc = DEVICE_CLASS(klass);
 747
 748     dc->realize = m48t59_isa_realize;
 749     dc->no_user = 1;
 750     dc->reset = m48t59_reset_isa;
 751     dc->props = m48t59_isa_properties;
 752 }
 753
 754 static const TypeInfo m48t59_isa_info = {
 755     .name          = TYPE_ISA_M48T59,
 756     .parent        = TYPE_ISA_DEVICE,
 757     .instance_size = sizeof(M48t59ISAState),
 758     .class_init    = m48t59_isa_class_init,
 759 };
 760
 761 static Property m48t59_properties[] = {
 762     DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),
 763     DEFINE_PROP_UINT32("model",   M48t59SysBusState, state.model,   -1),
 764     DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),
 765     DEFINE_PROP_END_OF_LIST(),
 766 };
 767
 768 static void m48t59_class_init(ObjectClass *klass, void *data)
 769 {
 770     DeviceClass *dc = DEVICE_CLASS(klass);
 771     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 772
 773     k->init = m48t59_init1;
 774     dc->reset = m48t59_reset_sysbus;
 775     dc->props = m48t59_properties;
 776 }
 777
 778 static const TypeInfo m48t59_info = {
 779     .name          = "m48t59",
 780     .parent        = TYPE_SYS_BUS_DEVICE,
 781     .instance_size = sizeof(M48t59SysBusState),
 782     .class_init    = m48t59_class_init,
 783 };
 784
 785 static void m48t59_register_types(void)
 786 {
 787     type_register_static(&m48t59_info);
 788     type_register_static(&m48t59_isa_info);
 789 }
 790
 791 type_init(m48t59_register_types)