hw/timer/puv3_ost.c

   1 /*
   2  * OSTimer device simulation in PKUnity SoC
   3  *
   4  * Copyright (C) 2010-2012 Guan Xuetao
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation, or any later version.
   9  * See the COPYING file in the top-level directory.
  10  */
  11 #include "hw/sysbus.h"
  12 #include "hw/ptimer.h"
  13
  14 #undef DEBUG_PUV3
  15 #include "hw/unicore32/puv3.h"
  16
  17 #define TYPE_PUV3_OST "puv3_ost"
  18 #define PUV3_OST(obj) OBJECT_CHECK(PUV3OSTState, (obj), TYPE_PUV3_OST)
  19
  20 /* puv3 ostimer implementation. */
  21 typedef struct PUV3OSTState {
  22     SysBusDevice parent_obj;
  23
  24     MemoryRegion iomem;
  25     QEMUBH *bh;
  26     qemu_irq irq;
  27     ptimer_state *ptimer;
  28
  29     uint32_t reg_OSMR0;
  30     uint32_t reg_OSCR;
  31     uint32_t reg_OSSR;
  32     uint32_t reg_OIER;
  33 } PUV3OSTState;
  34
  35 static uint64_t puv3_ost_read(void *opaque, hwaddr offset,
  36         unsigned size)
  37 {
  38     PUV3OSTState *s = opaque;
  39     uint32_t ret = 0;
  40
  41     switch (offset) {
  42     case 0x10: /* Counter Register */
  43         ret = s->reg_OSMR0 - (uint32_t)ptimer_get_count(s->ptimer);
  44         break;
  45     case 0x14: /* Status Register */
  46         ret = s->reg_OSSR;
  47         break;
  48     case 0x1c: /* Interrupt Enable Register */
  49         ret = s->reg_OIER;
  50         break;
  51     default:
  52         DPRINTF("Bad offset %x\n", (int)offset);
  53     }
  54     DPRINTF("offset 0x%x, value 0x%x\n", offset, ret);
  55     return ret;
  56 }
  57
  58 static void puv3_ost_write(void *opaque, hwaddr offset,
  59         uint64_t value, unsigned size)
  60 {
  61     PUV3OSTState *s = opaque;
  62
  63     DPRINTF("offset 0x%x, value 0x%x\n", offset, value);
  64     switch (offset) {
  65     case 0x00: /* Match Register 0 */
  66         s->reg_OSMR0 = value;
  67         if (s->reg_OSMR0 > s->reg_OSCR) {
  68             ptimer_set_count(s->ptimer, s->reg_OSMR0 - s->reg_OSCR);
  69         } else {
  70             ptimer_set_count(s->ptimer, s->reg_OSMR0 +
  71                     (0xffffffff - s->reg_OSCR));
  72         }
  73         ptimer_run(s->ptimer, 2);
  74         break;
  75     case 0x14: /* Status Register */
  76         assert(value == 0);
  77         if (s->reg_OSSR) {
  78             s->reg_OSSR = value;
  79             qemu_irq_lower(s->irq);
  80         }
  81         break;
  82     case 0x1c: /* Interrupt Enable Register */
  83         s->reg_OIER = value;
  84         break;
  85     default:
  86         DPRINTF("Bad offset %x\n", (int)offset);
  87     }
  88 }
  89
  90 static const MemoryRegionOps puv3_ost_ops = {
  91     .read = puv3_ost_read,
  92     .write = puv3_ost_write,
  93     .impl = {
  94         .min_access_size = 4,
  95         .max_access_size = 4,
  96     },
  97     .endianness = DEVICE_NATIVE_ENDIAN,
  98 };
  99
 100 static void puv3_ost_tick(void *opaque)
 101 {
 102     PUV3OSTState *s = opaque;
 103
 104     DPRINTF("ost hit when ptimer counter from 0x%x to 0x%x!\n",
 105             s->reg_OSCR, s->reg_OSMR0);
 106
 107     s->reg_OSCR = s->reg_OSMR0;
 108     if (s->reg_OIER) {
 109         s->reg_OSSR = 1;
 110         qemu_irq_raise(s->irq);
 111     }
 112 }
 113
 114 static int puv3_ost_init(SysBusDevice *dev)
 115 {
 116     PUV3OSTState *s = PUV3_OST(dev);
 117
 118     s->reg_OIER = 0;
 119     s->reg_OSSR = 0;
 120     s->reg_OSMR0 = 0;
 121     s->reg_OSCR = 0;
 122
 123     sysbus_init_irq(dev, &s->irq);
 124
 125     s->bh = qemu_bh_new(puv3_ost_tick, s);
 126     s->ptimer = ptimer_init(s->bh);
 127     ptimer_set_freq(s->ptimer, 50 * 1000 * 1000);
 128
 129     memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
 130             PUV3_REGS_OFFSET);
 131     sysbus_init_mmio(dev, &s->iomem);
 132
 133     return 0;
 134 }
 135
 136 static void puv3_ost_class_init(ObjectClass *klass, void *data)
 137 {
 138     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 139
 140     sdc->init = puv3_ost_init;
 141 }
 142
 143 static const TypeInfo puv3_ost_info = {
 144     .name = TYPE_PUV3_OST,
 145     .parent = TYPE_SYS_BUS_DEVICE,
 146     .instance_size = sizeof(PUV3OSTState),
 147     .class_init = puv3_ost_class_init,
 148 };
 149
 150 static void puv3_ost_register_type(void)
 151 {
 152     type_register_static(&puv3_ost_info);
 153 }
 154
 155 type_init(puv3_ost_register_type)