hw/timer/sh_timer.c

   1 /*
   2  * SuperH Timer modules.
   3  *
   4  * Copyright (c) 2007 Magnus Damm
   5  * Based on arm_timer.c by Paul Brook
   6  * Copyright (c) 2005-2006 CodeSourcery.
   7  *
   8  * This code is licensed under the GPL.
   9  */
  10
  11 #include "hw/hw.h"
  12 #include "hw/sh4/sh.h"
  13 #include "qemu/timer.h"
  14 #include "qemu/main-loop.h"
  15 #include "exec/address-spaces.h"
  16 #include "hw/ptimer.h"
  17
  18 //#define DEBUG_TIMER
  19
  20 #define TIMER_TCR_TPSC          (7 << 0)
  21 #define TIMER_TCR_CKEG          (3 << 3)
  22 #define TIMER_TCR_UNIE          (1 << 5)
  23 #define TIMER_TCR_ICPE          (3 << 6)
  24 #define TIMER_TCR_UNF           (1 << 8)
  25 #define TIMER_TCR_ICPF          (1 << 9)
  26 #define TIMER_TCR_RESERVED      (0x3f << 10)
  27
  28 #define TIMER_FEAT_CAPT   (1 << 0)
  29 #define TIMER_FEAT_EXTCLK (1 << 1)
  30
  31 #define OFFSET_TCOR   0
  32 #define OFFSET_TCNT   1
  33 #define OFFSET_TCR    2
  34 #define OFFSET_TCPR   3
  35
  36 typedef struct {
  37     ptimer_state *timer;
  38     uint32_t tcnt;
  39     uint32_t tcor;
  40     uint32_t tcr;
  41     uint32_t tcpr;
  42     int freq;
  43     int int_level;
  44     int old_level;
  45     int feat;
  46     int enabled;
  47     qemu_irq irq;
  48 } sh_timer_state;
  49
  50 /* Check all active timers, and schedule the next timer interrupt. */
  51
  52 static void sh_timer_update(sh_timer_state *s)
  53 {
  54     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
  55
  56     if (new_level != s->old_level)
  57       qemu_set_irq (s->irq, new_level);
  58
  59     s->old_level = s->int_level;
  60     s->int_level = new_level;
  61 }
  62
  63 static uint32_t sh_timer_read(void *opaque, hwaddr offset)
  64 {
  65     sh_timer_state *s = (sh_timer_state *)opaque;
  66
  67     switch (offset >> 2) {
  68     case OFFSET_TCOR:
  69         return s->tcor;
  70     case OFFSET_TCNT:
  71         return ptimer_get_count(s->timer);
  72     case OFFSET_TCR:
  73         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
  74     case OFFSET_TCPR:
  75         if (s->feat & TIMER_FEAT_CAPT)
  76             return s->tcpr;
  77     default:
  78         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
  79         return 0;
  80     }
  81 }
  82
  83 static void sh_timer_write(void *opaque, hwaddr offset,
  84                             uint32_t value)
  85 {
  86     sh_timer_state *s = (sh_timer_state *)opaque;
  87     int freq;
  88
  89     switch (offset >> 2) {
  90     case OFFSET_TCOR:
  91         s->tcor = value;
  92         ptimer_set_limit(s->timer, s->tcor, 0);
  93         break;
  94     case OFFSET_TCNT:
  95         s->tcnt = value;
  96         ptimer_set_count(s->timer, s->tcnt);
  97         break;
  98     case OFFSET_TCR:
  99         if (s->enabled) {
 100             /* Pause the timer if it is running.  This may cause some
 101                inaccuracy dure to rounding, but avoids a whole lot of other
 102                messyness.  */
 103             ptimer_stop(s->timer);
 104         }
 105         freq = s->freq;
 106         /* ??? Need to recalculate expiry time after changing divisor.  */
 107         switch (value & TIMER_TCR_TPSC) {
 108         case 0: freq >>= 2; break;
 109         case 1: freq >>= 4; break;
 110         case 2: freq >>= 6; break;
 111         case 3: freq >>= 8; break;
 112         case 4: freq >>= 10; break;
 113         case 6:
 114         case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
 115         default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
 116         }
 117         switch ((value & TIMER_TCR_CKEG) >> 3) {
 118         case 0: break;
 119         case 1:
 120         case 2:
 121         case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
 122         default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
 123         }
 124         switch ((value & TIMER_TCR_ICPE) >> 6) {
 125         case 0: break;
 126         case 2:
 127         case 3: if (s->feat & TIMER_FEAT_CAPT) break;
 128         default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
 129         }
 130         if ((value & TIMER_TCR_UNF) == 0)
 131             s->int_level = 0;
 132
 133         value &= ~TIMER_TCR_UNF;
 134
 135         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
 136             hw_error("sh_timer_write: Reserved ICPF value\n");
 137
 138         value &= ~TIMER_TCR_ICPF; /* capture not supported */
 139
 140         if (value & TIMER_TCR_RESERVED)
 141             hw_error("sh_timer_write: Reserved TCR bits set\n");
 142         s->tcr = value;
 143         ptimer_set_limit(s->timer, s->tcor, 0);
 144         ptimer_set_freq(s->timer, freq);
 145         if (s->enabled) {
 146             /* Restart the timer if still enabled.  */
 147             ptimer_run(s->timer, 0);
 148         }
 149         break;
 150     case OFFSET_TCPR:
 151         if (s->feat & TIMER_FEAT_CAPT) {
 152             s->tcpr = value;
 153             break;
 154         }
 155     default:
 156         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
 157     }
 158     sh_timer_update(s);
 159 }
 160
 161 static void sh_timer_start_stop(void *opaque, int enable)
 162 {
 163     sh_timer_state *s = (sh_timer_state *)opaque;
 164
 165 #ifdef DEBUG_TIMER
 166     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
 167 #endif
 168
 169     if (s->enabled && !enable) {
 170         ptimer_stop(s->timer);
 171     }
 172     if (!s->enabled && enable) {
 173         ptimer_run(s->timer, 0);
 174     }
 175     s->enabled = !!enable;
 176
 177 #ifdef DEBUG_TIMER
 178     printf("sh_timer_start_stop done %d\n", s->enabled);
 179 #endif
 180 }
 181
 182 static void sh_timer_tick(void *opaque)
 183 {
 184     sh_timer_state *s = (sh_timer_state *)opaque;
 185     s->int_level = s->enabled;
 186     sh_timer_update(s);
 187 }
 188
 189 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
 190 {
 191     sh_timer_state *s;
 192     QEMUBH *bh;
 193
 194     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
 195     s->freq = freq;
 196     s->feat = feat;
 197     s->tcor = 0xffffffff;
 198     s->tcnt = 0xffffffff;
 199     s->tcpr = 0xdeadbeef;
 200     s->tcr = 0;
 201     s->enabled = 0;
 202     s->irq = irq;
 203
 204     bh = qemu_bh_new(sh_timer_tick, s);
 205     s->timer = ptimer_init(bh);
 206
 207     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
 208     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
 209     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
 210     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
 211     /* ??? Save/restore.  */
 212     return s;
 213 }
 214
 215 typedef struct {
 216     MemoryRegion iomem;
 217     MemoryRegion iomem_p4;
 218     MemoryRegion iomem_a7;
 219     void *timer[3];
 220     int level[3];
 221     uint32_t tocr;
 222     uint32_t tstr;
 223     int feat;
 224 } tmu012_state;
 225
 226 static uint64_t tmu012_read(void *opaque, hwaddr offset,
 227                             unsigned size)
 228 {
 229     tmu012_state *s = (tmu012_state *)opaque;
 230
 231 #ifdef DEBUG_TIMER
 232     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
 233 #endif
 234
 235     if (offset >= 0x20) {
 236         if (!(s->feat & TMU012_FEAT_3CHAN))
 237             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 238         return sh_timer_read(s->timer[2], offset - 0x20);
 239     }
 240
 241     if (offset >= 0x14)
 242         return sh_timer_read(s->timer[1], offset - 0x14);
 243
 244     if (offset >= 0x08)
 245         return sh_timer_read(s->timer[0], offset - 0x08);
 246
 247     if (offset == 4)
 248         return s->tstr;
 249
 250     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
 251         return s->tocr;
 252
 253     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
 254     return 0;
 255 }
 256
 257 static void tmu012_write(void *opaque, hwaddr offset,
 258                         uint64_t value, unsigned size)
 259 {
 260     tmu012_state *s = (tmu012_state *)opaque;
 261
 262 #ifdef DEBUG_TIMER
 263     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
 264 #endif
 265
 266     if (offset >= 0x20) {
 267         if (!(s->feat & TMU012_FEAT_3CHAN))
 268             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
 269         sh_timer_write(s->timer[2], offset - 0x20, value);
 270         return;
 271     }
 272
 273     if (offset >= 0x14) {
 274         sh_timer_write(s->timer[1], offset - 0x14, value);
 275         return;
 276     }
 277
 278     if (offset >= 0x08) {
 279         sh_timer_write(s->timer[0], offset - 0x08, value);
 280         return;
 281     }
 282
 283     if (offset == 4) {
 284         sh_timer_start_stop(s->timer[0], value & (1 << 0));
 285         sh_timer_start_stop(s->timer[1], value & (1 << 1));
 286         if (s->feat & TMU012_FEAT_3CHAN)
 287             sh_timer_start_stop(s->timer[2], value & (1 << 2));
 288         else
 289             if (value & (1 << 2))
 290                 hw_error("tmu012_write: Bad channel\n");
 291
 292         s->tstr = value;
 293         return;
 294     }
 295
 296     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
 297         s->tocr = value & (1 << 0);
 298     }
 299 }
 300
 301 static const MemoryRegionOps tmu012_ops = {
 302     .read = tmu012_read,
 303     .write = tmu012_write,
 304     .endianness = DEVICE_NATIVE_ENDIAN,
 305 };
 306
 307 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
 308                  int feat, uint32_t freq,
 309                  qemu_irq ch0_irq, qemu_irq ch1_irq,
 310                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
 311 {
 312     tmu012_state *s;
 313     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 314
 315     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
 316     s->feat = feat;
 317     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
 318     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
 319     if (feat & TMU012_FEAT_3CHAN)
 320         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
 321                                     ch2_irq0); /* ch2_irq1 not supported */
 322
 323     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
 324                           "timer", 0x100000000ULL);
 325
 326     memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
 327                              &s->iomem, 0, 0x1000);
 328     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
 329
 330     memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
 331                              &s->iomem, 0, 0x1000);
 332     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
 333     /* ??? Save/restore.  */
 334 }